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32 lines
1.7 KiB
Plaintext
32 lines
1.7 KiB
Plaintext
=========================================================
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======================== PROCESSOR INFO =================
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=========================================================
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The SH4 can dual issue (i.e. parallel execution) two instructions
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as long as the groups of the two instructions are different:
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* LS - most ALU and FPU register load/stores
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* EX - most ALU arithmetic instructions
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* MT - TST, CMP, NOP, MOV Rm,Rn (NOTE: Can execute in parallel with other MT)
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* FE - most FPU arithmetic instructions
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* CO - other instructions (NOTE: Cannot never execute in parallel)
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The following general aspects of instructions are important to note per the SH4 manual:
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* Issue rate: Interval between the issue of an instruction and that of the next instruction
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* Latency: Interval between the issue of an instruction and the generation of its result (completion)
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* Latency is also the interval between the execution of two instructions with an interdependent relationship.
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(although different cases may either increase or decrease Latency)
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=========================================================
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======================== REGISTER USAGES ================
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=========================================================
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SH4 C ABI:
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- R0 to R3 are return values (can be overwritten)
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- R4 to R7 are input arguments (can be overwritten)
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- R8 to R13 are non-volatile (must be restored at end)
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- R14 is the frame pointer (must be restored at end)
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- R15 is the stack pointer (must be restored at end)
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- FR0 to FR3 are return values (can be overwritten)
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- FR4 to FR11 are input arguments (can be overwritten)
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- FR12 to FR13 are non-volatile (must be restored at end)
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