<!-- if a clockGenerator is given, this config needs to create the required source code -->
<toolchain name="VerilogClockExample" clockGenerator="clockGenerator">
    <commands>
        <command name="Export" requires="verilog"/>
    </commands>
    <params>
        <!-- used by the Vivado project template -->
        <param name="chip">xc7a35ticpg236-1L</param>
    </params>
    <files>
        <file name="clockGenerator.v" overwrite="true" filter="true">
            <content><![CDATA[<?
    // Add the board specific clock generation here!
    // This example assumes a 100MHz clock and creates a simple clock divider to
    // match the input clock frequency given in the circuit.
    // The variable model.frequency holds the frequency selected in the circuits
    // clock component.

    board_frequency := 100000000; // assuming a 100MHz clock

    maxCounter := board_frequency/model.frequency/2;
    bits := bitsNeededFor(maxCounter);

?>module clockGenerator
(
    input cin,
    output cout
);
 /*
  * Don't use a logic signal as clock source in a real world application!
  * Use the on chip clock resources instead!
  */
  reg [<?=bits-1?>:0] counter;
  reg state;

  assign cout = state;

  always @ (posedge cin) begin
       if (counter == <?=maxCounter?>) begin
            counter <= 0;
            state <= ~state;
       end
       else begin
          counter <= counter + 1;
       end
  end

endmodule
]]></content>
        </file>
        <!-- creates a vivado project file which simplifies testing -->
        <file name="vivado/&lt;?=shortname?&gt;.xpr" overwrite="false" filter="true" lookAt="BASYS3.config" ref="vivado"/>
    </files>
</toolchain>
