<? if (isPresent(elem.clockGenerator)) {?>
LIBRARY ieee;
USE ieee.std_logic_1164.all;

entity DIG_simpleClockDivider is
  port (
    cout: out std_logic;
    cin: in std_logic );
end DIG_simpleClockDivider;

architecture Behavioral of DIG_simpleClockDivider is
  component <?=elem.clockGenerator?> is
    port(
      cout: out std_logic;
      cin: in std_logic );
  end component <?=elem.clockGenerator?>;
begin
clock: component <?=elem.clockGenerator?>
    port map(
        cin => cin,
        cout => cout
    );
end Behavioral;
<? } else {?>LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;

entity DIG_simpleClockDivider is
  generic (
    maxCounter : integer );  <? vhdl.registerGeneric("maxCounter");?>
  port (
    cout: out std_logic;
    cin: in std_logic );
end DIG_simpleClockDivider;

architecture Behavioral of DIG_simpleClockDivider is
  -- Don't use a logic signal as clock source in a real world application!
  -- Use the on chip clock resources instead!
  signal counter: integer range 0 to maxCounter := 0;
  signal state: std_logic;
begin
  process (cin)
  begin
    if rising_edge(cin) then
       if counter = maxCounter then
          counter <= 0;
          state <= NOT (state);
       else
          counter <= counter+1;
       end if;
    end if;
  end process;
  cout <= state;
end Behavioral;
<? } ?>