LIBRARY ieee;
USE ieee.std_logic_1164.all;
<?
  if (elem.Bits=1)
      export entityName:="DIG_D_FF";
  else {
      export entityName:="DIG_D_FF_BUS";
      print("use ieee.numeric_std.all;");
  }
?>
entity <?=entityName?> is
  generic (<?if (elem.Bits>1) {?>
    Default: integer; <? vhdl.registerGeneric("Default");?>
    Bits: integer );<? vhdl.registerGeneric("Bits"); }
  else {?>
    Default: std_logic ); <? vhdl.registerGeneric("Default", "std_logic");}?>
  port ( D  : in <?= vhdl.genericType(elem.Bits)?>;
         C  : in std_logic;
         Q  : out <?= vhdl.genericType(elem.Bits)?>;
         notQ : out <?= vhdl.genericType(elem.Bits)?> );
end <?=entityName?>;

architecture Behavioral of <?=entityName?> is
   signal state : <?= vhdl.genericType(elem.Bits)?> := <?if (elem.Bits>1) {?>std_logic_vector(to_unsigned(Default, Bits))<?} else {?>Default<? }?>;
begin
   Q    <= state;
   notQ <= NOT( state );

   process(C)
   begin
      if rising_edge(C) then
        state  <= D;
      end if;
   end process;
end Behavioral;