LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

<?
  if (elem.Signed)
      export entityName:="DIG_Mul_signed";
  else
      export entityName:="DIG_Mul_unsigned";
?>

entity <?=entityName?> is
  generic ( Bits: integer ); <? vhdl.registerGeneric("Bits");?>
  port (
    a: in std_logic_vector ((Bits-1) downto 0);
    b: in std_logic_vector ((Bits-1) downto 0);
    mul: out std_logic_vector ((Bits*2-1) downto 0) );
end <?=entityName?>;

architecture Behavioral of <?=entityName?> is
begin
    <? if (elem.Signed) {?>
    mul <= std_logic_vector(signed(a) * signed(b));
    <? } else { ?>
    mul <= std_logic_vector(unsigned(a) * unsigned(b));
    <? } ?>
end Behavioral;