LIBRARY ieee;
USE ieee.std_logic_1164.all;
<?
  if (elem.Bits=1)
      export entityName:="DIG_Register";
  else
      export entityName:="DIG_Register_BUS";
?>
entity <?=entityName?> is
  <? if (elem.Bits>1) {?>generic ( Bits: integer ); <? vhdl.registerGeneric("Bits"); }?>
  port (
    Q: out <?= vhdl.genericType(elem.Bits)?>;
    D: in <?= vhdl.genericType(elem.Bits)?>;
    C: in std_logic;
    en: in std_logic );
end <?=entityName?>;

architecture Behavioral of <?=entityName?> is
  signal state : <?= vhdl.genericType(elem.Bits)?> := <?= vhdl.zero(elem.Bits)?>;
begin
   Q <= state;

   process ( C )
   begin
      if rising_edge(C) and (en='1') then
        state <= D;
      end if;
   end process;
end Behavioral;