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improved integration of java methods

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This commit is contained in:
hneemann 2018-03-18 00:39:23 +01:00
parent df04d51920
commit 0161e7e562
33 changed files with 519 additions and 489 deletions
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27
src/main/java/de/neemann/digital/hdl/hgs/Context.java
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@ -8,7 +8,6 @@ package de.neemann.digital.hdl.hgs;
import de.neemann.digital.hdl.hgs.function.Func;
import de.neemann.digital.hdl.hgs.function.Function;
import de.neemann.digital.hdl.hgs.function.InnerFunction;
import de.neemann.digital.hdl.hgs.function.JavaMethod;
import java.util.ArrayList;
import java.util.HashMap;
@ -153,32 +152,6 @@ public class Context {
return declareVar(name, func);
}
/**
* Adds a static java method to the context.
* The method can then be called from the template code.
*
* @param name the name
* @param clazz the class of the method
* @return this for chained calls
* @throws HGSEvalException HGSEvalException
*/
public Context declareStaticMethod(String name, Class clazz) throws HGSEvalException {
return declareFunc(name, JavaMethod.create(clazz, name));
}
/**
* Adds a non static java method to the context.
* The method can then be called from the template code.
*
* @param name the name
* @param instance the instance to call the method on
* @return this for chained calls
* @throws HGSEvalException HGSEvalException
*/
public Context declareMethod(String name, Object instance) throws HGSEvalException {
return declareFunc(name, JavaMethod.create(instance, name));
}
/**
* Prints code to the context
*

154
src/main/java/de/neemann/digital/hdl/hgs/function/JavaClass.java Normal file
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@ -0,0 +1,154 @@
/*
* Copyright (c) 2018 Helmut Neemann.
* Use of this source code is governed by the GPL v3 license
* that can be found in the LICENSE file.
*/
package de.neemann.digital.hdl.hgs.function;
import de.neemann.digital.hdl.hgs.Context;
import de.neemann.digital.hdl.hgs.Expression;
import de.neemann.digital.hdl.hgs.HGSEvalException;
import de.neemann.digital.hdl.hgs.HGSMap;
import java.lang.reflect.InvocationTargetException;
import java.lang.reflect.Method;
import java.lang.reflect.Modifier;
import java.util.ArrayList;
import java.util.HashMap;
/**
* Used to call a java function from the template code.
* Uses reflection to invoke the method;
*
* @param <T> the type of the instance
*/
public final class JavaClass<T> {
private final HashMap<String, MyMethod<T>> methods;
/**
* Creates a new instance
*
* @param clazz the class
*/
public JavaClass(Class<T> clazz) {
methods = new HashMap<>();
for (Method m : clazz.getDeclaredMethods()) {
int mod = m.getModifiers();
if (Modifier.isPublic(mod))
methods.put(m.getName(), new MyMethod<>(m, Modifier.isStatic(mod)));
}
}
/**
* Creates the method map
*
* @param instance the instance to call
* @return the method map
*/
public HGSMap createMap(T instance) {
return new MethodMap<>(this, instance);
}
private static final class MyMethod<T> {
private final Method method;
private final boolean isStatic;
private final boolean addContext;
private final int argCount;
private final int javaArgCount;
private final boolean isVarArgs;
private MyMethod(Method method, boolean isStatic) {
this.method = method;
this.isStatic = isStatic;
Class<?>[] argTypes = method.getParameterTypes();
javaArgCount = argTypes.length;
addContext = (argTypes.length > 0 && argTypes[0].isAssignableFrom(Context.class));
isVarArgs = method.isVarArgs();
if (isVarArgs) {
argCount = -1;
} else {
if (addContext)
argCount = argTypes.length - 1;
else
argCount = argTypes.length;
}
}
private Object call(T instance, Context c, ArrayList<Expression> args) throws HGSEvalException {
if (instance == null && !isStatic)
throw new HGSEvalException("function " + method.getName() + " is not static!");
if (argCount >= 0 && argCount != args.size())
throw new HGSEvalException("wrong number of arguments! expected: " + argCount + ", but found:" + args.size());
Object[] a = new Object[javaArgCount];
int i = 0;
if (addContext) {
a[0] = c;
i++;
}
if (!isVarArgs) {
for (Expression exp : args) {
a[i] = exp.value(c);
i++;
}
} else {
// ellipse
int fixed = javaArgCount - i - 1;
for (int n = 0; n < fixed; n++) {
a[i] = args.get(n).value(c);
i++;
}
final int numVarArgs = args.size() - fixed;
String[] varArgs = new String[numVarArgs];
for (int n = fixed; n < args.size(); n++)
varArgs[n - fixed] = args.get(n).value(c).toString();
a[i] = varArgs;
}
try {
return method.invoke(instance, a);
} catch (RuntimeException | IllegalAccessException | InvocationTargetException e) {
throw new HGSEvalException("Error invoking the java method " + method.getName() + "!", e);
}
}
}
private static final class MethodMap<T> implements HGSMap {
private final JavaClass<T> javaClass;
private final T instance;
private MethodMap(JavaClass<T> javaClass, T instance) {
this.javaClass = javaClass;
this.instance = instance;
}
@Override
public Object hgsMapGet(String key) {
MyMethod<T> m = javaClass.methods.get(key);
if (m == null) return null;
return new MethodCall<>(m, instance);
}
}
private static final class MethodCall<T> extends InnerFunction {
private final MyMethod<T> m;
private final T instance;
private MethodCall(MyMethod<T> m, T instance) {
super(m.argCount);
this.m = m;
this.instance = instance;
}
@Override
public Object call(Context c, ArrayList<Expression> args) throws HGSEvalException {
return m.call(instance, c, args);
}
}
}

121
src/main/java/de/neemann/digital/hdl/hgs/function/JavaMethod.java
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@ -1,121 +0,0 @@
/*
* Copyright (c) 2018 Helmut Neemann.
* Use of this source code is governed by the GPL v3 license
* that can be found in the LICENSE file.
*/
package de.neemann.digital.hdl.hgs.function;
import de.neemann.digital.hdl.hgs.Context;
import de.neemann.digital.hdl.hgs.Expression;
import de.neemann.digital.hdl.hgs.HGSEvalException;
import java.lang.reflect.InvocationTargetException;
import java.lang.reflect.Method;
import java.lang.reflect.Modifier;
import java.util.ArrayList;
/**
* Used to call a java function from the template code.
* Uses reflection to invoke the method;
*/
public final class JavaMethod extends InnerFunction {
private final Object instance;
private final Method method;
private final Class<?>[] argTypes;
private final boolean addContext;
/**
* Creates a function for a static method.
* If the first argument of the method is of type {@link Context} the
* context is passed in.
*
* @param c the class
* @param name the name of the method
* @return the function
*/
public static JavaMethod create(Class c, String name) {
for (Method m : c.getMethods()) {
if (m.getName().equals(name))
if (Modifier.isStatic(m.getModifiers())) {
Class<?>[] argTypes = m.getParameterTypes();
return create(null, m, argTypes);
}
}
throw new RuntimeException("method '" + name + "' not found in " + c.getName() + "!");
}
/**
* Creates a function for a non static method.
* If the first argument of the method is of type {@link Context} the
* context is passed in.
*
* @param inst the instance to use for the call
* @param name the name of the method
* @return the function
*/
public static JavaMethod create(Object inst, String name) {
final Class<?> c = inst.getClass();
for (Method m : c.getMethods()) {
if (m.getName().equals(name))
if (!Modifier.isStatic(m.getModifiers())) {
Class<?>[] argTypes = m.getParameterTypes();
return create(inst, m, argTypes);
}
}
throw new RuntimeException("method '" + name + "' not found in " + c.getName() + "!");
}
private static JavaMethod create(Object inst, Method m, Class<?>[] argTypes) {
if (argTypes.length > 0 && argTypes[0].isAssignableFrom(Context.class))
return new JavaMethod(argTypes.length - 1, inst, m, argTypes, true);
else
return new JavaMethod(argTypes.length, inst, m, argTypes, false);
}
private JavaMethod(int argCount, Object instance, Method method, Class<?>[] argTypes, boolean addContext) {
super(argCount);
this.instance = instance;
this.method = method;
this.argTypes = argTypes;
this.addContext = addContext;
}
@Override
public Object call(Context c, ArrayList<Expression> args) throws HGSEvalException {
if (getArgCount() != args.size())
throw new HGSEvalException("wrong number of arguments! expected: " + getArgCount() + ", but found:" + args.size());
Object[] a;
int i = 0;
if (addContext) {
a = new Object[args.size() + 1];
a[0] = c;
i++;
} else
a = new Object[args.size()];
for (Expression exp : args) {
a[i] = exp.value(c);
i++;
}
return f(a);
}
private Object f(Object... args) throws HGSEvalException {
for (int i = 0; i < args.length; i++) {
if (!argTypes[i].isAssignableFrom(args[i].getClass()))
throw new HGSEvalException("Argument " + i + " has wrong type! Expected: "
+ argTypes[i].getName()
+ ", found "
+ args[i].getClass().getName());
}
try {
return method.invoke(instance, args);
} catch (IllegalAccessException | InvocationTargetException e) {
throw new HGSEvalException("Error invoking the java method " + method.getName() + "!", e);
}
}
}

199
src/main/java/de/neemann/digital/hdl/vhdl/lib/VHDLTemplate.java
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@ -6,8 +6,7 @@
package de.neemann.digital.hdl.vhdl.lib;
import de.neemann.digital.hdl.hgs.*;
import de.neemann.digital.hdl.hgs.function.Function;
import de.neemann.digital.hdl.hgs.function.InnerFunction;
import de.neemann.digital.hdl.hgs.function.JavaClass;
import de.neemann.digital.hdl.model.HDLException;
import de.neemann.digital.hdl.model.HDLNode;
import de.neemann.digital.hdl.model.Port;
@ -20,7 +19,6 @@ import java.io.InputStreamReader;
import java.io.Reader;
import java.util.ArrayList;
import java.util.HashMap;
import java.util.List;
import static de.neemann.digital.hdl.vhdl.VHDLLibrary.writePort;
@ -28,58 +26,10 @@ import static de.neemann.digital.hdl.vhdl.VHDLLibrary.writePort;
* Reads a file with the vhdl code to create the entity
*/
public class VHDLTemplate implements VHDLEntity {
private static final JavaClass<VHDLTemplateFunctions> TEMP_FUNCTIONS_CLASS
= new JavaClass<>(VHDLTemplateFunctions.class);
private static final String ENTITY_PREFIX = "DIG_";
private static Context createBuitInContext() {
try {
return new Context()
.declareFunc("zero", new FunctionZero())
.declareFunc("type", new FunctionType())
.declareFunc("genericType", new FunctionGenericType())
.declareFunc("value", new FunctionValue())
.declareFunc("beginGenericPort", new InnerFunction(0) {
@Override
public Object call(Context c, ArrayList<Expression> args) throws HGSEvalException {
c.declareVar("portStartPos", c.length());
return null;
}
})
.declareFunc("endGenericPort", new InnerFunction(0) {
@Override
public Object call(Context c, ArrayList<Expression> args) throws HGSEvalException {
int start = Value.toInt(c.getVar("portStartPos"));
String portDecl = c.toString().substring(start);
c.declareVar("portDecl", portDecl);
return null;
}
})
.declareFunc("registerGeneric", new InnerFunction(-1) {
@Override
public Object call(Context c, ArrayList<Expression> args) throws HGSEvalException {
List<Generic> generics;
if (c.contains("generics"))
generics = (List<Generic>) c.getVar("generics");
else {
generics = new ArrayList<>();
c.declareVar("generics", generics);
}
String name = Value.toString(args.get(0).value(c));
if (args.size() == 1)
generics.add(new Generic(name, "Integer"));
else if (args.size() == 2)
generics.add(new Generic(name, Value.toString(args.get(1).value(c))));
else
throw new HGSEvalException("registerGeneric needs one or two arguments!");
return null;
}
});
} catch (HGSEvalException e) {
throw new RuntimeException("error creating template built-in's!");
}
}
private static final Context VHDLCONTEXT = createBuitInContext();
private final static String ENTITY_PREFIX = "DIG_";
private final Statement statements;
private final String entityName;
private HashMap<String, Entity> entities;
@ -124,7 +74,7 @@ public class VHDLTemplate implements VHDLEntity {
Entity e = getEntity(node);
if (!e.isWritten()) {
out.print(e.getCode());
e.setWritten(true);
e.setWritten();
}
} catch (HGSEvalException e) {
throw new IOException("error evaluating the template " + createFileName(entityName), e);
@ -164,13 +114,13 @@ public class VHDLTemplate implements VHDLEntity {
public void writeGenericMap(CodePrinter out, HDLNode node) throws IOException {
try {
final Entity e = getEntity(node);
if (e.getGenerics() != null) {
if (!e.getGenerics().isEmpty()) {
out.println("generic map (").inc();
Separator semic = new Separator(",\n");
for (Generic gen : e.getGenerics()) {
for (VHDLTemplateFunctions.Generic gen : e.getGenerics()) {
semic.check(out);
final Object value = node.getAttributes().hgsMapGet(gen.name);
out.print(gen.name).print(" => ").print(gen.format(value));
final Object value = node.getAttributes().hgsMapGet(gen.getName());
out.print(gen.getName()).print(" => ").print(gen.format(value));
}
out.println(")").dec();
}
@ -196,24 +146,17 @@ public class VHDLTemplate implements VHDLEntity {
private final class Entity {
private final String code;
private final String portDecl;
private final String name;
private final List<Generic> generics;
private final VHDLTemplateFunctions helper;
private boolean isWritten = false;
private Entity(HDLNode node, String name) throws HGSEvalException {
final Context c = new Context(VHDLCONTEXT)
.declareVar("elem", node.getAttributes());
helper = new VHDLTemplateFunctions();
final Context c = new Context()
.declareVar("elem", node.getAttributes())
.declareVar("vhdl", TEMP_FUNCTIONS_CLASS.createMap(helper));
statements.execute(c);
code = c.toString();
if (c.contains("portDecl"))
portDecl = c.getVar("portDecl").toString();
else
portDecl = null;
if (c.contains("generics"))
generics = (List<Generic>) c.getVar("generics");
else
generics = null;
if (c.contains("entityName"))
this.name = c.getVar("entityName").toString();
@ -226,129 +169,25 @@ public class VHDLTemplate implements VHDLEntity {
}
private String getPortDecl() {
return portDecl;
return helper.getPortDecl();
}
private boolean isWritten() {
return isWritten;
}
private void setWritten(boolean written) {
isWritten = written;
private void setWritten() {
isWritten = true;
}
private String getName() {
return name;
}
private List<Generic> getGenerics() {
return generics;
private ArrayList<VHDLTemplateFunctions.Generic> getGenerics() {
return helper.getGenerics();
}
}
private final static class FunctionType extends Function {
private FunctionType() {
super(1);
}
@Override
protected Object f(Object... args) throws HGSEvalException {
int bits = Value.toInt(args[0]);
if (bits == 0)
throw new HGSEvalException("zero bits is not allowed!");
if (bits == 1)
return "std_logic";
else
return "std_logic_vector (" + (bits - 1) + " downto 0)";
}
}
private final static class FunctionGenericType extends Function {
private FunctionGenericType() {
super(1);
}
@Override
protected Object f(Object... args) throws HGSEvalException {
int n = Value.toInt(args[0]);
if (n == 1)
return "std_logic";
else
return "std_logic_vector ((Bits-1) downto 0)";
}
}
private final static class FunctionZero extends Function {
private FunctionZero() {
super(1);
}
@Override
protected Object f(Object... args) throws HGSEvalException {
int n = Value.toInt(args[0]);
if (n == 1)
return "'0'";
else
return "(others => '0')";
}
}
private final static class FunctionValue extends Function {
/**
* Creates a new function
*/
private FunctionValue() {
super(2);
}
@Override
protected Object f(Object... args) throws HGSEvalException {
int val = Value.toInt(args[0]);
int bits = Value.toInt(args[1]);
return getBin(val, bits);
}
private static String getBin(int val, int bits) {
String s = Integer.toBinaryString(val);
while (s.length() < bits)
s = "0" + s;
if (bits > 1)
s = "\"" + s + "\"";
else
s = "'" + s + "'";
return s;
}
}
private static final class Generic {
private final String name;
private final String type;
private Generic(String name, String type) {
this.name = name;
this.type = type.toLowerCase();
}
public String format(Object o) throws HGSEvalException {
switch (type) {
case "integer":
return Long.toString(Value.toLong(o));
case "real":
return Double.toString(Value.toDouble(o));
case "std_logic":
return "'" + (Value.toBool(o) ? 1 : 0) + "'";
default:
throw new HGSEvalException("type " + type + " not allowed as generic");
}
}
}
}

171
src/main/java/de/neemann/digital/hdl/vhdl/lib/VHDLTemplateFunctions.java Normal file
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@ -0,0 +1,171 @@
/*
* Copyright (c) 2018 Helmut Neemann.
* Use of this source code is governed by the GPL v3 license
* that can be found in the LICENSE file.
*/
package de.neemann.digital.hdl.vhdl.lib;
import de.neemann.digital.hdl.hgs.Context;
import de.neemann.digital.hdl.hgs.HGSEvalException;
import de.neemann.digital.hdl.hgs.Value;
import java.util.ArrayList;
/**
* Helper functions for the vhdl template generator.
* The public methods are mapped to the vhdl templates.
*/
public final class VHDLTemplateFunctions {
private int portStartPos;
private String portDecl;
private ArrayList<Generic> generics;
/**
* Creates a new instance
*/
public VHDLTemplateFunctions() {
generics = new ArrayList<>();
}
/**
* Create a vhdl zero with the given bit number
*
* @param bits the bit number
* @return '0' or (others => '0')
*/
public static String zero(long bits) {
if (bits == 1)
return "'0'";
else
return "(others => '0')";
}
/**
* Creates a vhdl value
*
* @param val the value
* @param bits the bit number
* @return the value as vhdl code
*/
public static String value(long val, long bits) {
String s = Long.toBinaryString(val);
while (s.length() < bits)
s = "0" + s;
if (bits > 1)
s = "\"" + s + "\"";
else
s = "'" + s + "'";
return s;
}
/**
* Creats the code for a generic type
*
* @param n the number of bits
* @return the type
*/
public static String genericType(long n) {
if (n == 1)
return "std_logic";
else
return "std_logic_vector ((Bits-1) downto 0)";
}
/**
* Creates a type of given width
*
* @param n the number of bits
* @return the type
*/
public static String type(long n) {
if (n == 1)
return "std_logic";
else
return "std_logic_vector (" + (n - 1) + " downto 0)";
}
/**
* Begins the generic port definition.
*
* @param c the context
*/
public void beginGenericPort(Context c) {
portStartPos = c.length();
}
/**
* Ends the generic port definition.
*
* @param c the context
*/
public void endGenericPort(Context c) {
portDecl = c.toString().substring(portStartPos);
}
/**
* Registers a generic value of the given type
*
* @param args the arguments
* @throws HGSEvalException HGSEvalException
*/
public void registerGeneric(String... args) throws HGSEvalException {
if (args.length == 1)
generics.add(new Generic(args[0], "integer"));
else if (args.length == 2)
generics.add(new Generic(args[0], args[1]));
else
throw new HGSEvalException("wrong number of arguments");
}
String getPortDecl() {
return portDecl;
}
ArrayList<Generic> getGenerics() {
return generics;
}
/**
* A generic value
*/
public static final class Generic {
private final String name;
private final String type;
private Generic(String name, String type) {
this.name = name;
this.type = type.toLowerCase();
}
/**
* @return the name of the generic value
*/
public String getName() {
return name;
}
/**
* Formats the generic value according to the values type
*
* @param val the value
* @return the formatted vhdl value
* @throws HGSEvalException HGSEvalException
*/
public String format(Object val) throws HGSEvalException {
switch (type) {
case "integer":
return Long.toString(Value.toLong(val));
case "real":
return Double.toString(Value.toDouble(val));
case "std_logic":
return "'" + (Value.toBool(val) ? 1 : 0) + "'";
default:
throw new HGSEvalException("type " + type + " not allowed as generic");
}
}
}
}

6
src/main/resources/vhdl/DIG_Add.tem
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@ -3,15 +3,15 @@ USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity DIG_Add is
<?beginGenericPort();?>
generic ( Bits: integer ); <?registerGeneric("Bits");?>
<? vhdl.beginGenericPort();?>
generic ( Bits: integer ); <? vhdl.registerGeneric("Bits");?>
port (
PORT_s: out std_logic_vector((Bits-1) downto 0);
PORT_c_o: out std_logic;
PORT_a: in std_logic_vector((Bits-1) downto 0);
PORT_b: in std_logic_vector((Bits-1) downto 0);
PORT_c_i: in std_logic );
<?endGenericPort();?>
<? vhdl.endGenericPort();?>
end DIG_Add;
architecture DIG_Add_arch of DIG_Add is

14
src/main/resources/vhdl/DIG_BitExtender.tem
View File

@ -5,13 +5,13 @@ USE ieee.std_logic_1164.all;
entityName:="DIG_BitExtender";?>
entity DIG_BitExtender is
<?beginGenericPort();?>
generic ( inputBits : integer; <?registerGeneric("inputBits");?>
outputBits : integer); <?registerGeneric("outputBits");?>
<? vhdl.beginGenericPort();?>
generic ( inputBits : integer; <? vhdl.registerGeneric("inputBits");?>
outputBits : integer); <? vhdl.registerGeneric("outputBits");?>
port (
PORT_in: in std_logic_vector ((inputBits-1) downto 0);
PORT_out: out std_logic_vector ((outputBits-1) downto 0) );
<?endGenericPort();?>
<? vhdl.endGenericPort();?>
end DIG_BitExtender;
architecture DIG_BitExtender_arch of DIG_BitExtender is
@ -24,12 +24,12 @@ end DIG_BitExtender_arch;
entityName:="DIG_BitExtenderSingle";
?>
entity DIG_BitExtenderSingle is
<?beginGenericPort();?>
generic ( outputBits : integer); <?registerGeneric("outputBits");?>
<? vhdl.beginGenericPort();?>
generic ( outputBits : integer); <? vhdl.registerGeneric("outputBits");?>
port (
PORT_in: in std_logic;
PORT_out: out std_logic_vector ((outputBits-1) downto 0) );
<?endGenericPort();?>
<? vhdl.endGenericPort();?>
end DIG_BitExtenderSingle;
architecture DIG_BitExtenderSingle_arch of DIG_BitExtenderSingle is

8
src/main/resources/vhdl/DIG_BitSelector.tem
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@ -9,8 +9,8 @@ USE ieee.std_logic_1164.all;
entity <?=entityName?> is
port (
PORT_out: out std_logic;
PORT_in: in <?=type(Bits)?>;
PORT_sel: in <?=type(elem.'Selector Bits')?> );
PORT_in: in <?= vhdl.type(Bits)?>;
PORT_sel: in <?= vhdl.type(elem.'Selector Bits')?> );
end <?=entityName?>;
architecture <?=entityName?>_arch of <?=entityName?> is
@ -18,6 +18,6 @@ begin
with PORT_sel select
PORT_out <=
<? for (n:=0;n<Bits;n++) { ?>
PORT_in(<?=n?>) when <?=value(n, elem.'Selector Bits') ?>,
<? } print(zero(elem.Bits));?> when others;
PORT_in(<?=n?>) when <?= vhdl.value(n, elem.'Selector Bits') ?>,
<? } print( vhdl.zero(elem.Bits));?> when others;
end <?=entityName?>_arch;

10
src/main/resources/vhdl/DIG_Comparator.tem
View File

@ -10,15 +10,15 @@ USE ieee.std_logic_1164.all;
?>
entity <?=entityName?> is
<?beginGenericPort();?>
generic ( Bits : integer );<?registerGeneric("Bits");?>
<? vhdl.beginGenericPort();?>
generic ( Bits : integer );<? vhdl.registerGeneric("Bits");?>
port (
PORT_gr: out std_logic;
PORT_eq: out std_logic;
PORT_le: out std_logic;
PORT_a: in <?=genericType(elem.Bits)?>;
PORT_b: in <?=genericType(elem.Bits)?> );
<?endGenericPort();?>
PORT_a: in <?= vhdl.genericType(elem.Bits)?>;
PORT_b: in <?= vhdl.genericType(elem.Bits)?> );
<? vhdl.endGenericPort();?>
end <?=entityName?>;
architecture <?=entityName?>_arch of <?=entityName?> is

6
src/main/resources/vhdl/DIG_Counter.tem
View File

@ -3,15 +3,15 @@ USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity DIG_Counter is
<?beginGenericPort();?>
generic ( Bits: integer ); <?registerGeneric("Bits");?>
<? vhdl.beginGenericPort();?>
generic ( Bits: integer ); <? vhdl.registerGeneric("Bits");?>
port (
PORT_out: out std_logic_vector((Bits-1) downto 0);
PORT_ovf: out std_logic;
PORT_C: in std_logic;
PORT_en: in std_logic;
PORT_clr: in std_logic );
<?endGenericPort();?>
<? vhdl.endGenericPort();?>
end DIG_Counter;
architecture DIG_Counter_arch of DIG_Counter is

14
src/main/resources/vhdl/DIG_D_FF.tem
View File

@ -8,17 +8,17 @@ USE ieee.std_logic_1164.all;
?>
entity <?=entityName?> is
<?beginGenericPort();?>
<?if (elem.Bits>1) {?>generic ( Bits: integer ); <?registerGeneric("Bits"); }?>
port ( PORT_D : in <?=genericType(elem.Bits)?>;
<? vhdl.beginGenericPort();?>
<?if (elem.Bits>1) {?>generic ( Bits: integer ); <? vhdl.registerGeneric("Bits"); }?>
port ( PORT_D : in <?= vhdl.genericType(elem.Bits)?>;
PORT_C : in std_logic;
PORT_Q : out <?=genericType(elem.Bits)?>;
PORT_notQ : out <?=genericType(elem.Bits)?> );
<?endGenericPort();?>
PORT_Q : out <?= vhdl.genericType(elem.Bits)?>;
PORT_notQ : out <?= vhdl.genericType(elem.Bits)?> );
<? vhdl.endGenericPort();?>
end <?=entityName?>;
architecture <?=entityName?>_arch of <?=entityName?> is
signal state : <?=genericType(elem.Bits)?> := <?=zero(elem.Bits)?>;
signal state : <?= vhdl.genericType(elem.Bits)?> := <?= vhdl.zero(elem.Bits)?>;
begin
PORT_Q <= state;
PORT_notQ <= NOT( state );

18
src/main/resources/vhdl/DIG_D_FF_AS.tem
View File

@ -9,28 +9,28 @@ USE ieee.std_logic_1164.all;
?>
entity <?=entityName?> is
<?beginGenericPort();?>
<?if (elem.Bits>1) {?>generic ( Bits: integer ); <?registerGeneric("Bits"); }?>
<? vhdl.beginGenericPort();?>
<?if (elem.Bits>1) {?>generic ( Bits: integer ); <? vhdl.registerGeneric("Bits"); }?>
port (
PORT_Q: out <?=genericType(elem.Bits)?>;
PORT_notQ: out <?=genericType(elem.Bits)?>;
PORT_Q: out <?= vhdl.genericType(elem.Bits)?>;
PORT_notQ: out <?= vhdl.genericType(elem.Bits)?>;
PORT_Set: in std_logic;
PORT_D: in <?=genericType(elem.Bits)?>;
PORT_D: in <?= vhdl.genericType(elem.Bits)?>;
PORT_C: in std_logic;
PORT_Clr: in std_logic );
<?endGenericPort();?>
<? vhdl.endGenericPort();?>
end <?=entityName?>;
architecture <?=entityName?>_arch of <?=entityName?> is
signal state : <?=genericType(elem.Bits)?> := <?=zero(elem.Bits)?>;
signal state : <?= vhdl.genericType(elem.Bits)?> := <?= vhdl.zero(elem.Bits)?>;
begin
process ( PORT_Set, PORT_Clr, PORT_C )
begin
if (PORT_Set='1') then
state <= NOT(<?=zero(elem.Bits)?>);
state <= NOT(<?= vhdl.zero(elem.Bits)?>);
elsif (PORT_Clr='1') then
state <= <?=zero(elem.Bits)?>;
state <= <?= vhdl.zero(elem.Bits)?>;
elsif rising_edge(PORT_C) then
state <= PORT_D;
end if;

4
src/main/resources/vhdl/DIG_Decoder.tem
View File

@ -10,12 +10,12 @@ entity <?=entityName?> is
<? for (i:=0;i<outputs;i++) {?>
PORT_out_<?=i?>: out std_logic;
<? } ?>
PORT_sel: in <?=type(elem.'Selector Bits')?> );
PORT_sel: in <?= vhdl.type(elem.'Selector Bits')?> );
end <?=entityName?>;
architecture <?=entityName?>_arch of <?=entityName?> is
begin
<? for (i:=0;i<outputs;i++) {?>
PORT_out_<?=i?> <= '1' when PORT_sel = <?=value(i,elem.'Selector Bits')?> else '0';
PORT_out_<?=i?> <= '1' when PORT_sel = <?= vhdl.value(i,elem.'Selector Bits')?> else '0';
<? } ?>
end <?=entityName?>_arch;

14
src/main/resources/vhdl/DIG_Demultiplexer.tem
View File

@ -10,22 +10,22 @@ USE ieee.std_logic_1164.all;
?>
entity <?=entityName?> is
<? beginGenericPort();?>
<? vhdl.beginGenericPort();?>
<? if (elem.Bits>1) { ?>
generic ( Bits : integer );<? registerGeneric("Bits");?>
generic ( Bits : integer );<? vhdl.registerGeneric("Bits");?>
<? } ?>
port (
<? for (i:=0;i<outputs;i++) {?>
PORT_out_<?=i?>: out <?=genericType(elem.Bits)?>;
PORT_out_<?=i?>: out <?= vhdl.genericType(elem.Bits)?>;
<? } ?>
PORT_sel: in <?=type(elem.'Selector Bits')?>;
PORT_in: in <?=genericType(elem.Bits)?> );
<? endGenericPort();?>
PORT_sel: in <?= vhdl.type(elem.'Selector Bits')?>;
PORT_in: in <?= vhdl.genericType(elem.Bits)?> );
<? vhdl.endGenericPort();?>
end <?=entityName?>;
architecture <?=entityName?>_arch of <?=entityName?> is
begin
<? for (i:=0;i<outputs;i++) {?>
PORT_out_<?=i?> <= PORT_in when PORT_sel = <?=value(i,elem.'Selector Bits')?> else <?=zero(elem.Bits)?>;
PORT_out_<?=i?> <= PORT_in when PORT_sel = <?= vhdl.value(i,elem.'Selector Bits')?> else <?= vhdl.zero(elem.Bits)?>;
<? } ?>
end <?=entityName?>_arch;

10
src/main/resources/vhdl/DIG_Driver.tem
View File

@ -9,13 +9,13 @@ USE ieee.std_logic_1164.all;
?>
entity <?=entityName?> is
<?beginGenericPort();?>
<?if (elem.Bits>1) {?>generic ( Bits : integer ); <?registerGeneric("Bits"); }?>
<? vhdl.beginGenericPort();?>
<?if (elem.Bits>1) {?>generic ( Bits : integer ); <? vhdl.registerGeneric("Bits"); }?>
port (
PORT_out: out <?=genericType(elem.Bits)?>;
PORT_in: in <?=genericType(elem.Bits)?>;
PORT_out: out <?= vhdl.genericType(elem.Bits)?>;
PORT_in: in <?= vhdl.genericType(elem.Bits)?>;
PORT_sel: in std_logic );
<?endGenericPort();?>
<? vhdl.endGenericPort();?>
end <?=entityName?>;
architecture <?=entityName?>_arch of <?=entityName?> is

10
src/main/resources/vhdl/DIG_DriverInvSel.tem
View File

@ -9,13 +9,13 @@ USE ieee.std_logic_1164.all;
?>
entity <?=entityName?> is
<?beginGenericPort();?>
<?if (elem.Bits>1) {?>generic ( Bits : integer ); <?registerGeneric("Bits"); }?>
<? vhdl.beginGenericPort();?>
<?if (elem.Bits>1) {?>generic ( Bits : integer ); <? vhdl.registerGeneric("Bits"); }?>
port (
PORT_out: out <?=genericType(elem.Bits)?>;
PORT_in: in <?=genericType(elem.Bits)?>;
PORT_out: out <?= vhdl.genericType(elem.Bits)?>;
PORT_in: in <?= vhdl.genericType(elem.Bits)?>;
PORT_sel: in std_logic );
<?endGenericPort();?>
<? vhdl.endGenericPort();?>
end <?=entityName?>;
architecture <?=entityName?>_arch of <?=entityName?> is

6
src/main/resources/vhdl/DIG_JK_FF.tem
View File

@ -2,15 +2,15 @@ LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity DIG_JK_FF is
<?beginGenericPort();?>
generic (Default : std_logic); <?registerGeneric("Default", "std_logic");?>
<? vhdl.beginGenericPort();?>
generic (Default : std_logic); <? vhdl.registerGeneric("Default", "std_logic");?>
port (
PORT_Q: out std_logic;
PORT_notQ: out std_logic;
PORT_J: in std_logic;
PORT_C: in std_logic;
PORT_K: in std_logic );
<?endGenericPort();?>
<? vhdl.endGenericPort();?>
end DIG_JK_FF;
architecture DIG_JK_FF_arch of DIG_JK_FF is

6
src/main/resources/vhdl/DIG_JK_FF_AS.tem
View File

@ -2,8 +2,8 @@ LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity DIG_JK_FF_AS is
<?beginGenericPort();?>
generic (Default : std_logic); <?registerGeneric("Default", "std_logic");?>
<? vhdl.beginGenericPort();?>
generic (Default : std_logic); <? vhdl.registerGeneric("Default", "std_logic");?>
port (
PORT_Q: out std_logic;
PORT_notQ: out std_logic;
@ -12,7 +12,7 @@ entity DIG_JK_FF_AS is
PORT_C: in std_logic;
PORT_K: in std_logic;
PORT_Clr: in std_logic );
<?endGenericPort();?>
<? vhdl.endGenericPort();?>
end DIG_JK_FF_AS;
architecture DIG_JK_FF_AS_arch of DIG_JK_FF_AS is

16
src/main/resources/vhdl/DIG_MMCME2_BASE.tem
View File

@ -5,21 +5,21 @@ Library UNISIM;
use UNISIM.vcomponents.all;
entity DIG_MMCME2_BASE is
<?beginGenericPort();?>
<? vhdl.beginGenericPort();?>
generic (
D_PARAM : integer;<? registerGeneric("D_PARAM");?>
M_PARAM : real;<? registerGeneric("M_PARAM","real");?>
D_PARAM : integer;<? vhdl.registerGeneric("D_PARAM");?>
M_PARAM : real;<? vhdl.registerGeneric("M_PARAM","real");?>
<? if (elem.cascading) {?>
DIV_PARAM : integer;<? registerGeneric("DIV_PARAM");?>
DIV4_PARAM : integer;<?registerGeneric("DIV4_PARAM");?>
DIV_PARAM : integer;<? vhdl.registerGeneric("DIV_PARAM");?>
DIV4_PARAM : integer;<?vhdl.registerGeneric("DIV4_PARAM");?>
<? } else { ?>
DIV_PARAM : real;<? registerGeneric("DIV_PARAM","real");?>
DIV_PARAM : real;<? vhdl.registerGeneric("DIV_PARAM","real");?>
<? } ?>
PERIOD_PARAM: real);<? registerGeneric("PERIOD_PARAM","real");?>
PERIOD_PARAM: real);<? vhdl.registerGeneric("PERIOD_PARAM","real");?>
port (
PORT_in: in std_logic;
PORT_out: out std_logic );
<?endGenericPort();?>
<? vhdl.endGenericPort();?>
end DIG_MMCME2_BASE;
architecture DIG_MMCME2_BASE_arch of DIG_MMCME2_BASE is

6
src/main/resources/vhdl/DIG_Mul.tem
View File

@ -3,13 +3,13 @@ USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity DIG_Mul is
<?beginGenericPort();?>
generic ( Bits: integer ); <?registerGeneric("Bits");?>
<? vhdl.beginGenericPort();?>
generic ( Bits: integer ); <? vhdl.registerGeneric("Bits");?>
port (
PORT_a: in std_logic_vector ((Bits-1) downto 0);
PORT_b: in std_logic_vector ((Bits-1) downto 0);
PORT_mul: out std_logic_vector ((Bits*2-1) downto 0) );
<?endGenericPort();?>
<? vhdl.endGenericPort();?>
end DIG_Mul;
architecture DIG_Mul_arch of DIG_Mul is

16
src/main/resources/vhdl/DIG_Multiplexer.tem
View File

@ -11,16 +11,16 @@ USE ieee.std_logic_1164.all;
?>
entity <?=entityName?> is
<? beginGenericPort();?>
<? vhdl.beginGenericPort();?>
<? if (elem.Bits>1) { ?>
generic ( Bits : integer ); <? registerGeneric("Bits");?>
generic ( Bits : integer ); <? vhdl.registerGeneric("Bits");?>
<? } ?>
port (
PORT_out: out <?=genericType(elem.Bits)?>;
PORT_sel: in <?=type(elem.'Selector Bits')?>;
PORT_out: out <?= vhdl.genericType(elem.Bits)?>;
PORT_sel: in <?= vhdl.type(elem.'Selector Bits')?>;
<? for (n:=0;n<inputs;n++) { ?>
PORT_in_<?=n?>: in <?=genericType(elem.Bits); if (n<inputs-1) print(";"); }?> );
<? endGenericPort();?>
PORT_in_<?=n?>: in <?= vhdl.genericType(elem.Bits); if (n<inputs-1) print(";"); }?> );
<? vhdl.endGenericPort();?>
end <?=entityName?>;
architecture <?=entityName?>_arch of <?=entityName?> is
@ -28,6 +28,6 @@ begin
with PORT_sel select
PORT_out <=
<? for (n:=0;n<inputs;n++) { ?>
PORT_in_<?=n?> when <?=value(n, elem.'Selector Bits') ?>,
<? } print(zero(elem.Bits));?> when others;
PORT_in_<?=n?> when <?= vhdl.value(n, elem.'Selector Bits') ?>,
<? } print( vhdl.zero(elem.Bits));?> when others;
end <?=entityName?>_arch;

10
src/main/resources/vhdl/DIG_Not.tem
View File

@ -9,12 +9,12 @@ USE ieee.std_logic_1164.all;
?>
entity <?=entityName?> is
<?beginGenericPort();?>
<?if (elem.Bits>1) {?>generic ( Bits : integer );<?registerGeneric("Bits"); }?>
<?vhdl.beginGenericPort();?>
<?if (elem.Bits>1) {?>generic ( Bits : integer );<?vhdl.registerGeneric("Bits"); }?>
port (
PORT_out: out <?=genericType(elem.Bits)?>;
PORT_in: in <?=genericType(elem.Bits)?> );
<?endGenericPort();?>
PORT_out: out <?=vhdl.genericType(elem.Bits)?>;
PORT_in: in <?=vhdl.genericType(elem.Bits)?> );
<?vhdl.endGenericPort();?>
end <?=entityName?>;
architecture <?=entityName?>_arch of <?=entityName?> is

10
src/main/resources/vhdl/DIG_Operate.tem
View File

@ -9,17 +9,17 @@ USE ieee.std_logic_1164.all;
?>
entity <?=entityName?> is
<?beginGenericPort();?>
<?if (elem.Bits>1) {?>generic ( Bits : integer );<?registerGeneric("Bits"); }?>
<?vhdl.beginGenericPort();?>
<?if (elem.Bits>1) {?>generic ( Bits : integer );<?vhdl.registerGeneric("Bits"); }?>
port (
PORT_out: out <?=genericType(elem.Bits)?>;
PORT_out: out <?=vhdl.genericType(elem.Bits)?>;
<? for (i:=0;i<elem.Inputs;i++) { ?>
PORT_In_<?=i+1?>: in <?
print(genericType(elem.Bits));
print(vhdl.genericType(elem.Bits));
if (i=elem.Inputs-1) print(" )");
?>;
<? } ?>
<?endGenericPort();?>
<?vhdl.endGenericPort();?>
end <?=entityName?>;
architecture <?=entityName?>_arch of <?=entityName?> is
begin

6
src/main/resources/vhdl/DIG_PriorityEncoder.tem
View File

@ -8,7 +8,7 @@ USE ieee.std_logic_1164.all;
entity <?=entityName?> is
port (
PORT_num: out <?=type(elem.'Selector Bits')?>;
PORT_num: out <?= vhdl.type(elem.'Selector Bits')?>;
PORT_any: out std_logic;
<? for (n:=0;n<inputs;n++) { ?>
PORT_in<?=n?>: in std_logic<?if (n=inputs-1) print(" )"); ?>;
@ -19,9 +19,9 @@ architecture <?=entityName?>_arch of <?=entityName?> is
begin
PORT_num <=
<? for (n:=inputs-1;n>0;n--) { ?>
<?=value(n,elem.'Selector Bits')?> when PORT_in<?=n?> = '1' else
<?= vhdl.value(n,elem.'Selector Bits')?> when PORT_in<?=n?> = '1' else
<? } ?>
<?=value(0,elem.'Selector Bits')?> ;
<?= vhdl.value(0,elem.'Selector Bits')?> ;
PORT_any <= <?
for (n:=0;n<inputs;n++) {
print("PORT_in",n);

8
src/main/resources/vhdl/DIG_RAMDualAccess.tem
View File

@ -3,10 +3,10 @@ USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity DIG_RAMDualAccess is
<?beginGenericPort();?>
<? vhdl.beginGenericPort();?>
generic (
Bits : integer; <?registerGeneric("Bits");?>
AddrBits : integer ); <?registerGeneric("AddrBits");?>
Bits : integer; <? vhdl.registerGeneric("Bits");?>
AddrBits : integer ); <? vhdl.registerGeneric("AddrBits");?>
port (
PORT_1D: out std_logic_vector ((Bits-1) downto 0);
PORT_2D: out std_logic_vector ((Bits-1) downto 0);
@ -16,7 +16,7 @@ entity DIG_RAMDualAccess is
PORT_1A: in std_logic_vector ((AddrBits-1) downto 0);
PORT_1Din: in std_logic_vector ((Bits-1) downto 0);
PORT_2A: in std_logic_vector ((AddrBits-1) downto 0) );
<?endGenericPort();?>
<? vhdl.endGenericPort();?>
end DIG_RAMDualAccess;
architecture DIG_RAMDualAccess_arch of DIG_RAMDualAccess is

8
src/main/resources/vhdl/DIG_RAMDualPort.tem
View File

@ -3,10 +3,10 @@ USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity DIG_RAMDualPort is
<?beginGenericPort();?>
<? vhdl.beginGenericPort();?>
generic (
Bits : integer; <?registerGeneric("Bits");?>
AddrBits : integer ); <?registerGeneric("AddrBits");?>
Bits : integer; <? vhdl.registerGeneric("Bits");?>
AddrBits : integer ); <? vhdl.registerGeneric("AddrBits");?>
port (
PORT_D: out std_logic_vector ((Bits-1) downto 0);
PORT_A: in std_logic_vector ((AddrBits-1) downto 0);
@ -14,7 +14,7 @@ entity DIG_RAMDualPort is
PORT_str: in std_logic;
PORT_C: in std_logic;
PORT_ld: in std_logic );
<?endGenericPort();?>
<? vhdl.endGenericPort();?>
end DIG_RAMDualPort;
architecture DIG_RAMDualPort_arch of DIG_RAMDualPort is

12
src/main/resources/vhdl/DIG_ROM.tem
View File

@ -10,20 +10,20 @@ use IEEE.NUMERIC_STD.ALL;
entity <?=entityName?> is
port (
PORT_D: out <?=type(elem.Bits)?>;
PORT_A: in <?=type(elem.AddrBits)?>;
PORT_D: out <?= vhdl.type(elem.Bits)?>;
PORT_A: in <?= vhdl.type(elem.AddrBits)?>;
PORT_sel: in std_logic );
end <?=entityName?>;
architecture <?=entityName?>_arch of <?=entityName?> is
type mem is array ( 0 to <?=sizeOf(elem.Data)-1?>) of <?=type(elem.Bits)?>;
type mem is array ( 0 to <?=sizeOf(elem.Data)-1?>) of <?= vhdl.type(elem.Bits)?>;
constant my_Rom : mem := (
<?
len:=sizeOf(elem.Data);
col:=0;
for (i:=0;i<len;i++) {
print(value(elem.Data[i],elem.Bits));
print( vhdl.value(elem.Data[i],elem.Bits));
if (i<len-1) {
print(", ");
}
@ -40,8 +40,8 @@ begin
begin
if PORT_sel='0' then
PORT_D <= <? if (elem.Bits>1) {?>(others => 'Z')<? } else {?>'Z'<? } ?>;
elsif PORT_A > <?=value(sizeOf(elem.Data)-1,elem.AddrBits)?> then
PORT_D <= <?=zero(elem.Bits)?>;
elsif PORT_A > <?= vhdl.value(sizeOf(elem.Data)-1,elem.AddrBits)?> then
PORT_D <= <?= vhdl.zero(elem.Bits)?>;
else
PORT_D <= my_rom(to_integer(unsigned(PORT_A)));
end if;

12
src/main/resources/vhdl/DIG_Register.tem
View File

@ -9,18 +9,18 @@ USE ieee.std_logic_1164.all;
?>
entity <?=entityName?> is
<?beginGenericPort();?>
<?if (elem.Bits>1) {?>generic ( Bits: integer ); <?registerGeneric("Bits"); }?>
<? vhdl.beginGenericPort();?>
<?if (elem.Bits>1) {?>generic ( Bits: integer ); <? vhdl.registerGeneric("Bits"); }?>
port (
PORT_Q: out <?=genericType(elem.Bits)?>;
PORT_D: in <?=genericType(elem.Bits)?>;
PORT_Q: out <?= vhdl.genericType(elem.Bits)?>;
PORT_D: in <?= vhdl.genericType(elem.Bits)?>;
PORT_C: in std_logic;
PORT_en: in std_logic );
<?endGenericPort();?>
<? vhdl.endGenericPort();?>
end <?=entityName?>;
architecture <?=entityName?>_arch of <?=entityName?> is
signal state : <?=genericType(elem.Bits)?> := <?=zero(elem.Bits)?>;
signal state : <?= vhdl.genericType(elem.Bits)?> := <?= vhdl.zero(elem.Bits)?>;
begin
PORT_Q <= state;

8
src/main/resources/vhdl/DIG_RegisterFile.tem
View File

@ -3,10 +3,10 @@ USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity DIG_RegisterFile is
<?beginGenericPort();?>
<? vhdl.beginGenericPort();?>
generic (
Bits : integer; <?registerGeneric("Bits");?>
AddrBits : integer ); <?registerGeneric("AddrBits");?>
Bits : integer; <? vhdl.registerGeneric("Bits");?>
AddrBits : integer ); <? vhdl.registerGeneric("AddrBits");?>
port (
PORT_Da: out std_logic_vector ((Bits-1) downto 0);
PORT_Db: out std_logic_vector ((Bits-1) downto 0);
@ -16,7 +16,7 @@ entity DIG_RegisterFile is
PORT_C: in std_logic;
PORT_Ra: in std_logic_vector ((AddrBits-1) downto 0);
PORT_Rb: in std_logic_vector ((AddrBits-1) downto 0) );
<?endGenericPort();?>
<? vhdl.endGenericPort();?>
end DIG_RegisterFile;
architecture DIG_RegisterFile_arch of DIG_RegisterFile is

6
src/main/resources/vhdl/DIG_Reset.tem
View File

@ -2,12 +2,12 @@ LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity DIG_Reset is
<?beginGenericPort();?>
<? vhdl.beginGenericPort();?>
generic (
invertOutput : std_logic );<?registerGeneric("invertOutput","std_logic");?>
invertOutput : std_logic );<? vhdl.registerGeneric("invertOutput","std_logic");?>
port (
PORT_Reset: out std_logic );
<?endGenericPort();?>
<? vhdl.endGenericPort();?>
end DIG_Reset;
architecture DIG_Reset_arch of DIG_Reset is

6
src/main/resources/vhdl/DIG_Sub.tem
View File

@ -3,15 +3,15 @@ USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity DIG_Sub is
<?beginGenericPort();?>
generic ( Bits: integer ); <?registerGeneric("Bits");?>
<? vhdl.beginGenericPort();?>
generic ( Bits: integer ); <? vhdl.registerGeneric("Bits");?>
port (
PORT_s: out std_logic_vector((Bits-1) downto 0);
PORT_c_o: out std_logic;
PORT_a: in std_logic_vector((Bits-1) downto 0);
PORT_b: in std_logic_vector((Bits-1) downto 0);
PORT_c_i: in std_logic );
<?endGenericPort();?>
<? vhdl.endGenericPort();?>
end DIG_Sub;
architecture DIG_Sub_arch of DIG_Sub is

6
src/main/resources/vhdl/DIG_simpleClockDivider.tem
View File

@ -4,13 +4,13 @@ USE ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
entity DIG_simpleClockDivider is
<?beginGenericPort();?>
<? vhdl.beginGenericPort();?>
generic (
maxCounter : integer ); <?registerGeneric("maxCounter");?>
maxCounter : integer ); <? vhdl.registerGeneric("maxCounter");?>
port (
PORT_out: out std_logic;
PORT_in: in std_logic );
<?endGenericPort();?>
<? vhdl.endGenericPort();?>
end DIG_simpleClockDivider;
architecture DIG_simpleClockDivider_arch of DIG_simpleClockDivider is

74
src/test/java/de/neemann/digital/hdl/hgs/ParserTest.java
View File

@ -5,7 +5,7 @@
*/
package de.neemann.digital.hdl.hgs;
import de.neemann.digital.hdl.hgs.function.JavaMethod;
import de.neemann.digital.hdl.hgs.function.JavaClass;
import de.neemann.digital.hdl.hgs.function.Function;
import de.neemann.digital.integration.FileScanner;
import de.neemann.digital.integration.Resources;
@ -405,46 +405,60 @@ public class ParserTest extends TestCase {
return sb.toString();
}
private int inner = 0;
public static final class TestClass {
private long inner;
public void javaFunc2() {
inner = 5;
public void add(long n) {
inner += n;
}
public static String javaFunc3(String text) {
return text + text;
public void sub(long n) {
inner -= n;
}
}
public static String javaFunc4(Context c, String text) {
return text + c.toString();
public static final class TestClassStatic {
private static long inner;
public static void set(long n) {
inner = n;
}
public static String javaFunc5(Context c) {
return c.toString();
public static void add(long n) {
inner += n;
}
public void testJavaMethod() throws ParserException, IOException, HGSEvalException {
Context c = exec("<? print(javaFunc(2,\"Test\"),\"-\",javaFunc(5,\"a\"));?>",
new Context().declareMethod("javaFunc", this));
assertEquals("TestTest-aaaaa", c.toString());
c = exec("<? print(javaFunc3(\"Test\"));?>",
new Context().declareStaticMethod("javaFunc3", ParserTest.class));
assertEquals("TestTest", c.toString());
exec("<? javaFunc2();?>",
new Context().declareMethod("javaFunc2", this));
assertEquals(5, inner);
c = exec("Hello World!<? print(javaFunc4(\"-Test-\"));?>",
new Context().declareStaticMethod("javaFunc4", ParserTest.class));
assertEquals("Hello World!-Test-Hello World!", c.toString());
c = exec("Hello World!<? print(javaFunc5());?>",
new Context().declareStaticMethod("javaFunc5", ParserTest.class));
assertEquals("Hello World!Hello World!", c.toString());
public static void sub(long n) {
inner -= n;
}
public static String mean(String... value) {
String sum = "";
for (int i = 0; i < value.length; i++)
sum += value[i];
return sum;
}
}
public void testJavaClass() throws ParserException, IOException, HGSEvalException {
JavaClass<TestClass> jc = new JavaClass<>(TestClass.class);
TestClass t = new TestClass();
exec("<? z.add(6);z.sub(3); ?>",
new Context().declareVar("z", jc.createMap(t)));
assertEquals(3L, t.inner);
JavaClass<TestClassStatic> jcs = new JavaClass<>(TestClassStatic.class);
exec("<? z.set(0);z.add(6);z.sub(3); ?>",
new Context().declareVar("z", jcs.createMap(null)));
assertEquals(3L, TestClassStatic.inner);
Context c = exec("<? print(z.mean(\"a\"), z.mean(\"a\",\"b\"), z.mean(\"a\",\"b\",\"c\")); ?>",
new Context().declareVar("z", jcs.createMap(null)));
assertEquals("aababc",c.toString());
}
public void testPanic() throws IOException, ParserException, HGSEvalException {
Statement s = new Parser("<? if (i>1) panic(\"myError\"); ?>").parse();