diff --git a/src/main/java/de/neemann/digital/core/arithmetic/Add.java b/src/main/java/de/neemann/digital/core/arithmetic/Add.java
index b52a08a68..e57e00564 100644
--- a/src/main/java/de/neemann/digital/core/arithmetic/Add.java
+++ b/src/main/java/de/neemann/digital/core/arithmetic/Add.java
@@ -5,6 +5,7 @@ import de.neemann.digital.core.element.Element;
import de.neemann.digital.core.element.ElementAttributes;
import de.neemann.digital.core.element.ElementTypeDescription;
import de.neemann.digital.core.element.Keys;
+import de.neemann.digital.lang.Lang;
import static de.neemann.digital.core.ObservableValues.ovs;
import static de.neemann.digital.core.element.PinInfo.input;
@@ -75,6 +76,9 @@ public class Add extends Node implements Element {
a = inputs.get(0).addObserverToValue(this).checkBits(bits, this);
b = inputs.get(1).addObserverToValue(this).checkBits(bits, this);
cIn = inputs.get(2).addObserverToValue(this).checkBits(1, this);
+
+ if (bits > 63)
+ throw new BitsException(Lang.get("err_toManyBits_Found_N0_maxIs_N1", bits, 63), this, new ObservableValues(a, b));
}
@Override
diff --git a/src/main/resources/lang/lang_de.xml b/src/main/resources/lang/lang_de.xml
index 640e4db9e..ace034573 100644
--- a/src/main/resources/lang/lang_de.xml
+++ b/src/main/resources/lang/lang_de.xml
@@ -489,6 +489,7 @@ Sind evtl. die Namen der Variablen nicht eindeutig?
Diode benötigt am Ausgang einen PullUp-Widerstand!
Diode benötigt am Ausgang einen PullDown-Widerstand!
Testsignal {0} in der Schaltung nicht gefunden!
+ Es sind nur {1} Bits erlaubt, es sind jedoch {0} Bits angegeben!
Adress-Bits
Anzahl der Adress-Bits die verwendet werden.
diff --git a/src/main/resources/lang/lang_en.xml b/src/main/resources/lang/lang_en.xml
index 1093cc037..15c3d9ca7 100644
--- a/src/main/resources/lang/lang_en.xml
+++ b/src/main/resources/lang/lang_en.xml
@@ -479,6 +479,7 @@ The names of the variables may not be unique.
Diode needs a pull up resistor at its output!
Diode needs a pull down resistor at its output!
Test signal {0} not found in the circuit!
+ Only {1} bits allowed, but {0} bits found!
Address Bits
Number of address bits used.
diff --git a/src/test/java/de/neemann/digital/integration/TestExamples.java b/src/test/java/de/neemann/digital/integration/TestExamples.java
index f03ca6d04..a2b74c002 100644
--- a/src/test/java/de/neemann/digital/integration/TestExamples.java
+++ b/src/test/java/de/neemann/digital/integration/TestExamples.java
@@ -39,8 +39,8 @@ public class TestExamples extends TestCase {
*/
public void testTestExamples() throws Exception {
File examples = new File(Resources.getRoot(), "/dig/test");
- assertEquals(55, new FileScanner(this::check).scan(examples));
- assertEquals(51, testCasesInFiles);
+ assertEquals(60, new FileScanner(this::check).scan(examples));
+ assertEquals(56, testCasesInFiles);
}
diff --git a/src/test/resources/dig/test/arith/FullSub.dig b/src/test/resources/dig/test/arith/FullSub.dig
new file mode 100644
index 000000000..fa636eab7
--- /dev/null
+++ b/src/test/resources/dig/test/arith/FullSub.dig
@@ -0,0 +1,160 @@
+
+
+ 1
+
+
+ Description
+ FullSub
+
+
+ Width
+ 4
+
+
+
+
+ In
+
+
+ Label
+ A_i
+
+
+
+
+
+ In
+
+
+ Label
+ B_i
+
+
+
+
+
+ In
+
+
+ Label
+ BO_i-1
+
+
+
+
+
+ HalfSub.dig
+
+
+
+
+ HalfAdder.dig
+
+
+
+
+ Out
+
+
+ Label
+ BO_i
+
+
+
+
+
+ Or
+
+
+
+
+ Out
+
+
+ Label
+ S_i
+
+
+
+
+
+ Testcase
+
+
+ Testdata
+
+ A_i B_i BO_i-1 BO_i S_i
+ 0 0 0 0 0
+ 0 0 1 1 1
+ 0 1 0 1 1
+ 0 1 1 1 0
+ 1 0 0 0 1
+ 1 0 1 0 0
+ 1 1 0 0 0
+ 1 1 1 1 1
+
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+
\ No newline at end of file
diff --git a/src/test/resources/dig/test/arith/FullSubRC.dig b/src/test/resources/dig/test/arith/FullSubRC.dig
new file mode 100644
index 000000000..1e637f32a
--- /dev/null
+++ b/src/test/resources/dig/test/arith/FullSubRC.dig
@@ -0,0 +1,354 @@
+
+
+ 1
+
+
+ Width
+ 4
+
+
+
+
+ Out
+
+
+ Label
+ S_0
+
+
+
+
+
+ In
+
+
+ Label
+ A_0
+
+
+
+
+
+ In
+
+
+ Label
+ A_1
+
+
+
+
+
+ Out
+
+
+ Label
+ S_1
+
+
+
+
+
+ In
+
+
+ Label
+ A_2
+
+
+
+
+
+ In
+
+
+ Label
+ A_3
+
+
+
+
+
+ Out
+
+
+ Label
+ S_2
+
+
+
+
+
+ In
+
+
+ Label
+ B_0
+
+
+
+
+
+ In
+
+
+ Label
+ B_1
+
+
+
+
+
+ Out
+
+
+ Label
+ S_3
+
+
+
+
+
+ In
+
+
+ Label
+ B_2
+
+
+
+
+
+ In
+
+
+ Label
+ B_3
+
+
+
+
+
+ Out
+
+
+ Label
+ C_3
+
+
+
+
+
+ In
+
+
+ Label
+ C_-1
+
+
+
+
+
+ FullSub.dig
+
+
+
+
+ FullSub.dig
+
+
+
+
+ FullSub.dig
+
+
+
+
+ FullSub.dig
+
+
+
+
+ Testcase
+
+
+ Testdata
+
+ # complete test of all 512 possible additions
+C_-1 A_3 A_2 A_1 A_0 B_3 B_2 B_1 B_0 C_3 S_3 S_2 S_1 S_0
+repeat(256) 0 bits(4,n>>4) bits(4,n) bits(5,(n>>4)-(n&15))
+repeat(256) 1 bits(4,n>>4) bits(4,n) bits(5,(n>>4)-(n&15)-1)
+
+
+
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\ No newline at end of file
diff --git a/src/test/resources/dig/test/arith/HalfAdder.dig b/src/test/resources/dig/test/arith/HalfAdder.dig
new file mode 100644
index 000000000..5e5383387
--- /dev/null
+++ b/src/test/resources/dig/test/arith/HalfAdder.dig
@@ -0,0 +1,115 @@
+
+
+ 1
+
+
+ XOr
+
+
+
+
+ And
+
+
+
+
+ In
+
+
+ Label
+ $A$
+
+
+
+
+
+ In
+
+
+ Label
+ $B$
+
+
+
+
+
+ Out
+
+
+ Label
+ $S$
+
+
+
+
+
+ Out
+
+
+ Label
+ $C$
+
+
+
+
+
+ Testcase
+
+
+ Testdata
+
+ A B C S
+0 0 0 0
+0 1 0 1
+1 0 0 1
+1 1 1 0
+
+
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+
\ No newline at end of file
diff --git a/src/test/resources/dig/test/arith/HalfSub.dig b/src/test/resources/dig/test/arith/HalfSub.dig
new file mode 100644
index 000000000..109091182
--- /dev/null
+++ b/src/test/resources/dig/test/arith/HalfSub.dig
@@ -0,0 +1,124 @@
+
+
+ 1
+
+
+ XOr
+
+
+
+
+ And
+
+
+
+
+ In
+
+
+ Label
+ $A$
+
+
+
+
+
+ In
+
+
+ Label
+ $B$
+
+
+
+
+
+ Out
+
+
+ Label
+ $S$
+
+
+
+
+
+ Out
+
+
+ Label
+ $BO$
+
+
+
+
+
+ Not
+
+
+
+
+ Testcase
+
+
+ Testdata
+
+ A B BO S
+0 0 0 0
+0 1 1 1
+1 0 0 1
+1 1 0 0
+
+
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+
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\ No newline at end of file
diff --git a/src/test/resources/dig/test/arith/subTest.dig b/src/test/resources/dig/test/arith/subTest.dig
new file mode 100644
index 000000000..ca96b7661
--- /dev/null
+++ b/src/test/resources/dig/test/arith/subTest.dig
@@ -0,0 +1,292 @@
+
+
+ 1
+
+
+
+ Sub
+
+
+ Bits
+ 4
+
+
+
+
+
+ In
+
+
+ Label
+ B
+
+
+ Bits
+ 4
+
+
+
+
+
+ In
+
+
+ Label
+ A
+
+
+ Bits
+ 4
+
+
+
+
+
+ In
+
+
+ Label
+ C
+
+
+
+
+
+ Splitter
+
+
+ Input Splitting
+ 4,1
+
+
+ Output Splitting
+ 5
+
+
+
+
+
+ Comparator
+
+
+ Bits
+ 5
+
+
+
+
+
+ Out
+
+
+ Label
+ Y
+
+
+
+
+
+ FullSubRC.dig
+
+
+
+
+ Splitter
+
+
+ Input Splitting
+ 4
+
+
+ Output Splitting
+ 1*4
+
+
+
+
+
+ Splitter
+
+
+ Input Splitting
+ 4
+
+
+ Output Splitting
+ 1*4
+
+
+
+
+
+ Splitter
+
+
+ Input Splitting
+ 1*5
+
+
+ Output Splitting
+ 5
+
+
+
+
+
+ Testcase
+
+
+ Testdata
+
+ A B C Y
+
+repeat(1<<9) ((n>>4)&0xf) (n & 0xf) (n>>8) 1
+
+
+
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\ No newline at end of file