diff --git a/src/main/dig/processor/Processor.dig b/src/main/dig/processor/Processor.dig index e576a8dbd..464e98c81 100644 --- a/src/main/dig/processor/Processor.dig +++ b/src/main/dig/processor/Processor.dig @@ -40,7 +40,7 @@ Single-Cycle CPU.}} 16 - + Multiplexer @@ -171,7 +171,7 @@ Single-Cycle CPU.}} 2147483647 - + Driver @@ -521,7 +521,7 @@ Single-Cycle CPU.}} muxA - + Tunnel @@ -603,7 +603,7 @@ Single-Cycle CPU.}} C - + Tunnel @@ -823,7 +823,7 @@ c11,c21,8014,2020,38eb,c31,8014,2030,38e6,1991,ffff,3e09,146,165,154,4400,3ddb,a 16 - + Out @@ -833,6 +833,10 @@ c11,c21,8014,2020,38eb,c31,8014,2030,38e6,1991,ffff,3e09,146,165,154,4400,3ddb,a Data Bus {{de Datenbus}} + + rotation + + Label D @@ -842,60 +846,8 @@ c11,c21,8014,2020,38eb,c31,8014,2030,38e6,1991,ffff,3e09,146,165,154,4400,3ddb,a 16 - - - - Tunnel - - - NetName - A - - - - - - Tunnel - - - rotation - - - - NetName - A - - - - - - Tunnel - - - rotation - - - - NetName - D - - - - Tunnel - - - rotation - - - - NetName - D - - - - Tunnel @@ -908,7 +860,7 @@ c11,c21,8014,2020,38eb,c31,8014,2030,38e6,1991,ffff,3e09,146,165,154,4400,3ddb,a ioW - + Out @@ -923,7 +875,7 @@ c11,c21,8014,2020,38eb,c31,8014,2030,38e6,1991,ffff,3e09,146,165,154,4400,3ddb,a ioW - + Tunnel @@ -937,7 +889,7 @@ c11,c21,8014,2020,38eb,c31,8014,2030,38e6,1991,ffff,3e09,146,165,154,4400,3ddb,a ioR - + Out @@ -952,43 +904,7 @@ c11,c21,8014,2020,38eb,c31,8014,2030,38e6,1991,ffff,3e09,146,165,154,4400,3ddb,a ioR - - - - Rectangle - - - RectHeight - 10 - - - Label - Outputs - - - RectWidth - 9 - - - - - - Rectangle - - - RectHeight - 10 - - - Label - Inputs - - - RectWidth - 9 - - - + @@ -1016,10 +932,6 @@ c11,c21,8014,2020,38eb,c31,8014,2030,38e6,1991,ffff,3e09,146,165,154,4400,3ddb,a - - - - @@ -1032,14 +944,6 @@ c11,c21,8014,2020,38eb,c31,8014,2030,38e6,1991,ffff,3e09,146,165,154,4400,3ddb,a - - - - - - - - @@ -1064,6 +968,10 @@ c11,c21,8014,2020,38eb,c31,8014,2030,38e6,1991,ffff,3e09,146,165,154,4400,3ddb,a + + + + @@ -1077,7 +985,7 @@ c11,c21,8014,2020,38eb,c31,8014,2030,38e6,1991,ffff,3e09,146,165,154,4400,3ddb,a - + @@ -1124,10 +1032,6 @@ c11,c21,8014,2020,38eb,c31,8014,2030,38e6,1991,ffff,3e09,146,165,154,4400,3ddb,a - - - - @@ -1178,7 +1082,7 @@ c11,c21,8014,2020,38eb,c31,8014,2030,38e6,1991,ffff,3e09,146,165,154,4400,3ddb,a - + @@ -1200,6 +1104,10 @@ c11,c21,8014,2020,38eb,c31,8014,2030,38e6,1991,ffff,3e09,146,165,154,4400,3ddb,a + + + + @@ -1236,10 +1144,6 @@ c11,c21,8014,2020,38eb,c31,8014,2030,38e6,1991,ffff,3e09,146,165,154,4400,3ddb,a - - - - @@ -1260,6 +1164,10 @@ c11,c21,8014,2020,38eb,c31,8014,2030,38e6,1991,ffff,3e09,146,165,154,4400,3ddb,a + + + + @@ -1330,7 +1238,7 @@ c11,c21,8014,2020,38eb,c31,8014,2030,38e6,1991,ffff,3e09,146,165,154,4400,3ddb,a - + @@ -1428,10 +1336,6 @@ c11,c21,8014,2020,38eb,c31,8014,2030,38e6,1991,ffff,3e09,146,165,154,4400,3ddb,a - - - - @@ -1509,13 +1413,17 @@ c11,c21,8014,2020,38eb,c31,8014,2030,38e6,1991,ffff,3e09,146,165,154,4400,3ddb,a - - + + + + + + diff --git a/src/main/dig/processor/ProcessorHDL.dig b/src/main/dig/processor/ProcessorHDL.dig index 27cfe3b8d..dbbf39ae9 100644 --- a/src/main/dig/processor/ProcessorHDL.dig +++ b/src/main/dig/processor/ProcessorHDL.dig @@ -319,6 +319,10 @@ Single-Cycle CPU.}} AddrBits 10 + + Label + mem + Bits 16 diff --git a/src/main/dig/processor/ProcessorHDLTest.dig b/src/main/dig/processor/ProcessorHDLTest.dig new file mode 100644 index 000000000..fe463c0e5 --- /dev/null +++ b/src/main/dig/processor/ProcessorHDLTest.dig @@ -0,0 +1,4819 @@ + + + 1 + + + + Clock + + + runRealTime + true + + + Label + Clk + + + Frequency + 2147483647 + + + + + + TestIO.dig + + + Label + Reg3 + + + generic + addr := 3; + + + + + + TestIO.dig + + + Label + Reg32 + + + generic + addr := 32; + + + + + + Testcase + + + Label + MOV + + + Testdata + + # auto generated, do not modify +Clk R1 R2 + +init R1=3; +init R2=4; + +# mov r2,r1 +program(0x121) + +C X X + +# expects +# R1=3 +# R2=3 +0 3 3 + + + + + + + + Testcase + + + Label + ADD + + + Testdata + + # auto generated, do not modify +Clk Carry R1 R2 + +init Carry=0; +init R1=2; +init R2=3; + +# add r1,r2 +program(0x212) + +C X X X + +# expects +# Carry=0 +# R1=5 +# R2=3 +0 0 5 3 + + + + + + + + Testcase + + + Label + ADDI S + + + Testdata + + # auto generated, do not modify +Clk Carry R1 + +init Carry=0; +init R1=2; + +# addi r1,3 +program(0xc13) + +C X X + +# expects +# Carry=0 +# R1=5 +0 0 5 + + + + + + + + Testcase + + + Label + ADDI L + + + Testdata + + # auto generated, do not modify +Clk Carry R1 + +init Carry=0; +init R1=2; + +# addi r1,23 +program(0x8017,0xb10) + +repeat (2) C X X + +# expects +# Carry=0 +# R1=25 +0 0 25 + + + + + + + + Testcase + + + Label + ADD C_in + + + Testdata + + # auto generated, do not modify +Clk Carry R1 R2 + +init Carry=1; +init R1=2; +init R2=3; + +# add r1,r2 +program(0x212) + +C X X X + +# expects +# Carry=0 +# R1=5 +# R2=3 +0 0 5 3 + + + + + + + + Testcase + + + Label + ADDI C_in S + + + Testdata + + # auto generated, do not modify +Clk Carry R1 + +init Carry=1; +init R1=2; + +# addi r1,3 +program(0xc13) + +C X X + +# expects +# Carry=0 +# R1=5 +0 0 5 + + + + + + + + Testcase + + + Label + ADDI C_in L + + + Testdata + + # auto generated, do not modify +Clk Carry R1 + +init Carry=1; +init R1=2; + +# addi r1,23 +program(0x8017,0xb10) + +repeat (2) C X X + +# expects +# Carry=0 +# R1=25 +0 0 25 + + + + + + + + Testcase + + + Label + ADD C_out + + + Testdata + + # auto generated, do not modify +Clk Carry R1 R2 + +init Carry=0; +init R1=-1; +init R2=3; + +# add r1,r2 +program(0x212) + +C X X X + +# expects +# Carry=1 +# R1=2 +# R2=3 +0 1 2 3 + + + + + + + + Testcase + + + Label + ADDI C_out S + + + Testdata + + # auto generated, do not modify +Clk Carry R1 + +init Carry=0; +init R1=-1; + +# addi r1,3 +program(0xc13) + +C X X + +# expects +# Carry=1 +# R1=2 +0 1 2 + + + + + + + + Testcase + + + Label + ADDI C_out L + + + Testdata + + # auto generated, do not modify +Clk Carry R1 + +init Carry=0; +init R1=-1; + +# addi r1,23 +program(0x8017,0xb10) + +repeat (2) C X X + +# expects +# Carry=1 +# R1=22 +0 1 22 + + + + + + + + Testcase + + + Label + ADD C_in C_out + + + Testdata + + # auto generated, do not modify +Clk Carry R1 R2 + +init Carry=1; +init R1=-1; +init R2=3; + +# add r1,r2 +program(0x212) + +C X X X + +# expects +# Carry=1 +# R1=2 +# R2=3 +0 1 2 3 + + + + + + + + Testcase + + + Label + ADDI C_in C_out S + + + Testdata + + # auto generated, do not modify +Clk Carry R1 + +init Carry=1; +init R1=-1; + +# addi r1,3 +program(0xc13) + +C X X + +# expects +# Carry=1 +# R1=2 +0 1 2 + + + + + + + + Testcase + + + Label + ADDI C_in C_out L + + + Testdata + + # auto generated, do not modify +Clk Carry R1 + +init Carry=1; +init R1=-1; + +# addi r1,23 +program(0x8017,0xb10) + +repeat (2) C X X + +# expects +# Carry=1 +# R1=22 +0 1 22 + + + + + + + + Testcase + + + Label + ADC + + + Testdata + + # auto generated, do not modify +Clk Carry R1 R2 + +init Carry=0; +init R1=2; +init R2=3; + +# adc r1,r2 +program(0x312) + +C X X X + +# expects +# Carry=0 +# R1=5 +# R2=3 +0 0 5 3 + + + + + + + + Testcase + + + Label + ADCI S + + + Testdata + + # auto generated, do not modify +Clk Carry R1 + +init Carry=0; +init R1=2; + +# adci r1,3 +program(0xe13) + +C X X + +# expects +# Carry=0 +# R1=5 +0 0 5 + + + + + + + + Testcase + + + Label + ADCI L + + + Testdata + + # auto generated, do not modify +Clk Carry R1 + +init Carry=0; +init R1=2; + +# adci r1,23 +program(0x8017,0xd10) + +repeat (2) C X X + +# expects +# Carry=0 +# R1=25 +0 0 25 + + + + + + + + Testcase + + + Label + ADC C_in + + + Testdata + + # auto generated, do not modify +Clk Carry R1 R2 + +init Carry=1; +init R1=2; +init R2=3; + +# adc r1,r2 +program(0x312) + +C X X X + +# expects +# Carry=0 +# R1=6 +# R2=3 +0 0 6 3 + + + + + + + + Testcase + + + Label + ADCI C_in S + + + Testdata + + # auto generated, do not modify +Clk Carry R1 + +init Carry=1; +init R1=2; + +# adci r1,3 +program(0xe13) + +C X X + +# expects +# Carry=0 +# R1=6 +0 0 6 + + + + + + + + Testcase + + + Label + ADCI C_in L + + + Testdata + + # auto generated, do not modify +Clk Carry R1 + +init Carry=1; +init R1=2; + +# adci r1,23 +program(0x8017,0xd10) + +repeat (2) C X X + +# expects +# Carry=0 +# R1=26 +0 0 26 + + + + + + + + Testcase + + + Label + ADC C_out + + + Testdata + + # auto generated, do not modify +Clk Carry R1 R2 + +init Carry=0; +init R1=-1; +init R2=3; + +# adc r1,r2 +program(0x312) + +C X X X + +# expects +# Carry=1 +# R1=2 +# R2=3 +0 1 2 3 + + + + + + + + Testcase + + + Label + ADCI C_out S + + + Testdata + + # auto generated, do not modify +Clk Carry R1 + +init Carry=0; +init R1=-1; + +# adci r1,3 +program(0xe13) + +C X X + +# expects +# Carry=1 +# R1=2 +0 1 2 + + + + + + + + Testcase + + + Label + ADCI C_out L + + + Testdata + + # auto generated, do not modify +Clk Carry R1 + +init Carry=0; +init R1=-1; + +# adci r1,23 +program(0x8017,0xd10) + +repeat (2) C X X + +# expects +# Carry=1 +# R1=22 +0 1 22 + + + + + + + + Testcase + + + Label + ADC C_in C_out + + + Testdata + + # auto generated, do not modify +Clk Carry R1 R2 + +init Carry=1; +init R1=-1; +init R2=3; + +# adc r1,r2 +program(0x312) + +C X X X + +# expects +# Carry=1 +# R1=3 +# R2=3 +0 1 3 3 + + + + + + + + Testcase + + + Label + ADCI C_in C_out S + + + Testdata + + # auto generated, do not modify +Clk Carry R1 + +init Carry=1; +init R1=-1; + +# adci r1,3 +program(0xe13) + +C X X + +# expects +# Carry=1 +# R1=3 +0 1 3 + + + + + + + + Testcase + + + Label + ADCI C_in C_out L + + + Testdata + + # auto generated, do not modify +Clk Carry R1 + +init Carry=1; +init R1=-1; + +# adci r1,23 +program(0x8017,0xd10) + +repeat (2) C X X + +# expects +# Carry=1 +# R1=23 +0 1 23 + + + + + + + + Testcase + + + Label + SUB + + + Testdata + + # auto generated, do not modify +Clk Carry R1 R2 + +init Carry=0; +init R1=3; +init R2=2; + +# sub r1,r2 +program(0x412) + +C X X X + +# expects +# Carry=0 +# R1=1 +# R2=2 +0 0 1 2 + + + + + + + + Testcase + + + Label + SUBI S + + + Testdata + + # auto generated, do not modify +Clk Carry R1 + +init Carry=0; +init R1=3; + +# subi r1,2 +program(0x1012) + +C X X + +# expects +# Carry=0 +# R1=1 +0 0 1 + + + + + + + + Testcase + + + Label + SUBI L + + + Testdata + + # auto generated, do not modify +Clk Carry R1 + +init Carry=0; +init R1=23; + +# subi r1,22 +program(0x8016,0xf10) + +repeat (2) C X X + +# expects +# Carry=0 +# R1=1 +0 0 1 + + + + + + + + Testcase + + + Label + SUB C_in + + + Testdata + + # auto generated, do not modify +Clk Carry R1 R2 + +init Carry=1; +init R1=3; +init R2=2; + +# sub r1,r2 +program(0x412) + +C X X X + +# expects +# Carry=0 +# R1=1 +# R2=2 +0 0 1 2 + + + + + + + + Testcase + + + Label + SUBI C_in S + + + Testdata + + # auto generated, do not modify +Clk Carry R1 + +init Carry=1; +init R1=3; + +# subi r1,2 +program(0x1012) + +C X X + +# expects +# Carry=0 +# R1=1 +0 0 1 + + + + + + + + Testcase + + + Label + SUBI C_in L + + + Testdata + + # auto generated, do not modify +Clk Carry R1 + +init Carry=1; +init R1=23; + +# subi r1,22 +program(0x8016,0xf10) + +repeat (2) C X X + +# expects +# Carry=0 +# R1=1 +0 0 1 + + + + + + + + Testcase + + + Label + SUB C_out + + + Testdata + + # auto generated, do not modify +Clk Carry R1 R2 + +init Carry=0; +init R1=2; +init R2=3; + +# sub r1,r2 +program(0x412) + +C X X X + +# expects +# Carry=1 +# R1=65535 +# R2=3 +0 1 65535 3 + + + + + + + + Testcase + + + Label + SUBI C_out S + + + Testdata + + # auto generated, do not modify +Clk Carry R1 + +init Carry=0; +init R1=2; + +# subi r1,3 +program(0x1013) + +C X X + +# expects +# Carry=1 +# R1=65535 +0 1 65535 + + + + + + + + Testcase + + + Label + SUBI C_out L + + + Testdata + + # auto generated, do not modify +Clk Carry R1 + +init Carry=0; +init R1=22; + +# subi r1,23 +program(0x8017,0xf10) + +repeat (2) C X X + +# expects +# Carry=1 +# R1=65535 +0 1 65535 + + + + + + + + Testcase + + + Label + SUB C_in C_out + + + Testdata + + # auto generated, do not modify +Clk Carry R1 R2 + +init Carry=1; +init R1=2; +init R2=3; + +# sub r1,r2 +program(0x412) + +C X X X + +# expects +# Carry=1 +# R1=65535 +# R2=3 +0 1 65535 3 + + + + + + + + Testcase + + + Label + SUBI C_in C_out S + + + Testdata + + # auto generated, do not modify +Clk Carry R1 + +init Carry=1; +init R1=2; + +# subi r1,3 +program(0x1013) + +C X X + +# expects +# Carry=1 +# R1=65535 +0 1 65535 + + + + + + + + Testcase + + + Label + SUBI C_in C_out L + + + Testdata + + # auto generated, do not modify +Clk Carry R1 + +init Carry=1; +init R1=22; + +# subi r1,23 +program(0x8017,0xf10) + +repeat (2) C X X + +# expects +# Carry=1 +# R1=65535 +0 1 65535 + + + + + + + + Testcase + + + Label + SBC + + + Testdata + + # auto generated, do not modify +Clk Carry R1 R2 + +init Carry=0; +init R1=3; +init R2=2; + +# sbc r1,r2 +program(0x512) + +C X X X + +# expects +# Carry=0 +# R1=1 +# R2=2 +0 0 1 2 + + + + + + + + Testcase + + + Label + SBCI S + + + Testdata + + # auto generated, do not modify +Clk Carry R1 + +init Carry=0; +init R1=3; + +# sbci r1,2 +program(0x1212) + +C X X + +# expects +# Carry=0 +# R1=1 +0 0 1 + + + + + + + + Testcase + + + Label + SBCI L + + + Testdata + + # auto generated, do not modify +Clk Carry R1 + +init Carry=0; +init R1=23; + +# sbci r1,22 +program(0x8016,0x1110) + +repeat (2) C X X + +# expects +# Carry=0 +# R1=1 +0 0 1 + + + + + + + + Testcase + + + Label + SBC C_in + + + Testdata + + # auto generated, do not modify +Clk Carry R1 R2 + +init Carry=1; +init R1=3; +init R2=2; + +# sbc r1,r2 +program(0x512) + +C X X X + +# expects +# Carry=0 +# R1=0 +# R2=2 +0 0 0 2 + + + + + + + + Testcase + + + Label + SBCI C_in S + + + Testdata + + # auto generated, do not modify +Clk Carry R1 + +init Carry=1; +init R1=3; + +# sbci r1,2 +program(0x1212) + +C X X + +# expects +# Carry=0 +# R1=0 +0 0 0 + + + + + + + + Testcase + + + Label + SBCI C_in L + + + Testdata + + # auto generated, do not modify +Clk Carry R1 + +init Carry=1; +init R1=23; + +# sbci r1,22 +program(0x8016,0x1110) + +repeat (2) C X X + +# expects +# Carry=0 +# R1=0 +0 0 0 + + + + + + + + Testcase + + + Label + SBC C_out + + + Testdata + + # auto generated, do not modify +Clk Carry R1 R2 + +init Carry=0; +init R1=2; +init R2=3; + +# sbc r1,r2 +program(0x512) + +C X X X + +# expects +# Carry=1 +# R1=65535 +# R2=3 +0 1 65535 3 + + + + + + + + Testcase + + + Label + SBCI C_out S + + + Testdata + + # auto generated, do not modify +Clk Carry R1 + +init Carry=0; +init R1=2; + +# sbci r1,3 +program(0x1213) + +C X X + +# expects +# Carry=1 +# R1=65535 +0 1 65535 + + + + + + + + Testcase + + + Label + SBCI C_out L + + + Testdata + + # auto generated, do not modify +Clk Carry R1 + +init Carry=0; +init R1=22; + +# sbci r1,23 +program(0x8017,0x1110) + +repeat (2) C X X + +# expects +# Carry=1 +# R1=65535 +0 1 65535 + + + + + + + + Testcase + + + Label + SBC C_in C_out + + + Testdata + + # auto generated, do not modify +Clk Carry R1 R2 + +init Carry=1; +init R1=2; +init R2=3; + +# sbc r1,r2 +program(0x512) + +C X X X + +# expects +# Carry=1 +# R1=65534 +# R2=3 +0 1 65534 3 + + + + + + + + Testcase + + + Label + SBCI C_in C_out S + + + Testdata + + # auto generated, do not modify +Clk Carry R1 + +init Carry=1; +init R1=2; + +# sbci r1,3 +program(0x1213) + +C X X + +# expects +# Carry=1 +# R1=65534 +0 1 65534 + + + + + + + + Testcase + + + Label + SBCI C_in C_out L + + + Testdata + + # auto generated, do not modify +Clk Carry R1 + +init Carry=1; +init R1=22; + +# sbci r1,23 +program(0x8017,0x1110) + +repeat (2) C X X + +# expects +# Carry=1 +# R1=65534 +0 1 65534 + + + + + + + + Testcase + + + Label + NOT + + + Testdata + + # auto generated, do not modify +Clk R1 + +init R1=0; + +# not r1 +program(0x1a10) + +C X + +# expects +# R1=65535 +0 65535 + + + + + + + + Testcase + + + Label + NEG + + + Testdata + + # auto generated, do not modify +Clk R1 + +init R1=1; + +# neg r1 +program(0x1310) + +C X + +# expects +# R1=65535 +0 65535 + + + + + + + + Testcase + + + Label + AND + + + Testdata + + # auto generated, do not modify +Clk R1 R2 + +init R1=2; +init R2=3; + +# and r1,r2 +program(0x612) + +C X X + +# expects +# R1=2 +# R2=3 +0 2 3 + + + + + + + + Testcase + + + Label + ANDI short + + + Testdata + + # auto generated, do not modify +Clk R1 + +init R1=2; + +# andi r1,3 +program(0x1513) + +C X + +# expects +# R1=2 +0 2 + + + + + + + + Testcase + + + Label + ANDI + + + Testdata + + # auto generated, do not modify +Clk R1 + +init R1=16; + +# andi r1,24 +program(0x8018,0x1410) + +repeat (2) C X + +# expects +# R1=16 +0 16 + + + + + + + + Testcase + + + Label + OR + + + Testdata + + # auto generated, do not modify +Clk R1 R2 + +init R1=2; +init R2=3; + +# or r1,r2 +program(0x712) + +C X X + +# expects +# R1=3 +# R2=3 +0 3 3 + + + + + + + + Testcase + + + Label + ORI short + + + Testdata + + # auto generated, do not modify +Clk R1 + +init R1=2; + +# ori r1,3 +program(0x1713) + +C X + +# expects +# R1=3 +0 3 + + + + + + + + Testcase + + + Label + ORI + + + Testdata + + # auto generated, do not modify +Clk R1 + +init R1=16; + +# ori r1,24 +program(0x8018,0x1610) + +repeat (2) C X + +# expects +# R1=24 +0 24 + + + + + + + + Testcase + + + Label + EOR + + + Testdata + + # auto generated, do not modify +Clk R1 R2 + +init R1=2; +init R2=3; + +# eor r1,r2 +program(0x812) + +C X X + +# expects +# R1=1 +# R2=3 +0 1 3 + + + + + + + + Testcase + + + Label + EORI short + + + Testdata + + # auto generated, do not modify +Clk R1 + +init R1=2; + +# eori r1,3 +program(0x1913) + +C X + +# expects +# R1=1 +0 1 + + + + + + + + Testcase + + + Label + EORI + + + Testdata + + # auto generated, do not modify +Clk R1 + +init R1=16; + +# eori r1,24 +program(0x8018,0x1810) + +repeat (2) C X + +# expects +# R1=8 +0 8 + + + + + + + + Testcase + + + Label + LSL + + + Testdata + + # auto generated, do not modify +Clk R1 + +init R1=8; + +# lsl r1 +program(0x2410) + +C X + +# expects +# R1=16 +0 16 + + + + + + + + Testcase + + + Label + LSR + + + Testdata + + # auto generated, do not modify +Clk R1 + +init R1=8; + +# lsr r1 +program(0x2510) + +C X + +# expects +# R1=4 +0 4 + + + + + + + + Testcase + + + Label + LSR + + + Testdata + + # auto generated, do not modify +Clk R1 + +init R1=65535; + +# lsr r1 +program(0x2510) + +C X + +# expects +# R1=32767 +0 32767 + + + + + + + + Testcase + + + Label + ASR + + + Testdata + + # auto generated, do not modify +Clk R1 + +init R1=8; + +# asr r1 +program(0x2810) + +C X + +# expects +# R1=4 +0 4 + + + + + + + + Testcase + + + Label + ASR + + + Testdata + + # auto generated, do not modify +Clk R1 + +init R1=65535; + +# asr r1 +program(0x2810) + +C X + +# expects +# R1=65535 +0 65535 + + + + + + + + Testcase + + + Label + ROR + + + Testdata + + # auto generated, do not modify +Clk R1 + +init Carry=0; +init R1=8; + +# ror r1 +program(0x2710) + +C X + +# expects +# R1=4 +0 4 + + + + + + + + Testcase + + + Label + ROR + + + Testdata + + # auto generated, do not modify +Clk R1 + +init Carry=1; +init R1=8; + +# ror r1 +program(0x2710) + +C X + +# expects +# R1=32772 +0 32772 + + + + + + + + Testcase + + + Label + ROL + + + Testdata + + # auto generated, do not modify +Clk R1 + +init Carry=0; +init R1=8; + +# rol r1 +program(0x2610) + +C X + +# expects +# R1=16 +0 16 + + + + + + + + Testcase + + + Label + ROL + + + Testdata + + # auto generated, do not modify +Clk R1 + +init Carry=1; +init R1=8; + +# rol r1 +program(0x2610) + +C X + +# expects +# R1=17 +0 17 + + + + + + + + Testcase + + + Label + SWAP + + + Testdata + + # auto generated, do not modify +Clk R1 + +init R1=4660; + +# swap r1 +program(0x2910) + +C X + +# expects +# R1=13330 +0 13330 + + + + + + + + Testcase + + + Label + SWAPN + + + Testdata + + # auto generated, do not modify +Clk R1 + +init R1=4660; + +# swapn r1 +program(0x2a10) + +C X + +# expects +# R1=8515 +0 8515 + + + + + + + + Testcase + + + Label + MUL + + + Testdata + + # auto generated, do not modify +Clk R1 R0 + +init R0=7; +init R1=8; + +# mul r0,r1 +program(0x1b01) + +C X X + +# expects +# R1=8 +# R0=56 +0 8 56 + + + + + + + + Testcase + + + Label + MULI short + + + Testdata + + # auto generated, do not modify +Clk R0 + +init R0=7; + +# muli r0,3 +program(0x1d03) + +C X + +# expects +# R0=21 +0 21 + + + + + + + + Testcase + + + Label + MULI long + + + Testdata + + # auto generated, do not modify +Clk R0 + +init R0=7; + +# muli r0,32 +program(0x8020,0x1c00) + +repeat (2) C X + +# expects +# R0=224 +0 224 + + + + + + + + Testcase + + + Label + LDI small + + + Testdata + + # auto generated, do not modify +Clk R1 + + +# ldi r1,5 +program(0xa15) + +C X + +# expects +# R1=5 +0 5 + + + + + + + + Testcase + + + Label + LDI small + + + Testdata + + # auto generated, do not modify +Clk R1 + + +# ldi r1,15 +program(0xa1f) + +C X + +# expects +# R1=15 +0 15 + + + + + + + + Testcase + + + Label + LDI large + + + Testdata + + # auto generated, do not modify +Clk R1 + + +# ldi r1,16 +program(0x8010,0x910) + +repeat (2) C X + +# expects +# R1=16 +0 16 + + + + + + + + Testcase + + + Label + LDI large + + + Testdata + + # auto generated, do not modify +Clk R1 + + +# ldi r1,0x8000 +program(0x8000,0x911) + +repeat (2) C X + +# expects +# R1=32768 +0 32768 + + + + + + + + Testcase + + + Label + LDS small + + + Testdata + + # auto generated, do not modify +Clk R1 R2 + +memory mem(0)=6; +memory mem(1)=7; + +# lds r1,0 +# lds r2,1 +program(0x3010,0x3021) + +repeat (2) C X X + +# expects +# R1=6 +# R2=7 +0 6 7 + + + + + + + + Testcase + + + Label + LDS large + + + Testdata + + # auto generated, do not modify +Clk R1 + +memory mem(0xff)=8; + +# lds r1,0x0xff +program(0x80ff,0x2f10) + +repeat (2) C X + +# expects +# R1=8 +0 8 + + + + + + + + Testcase + + + Label + STS small + + + Testdata + + # auto generated, do not modify +Clk R2 + +init R1=7; + +# sts 1,r1 +# lds r2,1 +program(0x2e11,0x3021) + +repeat (2) C X + +# expects +# R2=7 +0 7 + + + + + + + + Testcase + + + Label + STS large + + + Testdata + + # auto generated, do not modify +Clk R1 + +init R1=8; + +# sts 0x8000,r1 +# lds r2,0x8000 +program(0x8000,0x2d11,0x8000,0x2f21) + +repeat (4) C X + +# expects +# R1=8 +0 8 + + + + + + + + Testcase + + + Label + LD + + + Testdata + + # auto generated, do not modify +Clk R0 R1 + +memory mem(1)=7; +memory mem(0xff)=8; +init R2=1; +init R3=0xff; + +# ld r0,[r2] +# ld r1,[r3] +program(0x2c02,0x2c13) + +repeat (2) C X X + +# expects +# R0=7 +# R1=8 +0 7 8 + + + + + + + + Testcase + + + Label + LDD + + + Testdata + + # auto generated, do not modify +Clk R0 R1 + +memory mem(3)=7; +memory mem(0xff)=8; +init R2=1; +init R3=0x101; + +# ldd r0,[r2+2] +# ldd r1,[r3-2] +program(0x8002,0x3202,0xfffe,0x3213) + +repeat (4) C X X + +# expects +# R0=7 +# R1=8 +0 7 8 + + + + + + + + Testcase + + + Label + ST + + + Testdata + + # auto generated, do not modify +Clk R0 + +init R1=1; +init R2=7; + +# st [r1],r2 +# lds r0,1 +program(0x2b12,0x3001) + +repeat (2) C X + +# expects +# R0=7 +0 7 + + + + + + + + Testcase + + + Label + STD + + + Testdata + + # auto generated, do not modify +Clk R0 R1 + +init R2=4; +init R3=7; +init R4=8; + +# std [r2+2],r3 +# std [r2-2],r4 +# lds r0,6 +# lds r1,2 +program(0x8002,0x3123,0xfffe,0x3124,0x3006,0x3012) + +repeat (6) C X X + +# expects +# R0=7 +# R1=8 +0 7 8 + + + + + + + + Testcase + + + Label + JMP short + + + Testdata + + # auto generated, do not modify +Clk R0 + +init R0=2; + +# jmp end +# ldi r0, 1 +# end: nop +program(0x3d01,0xa01,0x0) + +repeat (3) C X + +# expects +# R0=2 +0 2 + + + + + + + + Testcase + + + Label + JMP short back + + + Testdata + + # auto generated, do not modify +Clk R0 + +init PC=20; + +# ldi r0,1 +# .org 10 +# code: ldi r0,3 +# .org 20 +# jmp code +# ldi r0, 2 +program(0xa01,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0xa03,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x3df5,0xa02) + +repeat (2) C X + +# expects +# R0=3 +0 3 + + + + + enabled + false + + + + + + Testcase + + + Label + JMP long + + + Testdata + + # auto generated, do not modify +Clk R0 + + +# jmp 130 +# ldi r0, 1 +# .org 130 +# ldi r0,2 +program(0x8082,0x3c00,0xa01,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0xa02) + +repeat (3) C X + +# expects +# R0=2 +0 2 + + + + + + + + Testcase + + + Label + RCALL + + + Testdata + + # auto generated, do not modify +Clk R0 RA + +init R0=3; + +# jmp end +# ldi r0, 1 +# func: ldi r0,1 +# rret ra +# ldi r0,2 +# end: rcall ra,func +program(0x3d04,0xa01,0xa01,0x3b0f,0xa02,0x8002,0x3af0) + +repeat (7) C X X + +# expects +# R0=1 +# RA=7 +0 1 7 + + + + + + + + Testcase + + + Label + CMP 210 + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=0; +init R0=2; +init R1=1; + +# cmp r0,r1 +program(0x1e01) + +C X X X + +# expects +# Carry=0 +# Zero=0 +# Neg=0 +0 0 0 0 + + + + + + + + Testcase + + + Label + CMP 211 + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=1; +init R0=2; +init R1=1; + +# cmp r0,r1 +program(0x1e01) + +C X X X + +# expects +# Carry=0 +# Zero=0 +# Neg=0 +0 0 0 0 + + + + + + + + Testcase + + + Label + CMP 220 + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=0; +init R0=2; +init R1=2; + +# cmp r0,r1 +program(0x1e01) + +C X X X + +# expects +# Carry=0 +# Zero=1 +# Neg=0 +0 0 1 0 + + + + + + + + Testcase + + + Label + CMP 221 + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=1; +init R0=2; +init R1=2; + +# cmp r0,r1 +program(0x1e01) + +C X X X + +# expects +# Carry=0 +# Zero=1 +# Neg=0 +0 0 1 0 + + + + + + + + Testcase + + + Label + CMP 230 + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=0; +init R0=2; +init R1=3; + +# cmp r0,r1 +program(0x1e01) + +C X X X + +# expects +# Carry=1 +# Zero=0 +# Neg=1 +0 1 0 1 + + + + + + + + Testcase + + + Label + CMP 231 + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=1; +init R0=2; +init R1=3; + +# cmp r0,r1 +program(0x1e01) + +C X X X + +# expects +# Carry=1 +# Zero=0 +# Neg=1 +0 1 0 1 + + + + + + + + Testcase + + + Label + CPC 210 + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=0; +init R0=2; +init R1=1; + +# cpc r0,r1 +program(0x1f01) + +C X X X + +# expects +# Carry=0 +# Zero=0 +# Neg=0 +0 0 0 0 + + + + + + + + Testcase + + + Label + CPC 201 + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=1; +init R0=2; +init R1=0; + +# cpc r0,r1 +program(0x1f01) + +C X X X + +# expects +# Carry=0 +# Zero=0 +# Neg=0 +0 0 0 0 + + + + + + + + Testcase + + + Label + CPC 220 + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=0; +init R0=2; +init R1=2; + +# cpc r0,r1 +program(0x1f01) + +C X X X + +# expects +# Carry=0 +# Zero=1 +# Neg=0 +0 0 1 0 + + + + + + + + Testcase + + + Label + CPC 211 + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=1; +init R0=2; +init R1=1; + +# cpc r0,r1 +program(0x1f01) + +C X X X + +# expects +# Carry=0 +# Zero=1 +# Neg=0 +0 0 1 0 + + + + + + + + Testcase + + + Label + CPC 230 + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=0; +init R0=2; +init R1=3; + +# cpc r0,r1 +program(0x1f01) + +C X X X + +# expects +# Carry=1 +# Zero=0 +# Neg=1 +0 1 0 1 + + + + + + + + Testcase + + + Label + CPC 221 + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=1; +init R0=2; +init R1=2; + +# cpc r0,r1 +program(0x1f01) + +C X X X + +# expects +# Carry=1 +# Zero=0 +# Neg=1 +0 1 0 1 + + + + + + + + Testcase + + + Label + CPI 210S + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=0; +init R0=2; + +# cpi r0,1 +program(0x2101) + +C X X X + +# expects +# Carry=0 +# Zero=0 +# Neg=0 +0 0 0 0 + + + + + + + + Testcase + + + Label + CPI 210L + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=0; +init R0=22; + +# cpi r0,21 +program(0x8015,0x2000) + +repeat (2) C X X X + +# expects +# Carry=0 +# Zero=0 +# Neg=0 +0 0 0 0 + + + + + + + + Testcase + + + Label + CPI 211S + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=1; +init R0=2; + +# cpi r0,1 +program(0x2101) + +C X X X + +# expects +# Carry=0 +# Zero=0 +# Neg=0 +0 0 0 0 + + + + + + + + Testcase + + + Label + CPI 211L + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=1; +init R0=22; + +# cpi r0,21 +program(0x8015,0x2000) + +repeat (2) C X X X + +# expects +# Carry=0 +# Zero=0 +# Neg=0 +0 0 0 0 + + + + + + + + Testcase + + + Label + CPI 220S + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=0; +init R0=2; + +# cpi r0,2 +program(0x2102) + +C X X X + +# expects +# Carry=0 +# Zero=1 +# Neg=0 +0 0 1 0 + + + + + + + + Testcase + + + Label + CPI 220L + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=0; +init R0=22; + +# cpi r0,22 +program(0x8016,0x2000) + +repeat (2) C X X X + +# expects +# Carry=0 +# Zero=1 +# Neg=0 +0 0 1 0 + + + + + + + + Testcase + + + Label + CPI 221S + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=1; +init R0=2; + +# cpi r0,2 +program(0x2102) + +C X X X + +# expects +# Carry=0 +# Zero=1 +# Neg=0 +0 0 1 0 + + + + + + + + Testcase + + + Label + CPI 221L + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=1; +init R0=22; + +# cpi r0,22 +program(0x8016,0x2000) + +repeat (2) C X X X + +# expects +# Carry=0 +# Zero=1 +# Neg=0 +0 0 1 0 + + + + + + + + Testcase + + + Label + CPI 230S + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=0; +init R0=2; + +# cpi r0,3 +program(0x2103) + +C X X X + +# expects +# Carry=1 +# Zero=0 +# Neg=1 +0 1 0 1 + + + + + + + + Testcase + + + Label + CPI 230L + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=0; +init R0=22; + +# cpi r0,23 +program(0x8017,0x2000) + +repeat (2) C X X X + +# expects +# Carry=1 +# Zero=0 +# Neg=1 +0 1 0 1 + + + + + + + + Testcase + + + Label + CPI 231S + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=1; +init R0=2; + +# cpi r0,3 +program(0x2103) + +C X X X + +# expects +# Carry=1 +# Zero=0 +# Neg=1 +0 1 0 1 + + + + + + + + Testcase + + + Label + CPI 231L + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=1; +init R0=22; + +# cpi r0,23 +program(0x8017,0x2000) + +repeat (2) C X X X + +# expects +# Carry=1 +# Zero=0 +# Neg=1 +0 1 0 1 + + + + + + + + Testcase + + + Label + CPCI 210S + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=0; +init R0=2; + +# cpci r0,1 +program(0x2301) + +C X X X + +# expects +# Carry=0 +# Zero=0 +# Neg=0 +0 0 0 0 + + + + + + + + Testcase + + + Label + CPCI 210L + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=0; +init R0=22; + +# cpci r0,21 +program(0x8015,0x2200) + +repeat (2) C X X X + +# expects +# Carry=0 +# Zero=0 +# Neg=0 +0 0 0 0 + + + + + + + + Testcase + + + Label + CPCI 201S + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=1; +init R0=2; + +# cpci r0,0 +program(0x2300) + +C X X X + +# expects +# Carry=0 +# Zero=0 +# Neg=0 +0 0 0 0 + + + + + + + + Testcase + + + Label + CPCI 201L + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=1; +init R0=22; + +# cpci r0,20 +program(0x8014,0x2200) + +repeat (2) C X X X + +# expects +# Carry=0 +# Zero=0 +# Neg=0 +0 0 0 0 + + + + + + + + Testcase + + + Label + CPCI 220S + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=0; +init R0=2; + +# cpci r0,2 +program(0x2302) + +C X X X + +# expects +# Carry=0 +# Zero=1 +# Neg=0 +0 0 1 0 + + + + + + + + Testcase + + + Label + CPCI 220L + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=0; +init R0=22; + +# cpci r0,22 +program(0x8016,0x2200) + +repeat (2) C X X X + +# expects +# Carry=0 +# Zero=1 +# Neg=0 +0 0 1 0 + + + + + + + + Testcase + + + Label + CPCI 211S + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=1; +init R0=2; + +# cpci r0,1 +program(0x2301) + +C X X X + +# expects +# Carry=0 +# Zero=1 +# Neg=0 +0 0 1 0 + + + + + + + + Testcase + + + Label + CPCI 211L + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=1; +init R0=22; + +# cpci r0,21 +program(0x8015,0x2200) + +repeat (2) C X X X + +# expects +# Carry=0 +# Zero=1 +# Neg=0 +0 0 1 0 + + + + + + + + Testcase + + + Label + CPCI 230S + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=0; +init R0=2; + +# cpci r0,3 +program(0x2303) + +C X X X + +# expects +# Carry=1 +# Zero=0 +# Neg=1 +0 1 0 1 + + + + + + + + Testcase + + + Label + CPCI 230L + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=0; +init R0=22; + +# cpci r0,23 +program(0x8017,0x2200) + +repeat (2) C X X X + +# expects +# Carry=1 +# Zero=0 +# Neg=1 +0 1 0 1 + + + + + + + + Testcase + + + Label + CPCI 221S + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=1; +init R0=2; + +# cpci r0,2 +program(0x2302) + +C X X X + +# expects +# Carry=1 +# Zero=0 +# Neg=1 +0 1 0 1 + + + + + + + + Testcase + + + Label + CPCI 221L + + + Testdata + + # auto generated, do not modify +Clk Carry Zero Neg + +init Carry=1; +init R0=22; + +# cpci r0,22 +program(0x8016,0x2200) + +repeat (2) C X X X + +# expects +# Carry=1 +# Zero=0 +# Neg=1 +0 1 0 1 + + + + + + + + Testcase + + + Label + BRCS jmp + + + Testdata + + # auto generated, do not modify +Clk R0 + +init Carry=1; +init R0=2; + +# brcs end +# ldi r0, 1 +# end: nop +program(0x3401,0xa01,0x0) + +repeat (3) C X + +# expects +# R0=2 +0 2 + + + + + + + + Testcase + + + Label + BRCS skip + + + Testdata + + # auto generated, do not modify +Clk R0 + +init Carry=0; +init R0=2; + +# brcs end +# ldi r0, 1 +# end: nop +program(0x3401,0xa01,0x0) + +repeat (3) C X + +# expects +# R0=1 +0 1 + + + + + + + + Testcase + + + Label + BRCC jmp + + + Testdata + + # auto generated, do not modify +Clk R0 + +init Carry=0; +init R0=2; + +# brcc end +# ldi r0, 1 +# end: nop +program(0x3701,0xa01,0x0) + +repeat (3) C X + +# expects +# R0=2 +0 2 + + + + + + + + Testcase + + + Label + BRCC skip + + + Testdata + + # auto generated, do not modify +Clk R0 + +init Carry=1; +init R0=2; + +# brcc end +# ldi r0, 1 +# end: nop +program(0x3701,0xa01,0x0) + +repeat (3) C X + +# expects +# R0=1 +0 1 + + + + + + + + Testcase + + + Label + BRMI jmp + + + Testdata + + # auto generated, do not modify +Clk R0 + +init Neg=1; +init R0=2; + +# brmi end +# ldi r0, 1 +# end: nop +program(0x3601,0xa01,0x0) + +repeat (3) C X + +# expects +# R0=2 +0 2 + + + + + + + + Testcase + + + Label + BRMI skip + + + Testdata + + # auto generated, do not modify +Clk R0 + +init Neg=0; +init R0=2; + +# brmi end +# ldi r0, 1 +# end: nop +program(0x3601,0xa01,0x0) + +repeat (3) C X + +# expects +# R0=1 +0 1 + + + + + + + + Testcase + + + Label + BRPL jmp + + + Testdata + + # auto generated, do not modify +Clk R0 + +init Neg=0; +init R0=2; + +# brpl end +# ldi r0, 1 +# end: nop +program(0x3901,0xa01,0x0) + +repeat (3) C X + +# expects +# R0=2 +0 2 + + + + + + + + Testcase + + + Label + BRPL skip + + + Testdata + + # auto generated, do not modify +Clk R0 + +init Neg=1; +init R0=2; + +# brpl end +# ldi r0, 1 +# end: nop +program(0x3901,0xa01,0x0) + +repeat (3) C X + +# expects +# R0=1 +0 1 + + + + + + + + Testcase + + + Label + BREQ jmp + + + Testdata + + # auto generated, do not modify +Clk R0 + +init Zero=1; +init R0=2; + +# breq end +# ldi r0, 1 +# end: nop +program(0x3501,0xa01,0x0) + +repeat (3) C X + +# expects +# R0=2 +0 2 + + + + + + + + Testcase + + + Label + BREQ skip + + + Testdata + + # auto generated, do not modify +Clk R0 + +init Zero=0; +init R0=2; + +# breq end +# ldi r0, 1 +# end: nop +program(0x3501,0xa01,0x0) + +repeat (3) C X + +# expects +# R0=1 +0 1 + + + + + + + + Testcase + + + Label + BRNE jmp + + + Testdata + + # auto generated, do not modify +Clk R0 + +init Zero=0; +init R0=2; + +# brne end +# ldi r0, 1 +# end: nop +program(0x3801,0xa01,0x0) + +repeat (3) C X + +# expects +# R0=2 +0 2 + + + + + + + + Testcase + + + Label + BRNE skip + + + Testdata + + # auto generated, do not modify +Clk R0 + +init Zero=1; +init R0=2; + +# brne end +# ldi r0, 1 +# end: nop +program(0x3801,0xa01,0x0) + +repeat (3) C X + +# expects +# R0=1 +0 1 + + + + + + + + Testcase + + + Label + OUT short + + + Testdata + + # auto generated, do not modify +Clk Reg3 + +init R1=7; + +# out 3,R1 +program(0x3f31) + +C X + +# expects +# Reg3=7 +0 7 + + + + + + + + Testcase + + + Label + OUT long + + + Testdata + + # auto generated, do not modify +Clk Reg32 + +init R1=7; + +# out 32,R1 +program(0x8020,0x3e01) + +repeat (2) C X + +# expects +# Reg32=7 +0 7 + + + + + + + + Testcase + + + Label + OUTR + + + Testdata + + # auto generated, do not modify +Clk Reg3 + +init R0=3; +init R1=7; + +# outr [R0],R1 +program(0x4001) + +C X + +# expects +# Reg3=7 +0 7 + + + + + + + + Testcase + + + Label + IN short + + + Testdata + + # auto generated, do not modify +Clk R1 + +init Reg3=7; + +# in R1,3 +program(0x4213) + +C X + +# expects +# R1=7 +0 7 + + + + + + + + Testcase + + + Label + IN long + + + Testdata + + # auto generated, do not modify +Clk R1 + +init Reg32=7; + +# in R1,32 +program(0x8020,0x4110) + +repeat (2) C X + +# expects +# R1=7 +0 7 + + + + + + + + Testcase + + + Label + INR + + + Testdata + + # auto generated, do not modify +Clk R1 + +init R0=3; +init Reg3=7; + +# inr R1,[R0] +program(0x4310) + +C X + +# expects +# R1=7 +0 7 + + + + + + + + ProcessorHDL.dig + + + + + ROM + + + AddrBits + 16 + + + isProgramMemory + true + + + rotation + + + + Bits + 16 + + + + + + Const + + + rotation + + + + + + + Reset + + + invertOutput + false + + + + + + Driver + + + Bits + 16 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/main/dig/processor/core/WDmuxCtrl.dig b/src/main/dig/processor/core/WDmuxCtrl.dig index da8ccbded..805b211e8 100644 --- a/src/main/dig/processor/core/WDmuxCtrl.dig +++ b/src/main/dig/processor/core/WDmuxCtrl.dig @@ -64,7 +64,7 @@ stPC - + In @@ -74,18 +74,18 @@ ioR - + - - - - + + + + @@ -99,13 +99,9 @@ - + - - - - @@ -114,9 +110,17 @@ + + + + - + + + + +