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removed all old templates

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This commit is contained in:
hneemann 2018-03-14 17:45:38 +01:00
parent 98efae99ba
commit 137363ec4e
14 changed files with 132 additions and 183 deletions
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9
src/main/java/de/neemann/digital/core/element/ElementAttributes.java
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@ -319,9 +319,12 @@ public class ElementAttributes implements HGSMap {
@Override
public Object hgsMapGet(String key) throws HGSEvalException {
Key k = Keys.getKeyByName(key);
if (k == null)
throw new HGSEvalException("key " + key + " not available!");
else
if (k == null) {
if (attributes.containsKey(key))
return attributes.get(key);
else
throw new HGSEvalException("key " + key + " not available!");
} else
return get(k);
}
}

13
src/main/java/de/neemann/digital/hdl/hgs/Value.java
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@ -29,6 +29,19 @@ public final class Value {
throw new HGSEvalException("not a number: " + value.toString());
}
/**
* Converts the given value to a double
*
* @param value the value to convert
* @return the long
* @throws HGSEvalException HGSEvalException
*/
public static double toDouble(Object value) throws HGSEvalException {
if (value instanceof Number)
return ((Number) value).doubleValue();
throw new HGSEvalException("not a number: " + value.toString());
}
/**
* Converts the given value to an int
*

3
src/main/java/de/neemann/digital/hdl/vhdl/VHDLLibrary.java
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@ -5,7 +5,6 @@
*/
package de.neemann.digital.hdl.vhdl;
import de.neemann.digital.core.arithmetic.BitExtender;
import de.neemann.digital.core.arithmetic.Comparator;
import de.neemann.digital.core.basic.*;
import de.neemann.digital.core.element.ElementTypeDescription;
@ -62,7 +61,7 @@ public class VHDLLibrary {
put(DriverInvSel.DESCRIPTION, new DriverVHDL(true));
put(Comparator.DESCRIPTION, new ComparatorVHDL());
put(BitExtender.DESCRIPTION, new BitExtenderVHDL());
// put(BitExtender.DESCRIPTION, new BitExtenderVHDL());
put(PriorityEncoder.DESCRIPTION, new PriorityEncoderVHDL());
put(External.DESCRIPTION, new ExternalVHDL());

6
src/main/java/de/neemann/digital/hdl/vhdl/boards/ClockIntegratorARTIX7.java
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@ -58,16 +58,14 @@ public class ClockIntegratorARTIX7 implements ClockIntegrator {
oldSig.addPort(cIn);
ElementAttributes attr = new ElementAttributes()
.set(new Key<>("cascading", 0), p.isCascading())
.set(new Key<>("D_PARAM", 0), p.d)
.set(new Key<>("M_PARAM", 0), p.m)
.set(new Key<>("DIV_PARAM", 0), p.divider)
.set(new Key<>("DIV4_PARAM", 0), p.divider4)
.set(new Key<>("PERIOD_PARAM", 0.0), clkInPeriod);
if (p.isCascading())
model.addNode(new HDLNode(new Ports().add(cIn).add(cOut), "MMCME2_BASE_CC", attr));
else
model.addNode(new HDLNode(new Ports().add(cIn).add(cOut), "MMCME2_BASE", attr));
model.addNode(new HDLNode(new Ports().add(cIn).add(cOut), "MMCME2_BASE", attr));
}
static final class Parameters {

18
src/main/java/de/neemann/digital/hdl/vhdl/lib/VHDLTemplate.java
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@ -5,8 +5,6 @@
*/
package de.neemann.digital.hdl.vhdl.lib;
import de.neemann.digital.core.element.Key;
import de.neemann.digital.core.element.Keys;
import de.neemann.digital.hdl.hgs.*;
import de.neemann.digital.hdl.hgs.function.FuncAdapter;
import de.neemann.digital.hdl.hgs.function.Function;
@ -159,12 +157,9 @@ public class VHDLTemplate implements VHDLEntity {
out.println("generic map (").inc();
Separator semic = new Separator(",\n");
for (Generic gen : e.getGenerics()) {
Key key = Keys.getKeyByName(gen.name);
if (key != null) {
semic.check(out);
out.print(gen.name).print(" => ").print(gen.format(node.get(key)));
} else
throw new HDLException("unknown generic key: " + gen.name);
semic.check(out);
final Object value = node.getAttributes().hgsMapGet(gen.name);
out.print(gen.name).print(" => ").print(gen.format(value));
}
out.println(")").dec();
}
@ -328,12 +323,13 @@ public class VHDLTemplate implements VHDLEntity {
}
public String format(Object o) throws HGSEvalException {
long v = Value.toLong(o);
switch (type) {
case "integer":
return Long.toString(v);
return Long.toString(Value.toLong(o));
case "real":
return Double.toString(Value.toDouble(o));
case "std_logic":
return "'" + (v & 1) + "'";
return "'" + (Value.toBool(o) ? 1 : 0) + "'";
default:
throw new HGSEvalException("type " + type + " not allowed as generic");
}

40
src/main/resources/vhdl/DIG_BitExtender.tem Normal file
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@ -0,0 +1,40 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
<? if (elem.inputBits>1) {
entityName="DIG_BitExtender";?>
entity DIG_BitExtender is
<?beginGenericPort();?>
generic ( inputBits : integer; <?registerGeneric("inputBits");?>
outputBits : integer); <?registerGeneric("outputBits");?>
port (
PORT_in: in std_logic_vector ((inputBits-1) downto 0);
PORT_out: out std_logic_vector ((outputBits-1) downto 0) );
<?endGenericPort();?>
end DIG_BitExtender;
architecture DIG_BitExtender_arch of DIG_BitExtender is
begin
PORT_out((inputBits-2) downto 0) <= PORT_in((inputBits-2) downto 0);
PORT_out((outputBits-1) downto (inputBits-1)) <= (others => PORT_in(inputBits-1));
end DIG_BitExtender_arch;
<?
} else {
entityName="DIG_BitExtenderSingle";
?>
entity DIG_BitExtenderSingle is
<?beginGenericPort();?>
generic ( outputBits : integer); <?registerGeneric("outputBits");?>
port (
PORT_in: in std_logic;
PORT_out: out std_logic_vector ((outputBits-1) downto 0) );
<?endGenericPort();?>
end DIG_BitExtenderSingle;
architecture DIG_BitExtenderSingle_arch of DIG_BitExtenderSingle is
begin
PORT_out((outputBits-1) downto 0) <= (others => PORT_in);
end DIG_BitExtenderSingle_arch;
<? } ?>

16
src/main/resources/vhdl/DIG_BitExtender.vhdl
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@ -1,16 +0,0 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity DIG_BitExtender is
generic ( inputBits : integer;
outputBits : integer);
port (
PORT_in: in std_logic_vector ((inputBits-1) downto 0);
PORT_out: out std_logic_vector ((outputBits-1) downto 0) );
end DIG_BitExtender;
architecture DIG_BitExtender_arch of DIG_BitExtender is
begin
PORT_out((inputBits-2) downto 0) <= PORT_in((inputBits-2) downto 0);
PORT_out((outputBits-1) downto (inputBits-1)) <= (others => PORT_in(inputBits-1));
end DIG_BitExtender_arch;

14
src/main/resources/vhdl/DIG_BitExtenderSingle.vhdl
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@ -1,14 +0,0 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity DIG_BitExtenderSingle is
generic ( outputBits : integer);
port (
PORT_in: in std_logic;
PORT_out: out std_logic_vector ((outputBits-1) downto 0) );
end DIG_BitExtenderSingle;
architecture DIG_BitExtenderSingle_arch of DIG_BitExtenderSingle is
begin
PORT_out((outputBits-1) downto 0) <= (others => PORT_in);
end DIG_BitExtenderSingle_arch;

30
src/main/resources/vhdl/DIG_MMCME2_BASE.vhdl → src/main/resources/vhdl/DIG_MMCME2_BASE.tem
View File

@ -5,14 +5,21 @@ Library UNISIM;
use UNISIM.vcomponents.all;
entity DIG_MMCME2_BASE is
<?beginGenericPort();?>
generic (
D_PARAM : integer;
M_PARAM : real;
DIV_PARAM : real;
PERIOD_PARAM: real);
D_PARAM : integer;<? registerGeneric("D_PARAM");?>
M_PARAM : real;<? registerGeneric("M_PARAM","real");?>
<? if (elem.cascading) {?>
DIV_PARAM : integer;<? registerGeneric("DIV_PARAM");?>
DIV4_PARAM : integer;<?registerGeneric("DIV4_PARAM");?>
<? } else { ?>
DIV_PARAM : real;<? registerGeneric("DIV_PARAM","real");?>
<? } ?>
PERIOD_PARAM: real);<? registerGeneric("PERIOD_PARAM","real");?>
port (
PORT_in: in std_logic;
PORT_out: out std_logic );
<?endGenericPort();?>
end DIG_MMCME2_BASE;
architecture DIG_MMCME2_BASE_arch of DIG_MMCME2_BASE is
@ -41,10 +48,17 @@ CLKIN1_PERIOD => PERIOD_PARAM,
CLKOUT1_DIVIDE => 1,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
<? if (elem.cascading) {?>
CLKOUT4_DIVIDE => DIV4_PARAM,
CLKOUT5_DIVIDE => 1,
CLKOUT6_DIVIDE => DIV_PARAM,
CLKOUT0_DIVIDE_F => 1.0,
<? } else { ?>
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
CLKOUT6_DIVIDE => 1,
CLKOUT0_DIVIDE_F => DIV_PARAM,
<? } ?>
-- Divide amount for CLKOUT0 (1.000-128.000).
-- CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.01-0.99).
CLKOUT0_DUTY_CYCLE => 0.5,
@ -62,7 +76,11 @@ CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
CLKOUT6_PHASE => 0.0,
<? if (elem.cascading) {?>
CLKOUT4_CASCADE => true, -- Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE)
<? } else { ?>
CLKOUT4_CASCADE => FALSE, -- Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE)
<? } ?>
REF_JITTER1 => 0.0,
-- Reference input jitter in UI (0.000-0.999).
STARTUP_WAIT => TRUE
@ -70,7 +88,11 @@ STARTUP_WAIT => TRUE
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
<? if (elem.cascading) {?>
CLKOUT4 => PORT_out,
<? } else { ?>
CLKOUT0 => PORT_out,
<? } ?>
-- 1-bit output: CLKOUT6
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => feedback,

96
src/main/resources/vhdl/DIG_MMCME2_BASE_CC.vhdl
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@ -1,96 +0,0 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity DIG_MMCME2_BASE_CC is
generic (
D_PARAM : integer;
M_PARAM : real;
DIV_PARAM : integer;
DIV4_PARAM : integer;
PERIOD_PARAM: real);
port (
PORT_in: in std_logic;
PORT_out: out std_logic );
end DIG_MMCME2_BASE_CC;
architecture DIG_MMCME2_BASE_CC_arch of DIG_MMCME2_BASE_CC is
signal DEV_NULL: std_logic;
signal feedback: std_logic;
begin
DEV_NULL <= '0';
-- code taken from the "Vivado Design Suite 7 Series FPGA Libraries Guide" (UG953)
MMCME2_BASE_inst : MMCME2_BASE
generic map (
BANDWIDTH => "OPTIMIZED", -- Jitter programming (OPTIMIZED, HIGH, LOW)
CLKFBOUT_MULT_F => M_PARAM,
-- Multiply value for all CLKOUT (2.000-64.000).
DIVCLK_DIVIDE => D_PARAM,
-- Master division value (1-106)
CLKFBOUT_PHASE => 0.0,
-- Phase offset in degrees of CLKFB (-360.000-360.000).
CLKIN1_PERIOD => PERIOD_PARAM,
-- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
-- CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128)
CLKOUT1_DIVIDE => 1,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => DIV4_PARAM,
CLKOUT5_DIVIDE => 1,
CLKOUT6_DIVIDE => DIV_PARAM,
CLKOUT0_DIVIDE_F => 1.0,
-- Divide amount for CLKOUT0 (1.000-128.000).
-- CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.01-0.99).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
CLKOUT6_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 0.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
CLKOUT6_PHASE => 0.0,
CLKOUT4_CASCADE => true, -- Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE)
REF_JITTER1 => 0.0,
-- Reference input jitter in UI (0.000-0.999).
STARTUP_WAIT => TRUE
-- Delays DONE until MMCM is locked (FALSE, TRUE)
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT4 => PORT_out,
-- 1-bit output: CLKOUT6
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => feedback,
-- 1-bit output: Feedback clock
--CLKFBOUTB => CLKFBOUTB, -- 1-bit output: Inverted CLKFBOUT
-- Status Ports: 1-bit (each) output: MMCM status ports
--LOCKED => LOCKED,
-- 1-bit output: LOCK
-- Clock Inputs: 1-bit (each) input: Clock input
CLKIN1 => PORT_in,
-- 1-bit input: Clock
-- Control Ports: 1-bit (each) input: MMCM control ports
PWRDWN => DEV_NULL,
-- 1-bit input: Power-down
RST => DEV_NULL,
-- 1-bit input: Reset
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => feedback
-- 1-bit input: Feedback clock
);
end DIG_MMCME2_BASE_CC_arch;

4
src/main/resources/vhdl/DIG_Reset.vhdl → src/main/resources/vhdl/DIG_Reset.tem
View File

@ -2,10 +2,12 @@ LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity DIG_Reset is
<?beginGenericPort();?>
generic (
invertOutput : std_logic );
invertOutput : std_logic );<?registerGeneric("invertOutput","std_logic");?>
port (
PORT_Reset: out std_logic );
<?endGenericPort();?>
end DIG_Reset;
architecture DIG_Reset_arch of DIG_Reset is

4
src/main/resources/vhdl/DIG_simpleClockDivider.vhdl → src/main/resources/vhdl/DIG_simpleClockDivider.tem
View File

@ -4,11 +4,13 @@ USE ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
entity DIG_simpleClockDivider is
<?beginGenericPort();?>
generic (
maxCounter : integer );
maxCounter : integer ); <?registerGeneric("maxCounter");?>
port (
PORT_out: out std_logic;
PORT_in: in std_logic );
<?endGenericPort();?>
end DIG_simpleClockDivider;
architecture DIG_simpleClockDivider_arch of DIG_simpleClockDivider is

50
src/test/java/de/neemann/digital/hdl/vhdl/boards/ClockIntegratorARTIX7Test.java
View File

@ -57,7 +57,7 @@ public class ClockIntegratorARTIX7Test extends TestCase {
" D_PARAM => 1,\n" +
" M_PARAM => 12.0,\n" +
" DIV_PARAM => 120.0,\n" +
" PERIOD_PARAM => 10.0 )\n" +
" PERIOD_PARAM => 10.0)\n" +
" port map (\n" +
" PORT_in => PORT_Clk,\n" +
" PORT_out => S1 );\n" +
@ -79,14 +79,14 @@ public class ClockIntegratorARTIX7Test extends TestCase {
"Library UNISIM;\n" +
"use UNISIM.vcomponents.all;\n" +
"entity DIG_MMCME2_BASE is\n" +
" generic (\n" +
" D_PARAM : integer;\n" +
" M_PARAM : real;\n" +
" DIV_PARAM : real;\n" +
" PERIOD_PARAM: real);\n" +
" port (\n" +
" PORT_in: in std_logic;\n" +
" PORT_out: out std_logic );\n" +
" generic (\n" +
" D_PARAM : integer;\n" +
" M_PARAM : real;\n" +
" DIV_PARAM : real;\n" +
" PERIOD_PARAM: real);\n" +
" port (\n" +
" PORT_in: in std_logic;\n" +
" PORT_out: out std_logic );\n" +
"end DIG_MMCME2_BASE;\n" +
"architecture DIG_MMCME2_BASE_arch of DIG_MMCME2_BASE is\n" +
" signal DEV_NULL: std_logic;\n" +
@ -155,7 +155,7 @@ public class ClockIntegratorARTIX7Test extends TestCase {
" PORT_out: out std_logic;\n" +
" PORT_in: in std_logic );\n" +
" end component;\n" +
" component DIG_MMCME2_BASE_CC\n" +
" component DIG_MMCME2_BASE\n" +
" generic (\n" +
" D_PARAM : integer;\n" +
" M_PARAM : real;\n" +
@ -173,13 +173,13 @@ public class ClockIntegratorARTIX7Test extends TestCase {
" port map (\n" +
" PORT_out => S0,\n" +
" PORT_in => S1 );\n" +
" gate1 : DIG_MMCME2_BASE_CC\n" +
" gate1 : DIG_MMCME2_BASE\n" +
" generic map (\n" +
" D_PARAM => 2,\n" +
" M_PARAM => 12.0,\n" +
" DIV_PARAM => 127,\n" +
" DIV4_PARAM => 128,\n" +
" PERIOD_PARAM => 10.0 )\n" +
" PERIOD_PARAM => 10.0)\n" +
" port map (\n" +
" PORT_in => PORT_Clk,\n" +
" PORT_out => S1 );\n" +
@ -200,18 +200,18 @@ public class ClockIntegratorARTIX7Test extends TestCase {
"USE ieee.std_logic_1164.all;\n" +
"Library UNISIM;\n" +
"use UNISIM.vcomponents.all;\n" +
"entity DIG_MMCME2_BASE_CC is\n" +
" generic (\n" +
" D_PARAM : integer;\n" +
" M_PARAM : real;\n" +
" DIV_PARAM : integer;\n" +
" DIV4_PARAM : integer;\n" +
" PERIOD_PARAM: real);\n" +
" port (\n" +
" PORT_in: in std_logic;\n" +
" PORT_out: out std_logic );\n" +
"end DIG_MMCME2_BASE_CC;\n" +
"architecture DIG_MMCME2_BASE_CC_arch of DIG_MMCME2_BASE_CC is\n" +
"entity DIG_MMCME2_BASE is\n" +
" generic (\n" +
" D_PARAM : integer;\n" +
" M_PARAM : real;\n" +
" DIV_PARAM : integer;\n" +
" DIV4_PARAM : integer;\n" +
" PERIOD_PARAM: real);\n" +
" port (\n" +
" PORT_in: in std_logic;\n" +
" PORT_out: out std_logic );\n" +
"end DIG_MMCME2_BASE;\n" +
"architecture DIG_MMCME2_BASE_arch of DIG_MMCME2_BASE is\n" +
" signal DEV_NULL: std_logic;\n" +
" signal feedback: std_logic;\n" +
"begin\n" +
@ -256,7 +256,7 @@ public class ClockIntegratorARTIX7Test extends TestCase {
"RST => DEV_NULL,\n" +
"CLKFBIN => feedback\n" +
");\n" +
"end DIG_MMCME2_BASE_CC_arch;" , TestHelper.removeCommentLines(vhdl));
"end DIG_MMCME2_BASE_arch;" , TestHelper.removeCommentLines(vhdl));
}

12
src/test/java/de/neemann/digital/hdl/vhdl/lib/ClockTest.java
View File

@ -22,7 +22,7 @@ public class ClockTest extends TestCase {
ToBreakRunner br = new ToBreakRunner("dig/hdl/Clock.dig");
String vhdl = new VHDLGenerator(br.getLibrary()).export(br.getCircuit()).toString();
assertEquals("LIBRARY ieee;\n" +
assertEquals(TestHelper.removeCommentLines("LIBRARY ieee;\n" +
"USE ieee.std_logic_1164.all;\n" +
"USE ieee.numeric_std.all;\n" +
"entity main is\n" +
@ -52,7 +52,7 @@ public class ClockTest extends TestCase {
" PORT_in => S1 );\n" +
" gate1 : DIG_simpleClockDivider\n" +
" generic map (\n" +
" maxCounter => 2500000 )\n" +
" maxCounter => 2500000)\n" +
" port map (\n" +
" PORT_in => PORT_Clk,\n" +
" PORT_out => S1 );\n" +
@ -96,7 +96,7 @@ public class ClockTest extends TestCase {
" end if;\n" +
" end process;\n" +
" PORT_out <= state;\n" +
"end DIG_simpleClockDivider_arch;", TestHelper.removeCommentLines(vhdl));
"end DIG_simpleClockDivider_arch;",true), TestHelper.removeCommentLines(vhdl,true));
}
@ -104,7 +104,7 @@ public class ClockTest extends TestCase {
ToBreakRunner br = new ToBreakRunner("dig/hdl/Clock2.dig");
String vhdl = new VHDLGenerator(br.getLibrary()).export(br.getCircuit()).toString();
assertEquals("LIBRARY ieee;\n" +
assertEquals(TestHelper.removeCommentLines("LIBRARY ieee;\n" +
"USE ieee.std_logic_1164.all;\n" +
"USE ieee.numeric_std.all;\n" +
"entity main is\n" +
@ -137,7 +137,7 @@ public class ClockTest extends TestCase {
" PORT_In_2 => S1 );\n" +
" gate1 : DIG_simpleClockDivider\n" +
" generic map (\n" +
" maxCounter => 2500000 )\n" +
" maxCounter => 2500000)\n" +
" port map (\n" +
" PORT_in => PORT_Clk,\n" +
" PORT_out => S1 );\n" +
@ -182,7 +182,7 @@ public class ClockTest extends TestCase {
" end if;\n" +
" end process;\n" +
" PORT_out <= state;\n" +
"end DIG_simpleClockDivider_arch;", TestHelper.removeCommentLines(vhdl));
"end DIG_simpleClockDivider_arch;",true), TestHelper.removeCommentLines(vhdl, true));
}