From 13c555fbd1639d1156976df23dc7a95a69dac7e3 Mon Sep 17 00:00:00 2001
From: hneemann <helmut.neemann@arcor.de>
Date: Sun, 15 Dec 2019 13:46:29 +0100
Subject: [PATCH] enables at least one verilog test, see #394

---
 .../digital/hdl/verilog2/VerilogSimulatorTest.java   | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/src/test/java/de/neemann/digital/hdl/verilog2/VerilogSimulatorTest.java b/src/test/java/de/neemann/digital/hdl/verilog2/VerilogSimulatorTest.java
index 52e685038..de4f7be28 100644
--- a/src/test/java/de/neemann/digital/hdl/verilog2/VerilogSimulatorTest.java
+++ b/src/test/java/de/neemann/digital/hdl/verilog2/VerilogSimulatorTest.java
@@ -72,17 +72,19 @@ public class VerilogSimulatorTest extends TestCase {
         }
     }
 
-    /*
     public void testInSimulatorInOut() throws Exception {
         File examples = new File(Resources.getRoot(), "/dig/test/pinControl");
         try {
-            int tested = new FileScanner(this::checkVerilogExport).noOutput().scan(examples);
+            int tested = new FileScanner(f -> {
+                if (!f.getName().equals("uniTest.dig"))
+                    checkVerilogExport(f);
+            }).noOutput().scan(examples);
             assertEquals(2, tested);
-            assertEquals(2, testBenches);
+            assertEquals(1, testBenches);
         } catch (FileScanner.SkipAllException e) {
             // if iverilog is not installed its also ok
         }
-    }/**/
+    }
 
 
     public void testDistributedInSimulator() throws Exception {
@@ -142,7 +144,7 @@ public class VerilogSimulatorTest extends TestCase {
         try {
             File srcFile = new File(dir, file.getName()
                     .replace('.', '_')
-                    .replace('-', '_')+ ".v");
+                    .replace('-', '_') + ".v");
             CodePrinter out = new CodePrinter(srcFile);
             try (VerilogGenerator gen = new VerilogGenerator(br.getLibrary(), out)) {
                 gen.export(br.getCircuit());