From 1c1a6c3fe9b769a1d34d565c3723e5300b5b6753 Mon Sep 17 00:00:00 2001 From: hneemann Date: Sat, 18 Mar 2017 19:59:52 +0100 Subject: [PATCH] Added two cycle CPU with RAM and ROM sharing the same address space. --- src/main/dig/processor/ClockDiv.dig | 142 ++ src/main/dig/processor/ControlTwoCycle.dig | 575 +++++++ src/main/dig/processor/Memory.dig | 258 ++++ src/main/dig/processor/ProcessorTwoCycle.dig | 1350 +++++++++++++++++ .../digital/integration/TestExamples.java | 2 +- 5 files changed, 2326 insertions(+), 1 deletion(-) create mode 100644 src/main/dig/processor/ClockDiv.dig create mode 100644 src/main/dig/processor/ControlTwoCycle.dig create mode 100644 src/main/dig/processor/Memory.dig create mode 100644 src/main/dig/processor/ProcessorTwoCycle.dig diff --git a/src/main/dig/processor/ClockDiv.dig b/src/main/dig/processor/ClockDiv.dig new file mode 100644 index 000000000..1aa5585ad --- /dev/null +++ b/src/main/dig/processor/ClockDiv.dig @@ -0,0 +1,142 @@ + + + 1 + + + Width + 5 + + + + + Clock + + + Label + Clock + + + Frequency + 500000 + + + + + + T_FF + + + + + Not + + + + + And + + + + + And + + + + + Out + + + Label + C_in + + + + + + Out + + + Label + S_in + + + + + + Out + + + Label + C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/main/dig/processor/ControlTwoCycle.dig b/src/main/dig/processor/ControlTwoCycle.dig new file mode 100644 index 000000000..3a4c0bcf9 --- /dev/null +++ b/src/main/dig/processor/ControlTwoCycle.dig @@ -0,0 +1,575 @@ + + + 1 + + + Description + Leitwerk für einen einfachen Prozessor. +Es arbeitet rein kombinatorisch, es handelt sich +also um ein einfaches Schaltwerk. +Da es vergleichsweise komplex ist (24 +Ausgangsbits), wird es durch einen +entsprechenden ROM-Baustein +realisiert, und nicht durch 24 einzelne Schaltnetze. + + + Width + 5 + + + + + In + + + Description + Der Opcode incl. Immediate Bit + + + Label + Op + + + Bits + 7 + + + + + + Splitter + + + Input Splitting + 7 + + + Output Splitting + 6,1 + + + + + + Multiplexer + + + Bits + 6 + + + + + + Const + + + Value + 0 + + + Bits + 6 + + + + + + ROM + + + Label + Logic + + + Bits + 24 + + + Addr Bits + 6 + + + Data + 0,200080,4004c0,4044c0,4008c0,4048c0,400cc0,4010c0,4014c0,c4,d4,4004c4,4004d4,4044c4, +4044d4,4008c4,4008d4,4048c4,4048d4,400cc4,400cd4,4010c4,4010d4,4014c4,4014d4,402cc0, +402cc4,402cd4,400800,400804,400814,4018c0,401cc0,4058c0,405cc0,4020c0,24c0,28c0,20040a, +689,200006,20001e,85,95,200406,685,8018,10018,18018,28018,30018,38018,1a4,20,24,20018, +240004,24001c,240408,80284,80294,80688,100000,800020 + + + lastDataFile + + /home/hneemann/Dokumente/DHBW/Technische_Informatik_II/Systemnahes_Programmieren/java/assembler3/control.dat + + + + + + + Const + + + + + Out + + + Description + Programm Counter in Register Speichern + + + Label + stPC + + + + + + Splitter + + + Input Splitting + 24 + + + Output Splitting + 1*2,3,1*5,5,3,1*6 + + + + + + Out + + + Description + Wert am Datenbus in Register speichern + + + Label + WE + + + + + + Out + + + Description + Aktiviert das Speichern der Konstanten + + + Label + imm + + + + + + Out + + + Description + absoluten Sprung auslösen + + + Label + absJmp + + + + + + Out + + + Description + Selektor für Mux B + + + Label + muxB + + + Bits + 3 + + + + + + Out + + + Description + SourceRegister auf Datenbus legen + + + Label + srcToD + + + + + + Out + + + Description + Selector für Mux A + + + Label + muxA + + + + + + Out + + + Description + ALU auf den Datenbus legen + + + Label + ALUToBus + + + + + + Out + + + Description + Operation der ALU + + + Label + ALUop + + + Bits + 5 + + + + + + Out + + + Description + Wenn gesetzt führt die ALU eine arithmetische Operation aus, so dass die Flags gespeichert werden müssen. + + + Label + storeFlags + + + + + + Out + + + Description + Art des bedingten Sprunges + + + Label + Branch + + + Bits + 3 + + + + + + Out + + + Description + Ram speichert Daten vom Datenbus + + + Label + st + + + + + + Out + + + Description + Ram gibt Daten auf den Datenbus + + + Label + ld + + + + + + Break + + + Cycles + 600000 + + + Label + Break + + + + + + Out + + + Description + Es wird auf die IO geschrieben + + + Label + ioW + + + + + + Out + + + Description + Es wird IO gelesen + + + Label + ioR + + + + + + PullDown + + + Bits + 24 + + + + + + Or + + + + + In + + + Label + ins + + + + + + And + + + + + Not + + + + + Or + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/main/dig/processor/Memory.dig b/src/main/dig/processor/Memory.dig new file mode 100644 index 000000000..954cba32f --- /dev/null +++ b/src/main/dig/processor/Memory.dig @@ -0,0 +1,258 @@ + + + 1 + + + RAMSinglePort + + + Bits + 16 + + + Addr Bits + 15 + + + + + + ROM + + + isProgramMemory + true + + + Bits + 16 + + + Addr Bits + 15 + + + Data + 140f,20e1,4ce0,20e1,14f7,4cef,6e03,5200,7c00,6ff6,20e1,4ced,2de,20e1,8002,5a0d,3c02, +5c16,2001,20e1,4ce0,20e1,15f9,4cef,6ff1,ffff,59d0,8002,5a0d,2002,20e1,4ce0,20e1,8025, +12f0,4cef,6fe5,ffff,5b1d,401,2ed,4ede,18e1,4efe,18e2,6a0f + + + lastDataFile + /home/hneemann/Dokumente/DHBW/Technische_Informatik_II/Systemnahes_Programmieren/asm/fibonacci.hex + + + + + + Splitter + + + Input Splitting + 16 + + + Output Splitting + 15,1 + + + + + + Out + + + Label + D + + + Bits + 16 + + + + + + In + + + Label + A + + + Bits + 16 + + + + + + Not + + + + + And + + + + + And + + + + + In + + + Label + C + + + + + + In + + + Label + str + + + + + + In + + + Label + ld + + + + + + And + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/main/dig/processor/ProcessorTwoCycle.dig b/src/main/dig/processor/ProcessorTwoCycle.dig new file mode 100644 index 000000000..450812063 --- /dev/null +++ b/src/main/dig/processor/ProcessorTwoCycle.dig @@ -0,0 +1,1350 @@ + + + 1 + + + Description + Einfacher Prozessor, der an die MIPS-Architektur +angelehnt ist. Es handelt sich um eine Harvard +Single-Cycle CPU. + + + + + Register.dig + + + + + Multiplexer + + + Bits + 16 + + + + + + Multiplexer + + + Selector Bits + 3 + + + Bits + 16 + + + + + + ImReg.dig + + + + + Const + + + Value + 0 + + + Bits + 16 + + + + + + Const + + + Value + 255 + + + Bits + 16 + + + + + + Const + + + Value + 4095 + + + Bits + 16 + + + + + + SignExt.dig + + + + + ALU.dig + + + + + Driver + + + rotation + + + + Bits + 16 + + + flipSelPos + true + + + + + + Branch.dig + + + rotation + + + + + + + Splitter + + + Input Splitting + 16 + + + Output Splitting + 4,4,1,7 + + + + + + Driver + + + Bits + 16 + + + flipSelPos + true + + + + + + PC.dig + + + + + Clock + + + Label + Clock + + + Frequency + 500000 + + + + + + Driver + + + rotation + + + + Bits + 16 + + + flipSelPos + true + + + + + + /home/hneemann/Dokumente/Java/digital/src/main/dig/processor/Flags.dig + + + rotation + + + + + + + Tunnel + + + rotation + + + + NetName + stPC + + + + + + Tunnel + + + rotation + + + + NetName + WE + + + + + + Tunnel + + + rotation + + + + NetName + imm + + + + + + Tunnel + + + rotation + + + + NetName + abs + + + + + + Tunnel + + + rotation + + + + NetName + muxB + + + + + + Tunnel + + + rotation + + + + NetName + src2D + + + + + + Tunnel + + + rotation + + + + NetName + muxA + + + + + + Tunnel + + + rotation + + + + NetName + ALU2D + + + + + + Tunnel + + + rotation + + + + NetName + ALUop + + + + + + Tunnel + + + rotation + + + + NetName + sf + + + + + + Tunnel + + + rotation + + + + NetName + br + + + + + + Tunnel + + + rotation + + + + NetName + st + + + + + + Tunnel + + + rotation + + + + NetName + ld + + + + + + Tunnel + + + rotation + + + + NetName + ioW + + + + + + Tunnel + + + rotation + + + + NetName + ioR + + + + + + Tunnel + + + rotation + + + + NetName + stPC + + + + + + Tunnel + + + rotation + + + + NetName + WE + + + + + + Tunnel + + + rotation + + + + NetName + imm + + + + + + Tunnel + + + rotation + + + + NetName + abs + + + + + + Tunnel + + + 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/home/hneemann/Dokumente/Java/digital/src/main/dig/processor/Memory.dig + + + + + Multiplexer + + + Bits + 16 + + + + + + Register + + + Bits + 16 + + + + + + Const + + + + + Tunnel + + + rotation + + + + NetName + C_in + + + + + + Tunnel + + + NetName + C_in + + + + + + Tunnel + + + rotation + + + + NetName + S_in + + + + + + Tunnel + + + NetName + S_in + + + + + + Tunnel + + + rotation + + + + NetName + S_in + + + + + + /home/hneemann/Dokumente/Java/digital/src/main/dig/processor/ControlTwoCycle.dig + + + rotation + + + + + + + /home/hneemann/Dokumente/Java/digital/src/main/dig/processor/ClockDiv.dig + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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a/src/test/java/de/neemann/digital/integration/TestExamples.java +++ b/src/test/java/de/neemann/digital/integration/TestExamples.java @@ -28,7 +28,7 @@ public class TestExamples extends TestCase { */ public void testDistExamples() throws Exception { File examples = new File(Resources.getRoot().getParentFile().getParentFile(), "/main/dig"); - assertEquals(100, new FileScanner(this::check).scan(examples)); + assertEquals(104, new FileScanner(this::check).scan(examples)); assertEquals(52, testCasesInFiles); }