From 38611ea0aa7d57918b708f12f9947c18563b00a6 Mon Sep 17 00:00:00 2001 From: hneemann Date: Sat, 13 Jul 2019 12:46:44 +0200 Subject: [PATCH] Added a 32 bit ram as first non DIL library part. --- .../dig/lib/{ => DIL Chips}/74xx/ReadMe.txt | 0 .../{ => DIL Chips}/74xx/arithmetic/74147.dig | 0 .../{ => DIL Chips}/74xx/arithmetic/74148.dig | 0 .../{ => DIL Chips}/74xx/arithmetic/74181.dig | 0 .../{ => DIL Chips}/74xx/arithmetic/74182.dig | 0 .../{ => DIL Chips}/74xx/arithmetic/74198.dig | 0 .../{ => DIL Chips}/74xx/arithmetic/74280.dig | 0 .../{ => DIL Chips}/74xx/arithmetic/74283.dig | 0 .../{ => DIL Chips}/74xx/arithmetic/74382.dig | 0 .../{ => DIL Chips}/74xx/arithmetic/74682.dig | 0 .../{ => DIL Chips}/74xx/arithmetic/74688.dig | 0 .../{ => DIL Chips}/74xx/arithmetic/7480.dig | 0 .../{ => DIL Chips}/74xx/arithmetic/7483.dig | 0 .../74xx/arithmetic/7483Real.dig | 0 .../{ => DIL Chips}/74xx/arithmetic/7485.dig | 0 .../lib/{ => DIL Chips}/74xx/basic/7400.dig | 0 .../lib/{ => DIL Chips}/74xx/basic/7401.dig | 0 .../lib/{ => DIL Chips}/74xx/basic/7402.dig | 0 .../lib/{ => DIL Chips}/74xx/basic/7403.dig | 0 .../lib/{ => DIL Chips}/74xx/basic/7404.dig | 0 .../lib/{ => DIL Chips}/74xx/basic/7405.dig | 0 .../lib/{ => DIL Chips}/74xx/basic/7408.dig | 0 .../lib/{ => DIL Chips}/74xx/basic/7409.dig | 0 .../lib/{ => DIL Chips}/74xx/basic/7410.dig | 0 .../lib/{ => DIL Chips}/74xx/basic/7411.dig | 0 .../lib/{ => DIL Chips}/74xx/basic/7412.dig | 0 .../lib/{ => DIL Chips}/74xx/basic/7413.dig | 0 .../lib/{ => DIL Chips}/74xx/basic/74133.dig | 0 .../lib/{ => DIL Chips}/74xx/basic/7414.dig | 0 .../lib/{ => DIL Chips}/74xx/basic/7415.dig | 0 .../lib/{ => DIL Chips}/74xx/basic/7420.dig | 0 .../lib/{ => DIL Chips}/74xx/basic/7421.dig | 0 .../lib/{ => DIL Chips}/74xx/basic/7425.dig | 0 .../lib/{ => DIL Chips}/74xx/basic/74260.dig | 0 .../lib/{ => DIL Chips}/74xx/basic/74266.dig | 0 .../lib/{ => DIL Chips}/74xx/basic/7427.dig | 0 .../lib/{ => DIL Chips}/74xx/basic/7428.dig | 0 .../lib/{ => DIL Chips}/74xx/basic/7430.dig | 0 .../lib/{ => DIL Chips}/74xx/basic/7432.dig | 0 .../lib/{ => DIL Chips}/74xx/basic/7440.dig | 0 .../lib/{ => DIL Chips}/74xx/basic/744075.dig | 0 .../lib/{ => DIL Chips}/74xx/basic/7451.dig | 0 .../lib/{ => DIL Chips}/74xx/basic/7454.dig | 0 .../lib/{ => DIL Chips}/74xx/basic/7455.dig | 0 .../lib/{ => DIL Chips}/74xx/basic/7458.dig | 0 .../lib/{ => DIL Chips}/74xx/basic/7486.dig | 0 .../{ => DIL Chips}/74xx/counter/74160.dig | 0 .../{ => DIL Chips}/74xx/counter/74161.dig | 0 .../{ => DIL Chips}/74xx/counter/74162.dig | 0 .../74xx/counter/74162Real.dig | 0 .../{ => DIL Chips}/74xx/counter/74163.dig | 0 .../{ => DIL Chips}/74xx/counter/74191.dig | 0 .../{ => DIL Chips}/74xx/counter/74590.dig | 0 .../74xx/counter/74779-inc.dig | 0 .../{ => DIL Chips}/74xx/counter/74779.dig | 0 .../lib/{ => DIL Chips}/74xx/display/7447.dig | 0 .../lib/{ => DIL Chips}/74xx/display/7448.dig | 0 .../lib/{ => DIL Chips}/74xx/driver/7406.dig | 0 .../lib/{ => DIL Chips}/74xx/driver/7407.dig | 0 .../lib/{ => DIL Chips}/74xx/driver/7416.dig | 0 .../lib/{ => DIL Chips}/74xx/driver/7417.dig | 0 .../lib/{ => DIL Chips}/74xx/driver/74244.dig | 0 .../lib/{ => DIL Chips}/74xx/driver/74245.dig | 0 .../lib/{ => DIL Chips}/74xx/driver/74540.dig | 0 .../lib/{ => DIL Chips}/74xx/driver/74541.dig | 0 .../{ => DIL Chips}/74xx/flipflops/74107.dig | 0 .../{ => DIL Chips}/74xx/flipflops/74109.dig | 0 .../{ => DIL Chips}/74xx/flipflops/74112.dig | 0 .../{ => DIL Chips}/74xx/flipflops/74116.dig | 0 .../{ => DIL Chips}/74xx/flipflops/74173.dig | 0 .../{ => DIL Chips}/74xx/flipflops/74174.dig | 0 .../{ => DIL Chips}/74xx/flipflops/74273.dig | 0 .../74xx/flipflops/74373-D-inc.dig | 0 .../{ => DIL Chips}/74xx/flipflops/74373.dig | 0 .../{ => DIL Chips}/74xx/flipflops/74374.dig | 0 .../{ => DIL Chips}/74xx/flipflops/7474.dig | 0 .../{ => DIL Chips}/74xx/flipflops/7476.dig | 0 .../lib/{ => DIL Chips}/74xx/memory/74189.dig | 0 .../74xx/memory/74670-D-inc.dig | 0 .../lib/{ => DIL Chips}/74xx/memory/74670.dig | 0 .../lib/{ => DIL Chips}/74xx/memory/7489.dig | 0 .../{ => DIL Chips}/74xx/plexers/74138.dig | 0 .../{ => DIL Chips}/74xx/plexers/74139.dig | 0 .../{ => DIL Chips}/74xx/plexers/74150.dig | 0 .../{ => DIL Chips}/74xx/plexers/74151.dig | 0 .../{ => DIL Chips}/74xx/plexers/74153.dig | 0 .../{ => DIL Chips}/74xx/plexers/74154.dig | 0 .../{ => DIL Chips}/74xx/plexers/74157.dig | 0 .../{ => DIL Chips}/74xx/plexers/74238.dig | 0 .../{ => DIL Chips}/74xx/plexers/74253.dig | 0 .../lib/{ => DIL Chips}/74xx/plexers/7442.dig | 0 .../74xx/shift register/74164.dig | 0 .../74xx/shift register/74165.dig | 0 .../74xx/shift register/74166.dig | 0 .../dig/lib/{ => DIL Chips}/EPROMs/27c801.dig | 0 .../dig/lib/{ => DIL Chips}/EPROMs/28c010.dig | 0 .../dig/lib/{ => DIL Chips}/EPROMs/28c16.dig | 0 .../dig/lib/{ => DIL Chips}/EPROMs/28c256.dig | 0 .../dig/lib/{ => DIL Chips}/EPROMs/28c512.dig | 0 .../dig/lib/{ => DIL Chips}/EPROMs/28c64.dig | 0 .../dig/lib/{ => DIL Chips}/RAMs/A623308A.dig | 0 src/main/dig/lib/RAMs/RAM32Bit.dig | 1407 +++++++++++++++++ src/main/dig/lib/RAMs/outDataGen-inc.dig | 678 ++++++++ src/main/dig/lib/RAMs/strDataGen-inc.dig | 404 +++++ src/main/dig/lib/RAMs/strGen-inc.dig | 544 +++++++ .../hdl/verilog2/VerilogSimulatorTest.java | 4 +- .../digital/hdl/vhdl2/VHDLSimulatorTest.java | 15 +- .../digital/integration/TestExamples.java | 8 +- .../neemann/digital/integration/TestLib.java | 2 +- .../dig/test/vhdl/generics/Ram32BitTest.dig | 257 +++ 110 files changed, 3304 insertions(+), 15 deletions(-) rename src/main/dig/lib/{ => DIL Chips}/74xx/ReadMe.txt (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/arithmetic/74147.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/arithmetic/74148.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/arithmetic/74181.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/arithmetic/74182.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/arithmetic/74198.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/arithmetic/74280.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/arithmetic/74283.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/arithmetic/74382.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/arithmetic/74682.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/arithmetic/74688.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/arithmetic/7480.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/arithmetic/7483.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/arithmetic/7483Real.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/arithmetic/7485.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/basic/7400.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/basic/7401.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/basic/7402.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/basic/7403.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/basic/7404.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/basic/7405.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/basic/7408.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/basic/7409.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/basic/7410.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/basic/7411.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/basic/7412.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/basic/7413.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/basic/74133.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/basic/7414.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/basic/7415.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/basic/7420.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/basic/7421.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/basic/7425.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/basic/74260.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/basic/74266.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/basic/7427.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/basic/7428.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/basic/7430.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/basic/7432.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/basic/7440.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/basic/744075.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/basic/7451.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/basic/7454.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/basic/7455.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/basic/7458.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/basic/7486.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/counter/74160.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/counter/74161.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/counter/74162.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/counter/74162Real.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/counter/74163.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/counter/74191.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/counter/74590.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/counter/74779-inc.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/counter/74779.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/display/7447.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/display/7448.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/driver/7406.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/driver/7407.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/driver/7416.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/driver/7417.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/driver/74244.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/driver/74245.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/driver/74540.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/driver/74541.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/flipflops/74107.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/flipflops/74109.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/flipflops/74112.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/flipflops/74116.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/flipflops/74173.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/flipflops/74174.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/flipflops/74273.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/flipflops/74373-D-inc.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/flipflops/74373.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/flipflops/74374.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/flipflops/7474.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/flipflops/7476.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/memory/74189.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/memory/74670-D-inc.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/memory/74670.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/memory/7489.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/plexers/74138.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/plexers/74139.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/plexers/74150.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/plexers/74151.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/plexers/74153.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/plexers/74154.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/plexers/74157.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/plexers/74238.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/plexers/74253.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/plexers/7442.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/shift register/74164.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/shift register/74165.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/74xx/shift register/74166.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/EPROMs/27c801.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/EPROMs/28c010.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/EPROMs/28c16.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/EPROMs/28c256.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/EPROMs/28c512.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/EPROMs/28c64.dig (100%) rename src/main/dig/lib/{ => DIL Chips}/RAMs/A623308A.dig (100%) create mode 100644 src/main/dig/lib/RAMs/RAM32Bit.dig create mode 100644 src/main/dig/lib/RAMs/outDataGen-inc.dig create mode 100644 src/main/dig/lib/RAMs/strDataGen-inc.dig create mode 100644 src/main/dig/lib/RAMs/strGen-inc.dig create mode 100644 src/test/resources/dig/test/vhdl/generics/Ram32BitTest.dig diff --git a/src/main/dig/lib/74xx/ReadMe.txt b/src/main/dig/lib/DIL Chips/74xx/ReadMe.txt similarity index 100% rename from src/main/dig/lib/74xx/ReadMe.txt rename to src/main/dig/lib/DIL Chips/74xx/ReadMe.txt diff --git a/src/main/dig/lib/74xx/arithmetic/74147.dig b/src/main/dig/lib/DIL Chips/74xx/arithmetic/74147.dig similarity index 100% rename from src/main/dig/lib/74xx/arithmetic/74147.dig rename to src/main/dig/lib/DIL Chips/74xx/arithmetic/74147.dig diff --git a/src/main/dig/lib/74xx/arithmetic/74148.dig b/src/main/dig/lib/DIL Chips/74xx/arithmetic/74148.dig similarity index 100% rename from src/main/dig/lib/74xx/arithmetic/74148.dig rename to src/main/dig/lib/DIL Chips/74xx/arithmetic/74148.dig diff --git a/src/main/dig/lib/74xx/arithmetic/74181.dig b/src/main/dig/lib/DIL Chips/74xx/arithmetic/74181.dig similarity index 100% rename from src/main/dig/lib/74xx/arithmetic/74181.dig rename to src/main/dig/lib/DIL Chips/74xx/arithmetic/74181.dig diff --git a/src/main/dig/lib/74xx/arithmetic/74182.dig b/src/main/dig/lib/DIL Chips/74xx/arithmetic/74182.dig similarity index 100% rename from src/main/dig/lib/74xx/arithmetic/74182.dig rename to src/main/dig/lib/DIL Chips/74xx/arithmetic/74182.dig diff --git a/src/main/dig/lib/74xx/arithmetic/74198.dig b/src/main/dig/lib/DIL Chips/74xx/arithmetic/74198.dig similarity index 100% rename from src/main/dig/lib/74xx/arithmetic/74198.dig rename to src/main/dig/lib/DIL Chips/74xx/arithmetic/74198.dig diff --git a/src/main/dig/lib/74xx/arithmetic/74280.dig b/src/main/dig/lib/DIL Chips/74xx/arithmetic/74280.dig similarity index 100% rename from src/main/dig/lib/74xx/arithmetic/74280.dig rename to src/main/dig/lib/DIL Chips/74xx/arithmetic/74280.dig diff --git a/src/main/dig/lib/74xx/arithmetic/74283.dig b/src/main/dig/lib/DIL Chips/74xx/arithmetic/74283.dig similarity index 100% rename from src/main/dig/lib/74xx/arithmetic/74283.dig rename to src/main/dig/lib/DIL Chips/74xx/arithmetic/74283.dig diff --git a/src/main/dig/lib/74xx/arithmetic/74382.dig b/src/main/dig/lib/DIL Chips/74xx/arithmetic/74382.dig similarity index 100% rename from src/main/dig/lib/74xx/arithmetic/74382.dig rename to src/main/dig/lib/DIL Chips/74xx/arithmetic/74382.dig diff --git a/src/main/dig/lib/74xx/arithmetic/74682.dig b/src/main/dig/lib/DIL Chips/74xx/arithmetic/74682.dig similarity index 100% rename from src/main/dig/lib/74xx/arithmetic/74682.dig rename to src/main/dig/lib/DIL Chips/74xx/arithmetic/74682.dig diff --git a/src/main/dig/lib/74xx/arithmetic/74688.dig b/src/main/dig/lib/DIL Chips/74xx/arithmetic/74688.dig similarity index 100% rename from src/main/dig/lib/74xx/arithmetic/74688.dig rename to src/main/dig/lib/DIL Chips/74xx/arithmetic/74688.dig diff --git a/src/main/dig/lib/74xx/arithmetic/7480.dig b/src/main/dig/lib/DIL Chips/74xx/arithmetic/7480.dig similarity index 100% rename from src/main/dig/lib/74xx/arithmetic/7480.dig rename to src/main/dig/lib/DIL Chips/74xx/arithmetic/7480.dig diff --git a/src/main/dig/lib/74xx/arithmetic/7483.dig b/src/main/dig/lib/DIL Chips/74xx/arithmetic/7483.dig similarity index 100% rename from src/main/dig/lib/74xx/arithmetic/7483.dig rename to src/main/dig/lib/DIL Chips/74xx/arithmetic/7483.dig diff --git a/src/main/dig/lib/74xx/arithmetic/7483Real.dig b/src/main/dig/lib/DIL Chips/74xx/arithmetic/7483Real.dig similarity index 100% rename from src/main/dig/lib/74xx/arithmetic/7483Real.dig rename to src/main/dig/lib/DIL Chips/74xx/arithmetic/7483Real.dig diff --git a/src/main/dig/lib/74xx/arithmetic/7485.dig b/src/main/dig/lib/DIL Chips/74xx/arithmetic/7485.dig similarity index 100% rename from src/main/dig/lib/74xx/arithmetic/7485.dig rename to src/main/dig/lib/DIL Chips/74xx/arithmetic/7485.dig diff --git a/src/main/dig/lib/74xx/basic/7400.dig b/src/main/dig/lib/DIL Chips/74xx/basic/7400.dig similarity index 100% rename from src/main/dig/lib/74xx/basic/7400.dig rename to src/main/dig/lib/DIL Chips/74xx/basic/7400.dig diff --git a/src/main/dig/lib/74xx/basic/7401.dig b/src/main/dig/lib/DIL Chips/74xx/basic/7401.dig similarity index 100% rename from src/main/dig/lib/74xx/basic/7401.dig rename to src/main/dig/lib/DIL Chips/74xx/basic/7401.dig diff --git a/src/main/dig/lib/74xx/basic/7402.dig b/src/main/dig/lib/DIL Chips/74xx/basic/7402.dig similarity index 100% rename from src/main/dig/lib/74xx/basic/7402.dig rename to src/main/dig/lib/DIL Chips/74xx/basic/7402.dig diff --git a/src/main/dig/lib/74xx/basic/7403.dig b/src/main/dig/lib/DIL Chips/74xx/basic/7403.dig similarity index 100% rename from src/main/dig/lib/74xx/basic/7403.dig rename to src/main/dig/lib/DIL Chips/74xx/basic/7403.dig diff --git a/src/main/dig/lib/74xx/basic/7404.dig b/src/main/dig/lib/DIL Chips/74xx/basic/7404.dig similarity index 100% rename from src/main/dig/lib/74xx/basic/7404.dig rename to src/main/dig/lib/DIL Chips/74xx/basic/7404.dig diff --git a/src/main/dig/lib/74xx/basic/7405.dig b/src/main/dig/lib/DIL Chips/74xx/basic/7405.dig similarity index 100% rename from src/main/dig/lib/74xx/basic/7405.dig rename to src/main/dig/lib/DIL Chips/74xx/basic/7405.dig diff --git a/src/main/dig/lib/74xx/basic/7408.dig b/src/main/dig/lib/DIL Chips/74xx/basic/7408.dig similarity index 100% rename from src/main/dig/lib/74xx/basic/7408.dig rename to src/main/dig/lib/DIL Chips/74xx/basic/7408.dig diff --git a/src/main/dig/lib/74xx/basic/7409.dig b/src/main/dig/lib/DIL Chips/74xx/basic/7409.dig similarity index 100% rename from src/main/dig/lib/74xx/basic/7409.dig rename to src/main/dig/lib/DIL Chips/74xx/basic/7409.dig diff --git a/src/main/dig/lib/74xx/basic/7410.dig b/src/main/dig/lib/DIL Chips/74xx/basic/7410.dig similarity index 100% rename from src/main/dig/lib/74xx/basic/7410.dig rename to src/main/dig/lib/DIL Chips/74xx/basic/7410.dig diff --git a/src/main/dig/lib/74xx/basic/7411.dig b/src/main/dig/lib/DIL Chips/74xx/basic/7411.dig similarity index 100% rename from src/main/dig/lib/74xx/basic/7411.dig rename to src/main/dig/lib/DIL Chips/74xx/basic/7411.dig diff --git a/src/main/dig/lib/74xx/basic/7412.dig b/src/main/dig/lib/DIL Chips/74xx/basic/7412.dig similarity index 100% rename from src/main/dig/lib/74xx/basic/7412.dig rename to src/main/dig/lib/DIL Chips/74xx/basic/7412.dig diff --git a/src/main/dig/lib/74xx/basic/7413.dig b/src/main/dig/lib/DIL Chips/74xx/basic/7413.dig similarity index 100% rename from src/main/dig/lib/74xx/basic/7413.dig rename to src/main/dig/lib/DIL Chips/74xx/basic/7413.dig diff --git a/src/main/dig/lib/74xx/basic/74133.dig b/src/main/dig/lib/DIL Chips/74xx/basic/74133.dig similarity index 100% rename from src/main/dig/lib/74xx/basic/74133.dig rename to src/main/dig/lib/DIL Chips/74xx/basic/74133.dig diff --git a/src/main/dig/lib/74xx/basic/7414.dig b/src/main/dig/lib/DIL Chips/74xx/basic/7414.dig similarity index 100% rename from src/main/dig/lib/74xx/basic/7414.dig rename to src/main/dig/lib/DIL Chips/74xx/basic/7414.dig diff --git a/src/main/dig/lib/74xx/basic/7415.dig b/src/main/dig/lib/DIL Chips/74xx/basic/7415.dig similarity index 100% rename from src/main/dig/lib/74xx/basic/7415.dig rename to src/main/dig/lib/DIL Chips/74xx/basic/7415.dig diff --git a/src/main/dig/lib/74xx/basic/7420.dig b/src/main/dig/lib/DIL Chips/74xx/basic/7420.dig similarity index 100% rename from src/main/dig/lib/74xx/basic/7420.dig rename to src/main/dig/lib/DIL Chips/74xx/basic/7420.dig diff --git a/src/main/dig/lib/74xx/basic/7421.dig b/src/main/dig/lib/DIL Chips/74xx/basic/7421.dig similarity index 100% rename from src/main/dig/lib/74xx/basic/7421.dig rename to src/main/dig/lib/DIL Chips/74xx/basic/7421.dig diff --git a/src/main/dig/lib/74xx/basic/7425.dig b/src/main/dig/lib/DIL Chips/74xx/basic/7425.dig similarity index 100% rename from src/main/dig/lib/74xx/basic/7425.dig rename to src/main/dig/lib/DIL Chips/74xx/basic/7425.dig diff --git a/src/main/dig/lib/74xx/basic/74260.dig b/src/main/dig/lib/DIL Chips/74xx/basic/74260.dig similarity index 100% rename from src/main/dig/lib/74xx/basic/74260.dig rename to src/main/dig/lib/DIL Chips/74xx/basic/74260.dig diff --git a/src/main/dig/lib/74xx/basic/74266.dig b/src/main/dig/lib/DIL Chips/74xx/basic/74266.dig similarity index 100% rename from src/main/dig/lib/74xx/basic/74266.dig rename to src/main/dig/lib/DIL Chips/74xx/basic/74266.dig diff --git a/src/main/dig/lib/74xx/basic/7427.dig b/src/main/dig/lib/DIL Chips/74xx/basic/7427.dig similarity index 100% rename from src/main/dig/lib/74xx/basic/7427.dig rename to src/main/dig/lib/DIL Chips/74xx/basic/7427.dig diff --git a/src/main/dig/lib/74xx/basic/7428.dig b/src/main/dig/lib/DIL Chips/74xx/basic/7428.dig similarity index 100% rename from src/main/dig/lib/74xx/basic/7428.dig rename to src/main/dig/lib/DIL Chips/74xx/basic/7428.dig diff --git a/src/main/dig/lib/74xx/basic/7430.dig b/src/main/dig/lib/DIL Chips/74xx/basic/7430.dig similarity index 100% rename from src/main/dig/lib/74xx/basic/7430.dig rename to src/main/dig/lib/DIL Chips/74xx/basic/7430.dig diff --git a/src/main/dig/lib/74xx/basic/7432.dig b/src/main/dig/lib/DIL Chips/74xx/basic/7432.dig similarity index 100% rename from src/main/dig/lib/74xx/basic/7432.dig rename to src/main/dig/lib/DIL Chips/74xx/basic/7432.dig diff --git a/src/main/dig/lib/74xx/basic/7440.dig b/src/main/dig/lib/DIL Chips/74xx/basic/7440.dig similarity index 100% rename from src/main/dig/lib/74xx/basic/7440.dig rename to src/main/dig/lib/DIL Chips/74xx/basic/7440.dig diff --git a/src/main/dig/lib/74xx/basic/744075.dig b/src/main/dig/lib/DIL Chips/74xx/basic/744075.dig similarity index 100% rename from src/main/dig/lib/74xx/basic/744075.dig rename to src/main/dig/lib/DIL Chips/74xx/basic/744075.dig diff --git a/src/main/dig/lib/74xx/basic/7451.dig b/src/main/dig/lib/DIL Chips/74xx/basic/7451.dig similarity index 100% rename from src/main/dig/lib/74xx/basic/7451.dig rename to src/main/dig/lib/DIL Chips/74xx/basic/7451.dig diff --git a/src/main/dig/lib/74xx/basic/7454.dig b/src/main/dig/lib/DIL Chips/74xx/basic/7454.dig similarity index 100% rename from src/main/dig/lib/74xx/basic/7454.dig rename to src/main/dig/lib/DIL Chips/74xx/basic/7454.dig diff --git a/src/main/dig/lib/74xx/basic/7455.dig b/src/main/dig/lib/DIL Chips/74xx/basic/7455.dig similarity index 100% rename from src/main/dig/lib/74xx/basic/7455.dig rename to src/main/dig/lib/DIL Chips/74xx/basic/7455.dig diff --git a/src/main/dig/lib/74xx/basic/7458.dig b/src/main/dig/lib/DIL Chips/74xx/basic/7458.dig similarity index 100% rename from src/main/dig/lib/74xx/basic/7458.dig rename to src/main/dig/lib/DIL Chips/74xx/basic/7458.dig diff --git a/src/main/dig/lib/74xx/basic/7486.dig b/src/main/dig/lib/DIL Chips/74xx/basic/7486.dig similarity index 100% rename from src/main/dig/lib/74xx/basic/7486.dig rename to src/main/dig/lib/DIL Chips/74xx/basic/7486.dig diff --git a/src/main/dig/lib/74xx/counter/74160.dig b/src/main/dig/lib/DIL Chips/74xx/counter/74160.dig similarity index 100% rename from src/main/dig/lib/74xx/counter/74160.dig rename to src/main/dig/lib/DIL Chips/74xx/counter/74160.dig diff --git a/src/main/dig/lib/74xx/counter/74161.dig b/src/main/dig/lib/DIL Chips/74xx/counter/74161.dig similarity index 100% rename from src/main/dig/lib/74xx/counter/74161.dig rename to src/main/dig/lib/DIL Chips/74xx/counter/74161.dig diff --git a/src/main/dig/lib/74xx/counter/74162.dig b/src/main/dig/lib/DIL Chips/74xx/counter/74162.dig similarity index 100% rename from src/main/dig/lib/74xx/counter/74162.dig rename to src/main/dig/lib/DIL Chips/74xx/counter/74162.dig diff --git a/src/main/dig/lib/74xx/counter/74162Real.dig b/src/main/dig/lib/DIL Chips/74xx/counter/74162Real.dig similarity index 100% rename from src/main/dig/lib/74xx/counter/74162Real.dig rename to src/main/dig/lib/DIL Chips/74xx/counter/74162Real.dig diff --git a/src/main/dig/lib/74xx/counter/74163.dig b/src/main/dig/lib/DIL Chips/74xx/counter/74163.dig similarity index 100% rename from src/main/dig/lib/74xx/counter/74163.dig rename to src/main/dig/lib/DIL Chips/74xx/counter/74163.dig diff --git a/src/main/dig/lib/74xx/counter/74191.dig b/src/main/dig/lib/DIL Chips/74xx/counter/74191.dig similarity index 100% rename from src/main/dig/lib/74xx/counter/74191.dig rename to src/main/dig/lib/DIL Chips/74xx/counter/74191.dig diff --git a/src/main/dig/lib/74xx/counter/74590.dig b/src/main/dig/lib/DIL Chips/74xx/counter/74590.dig similarity index 100% rename from src/main/dig/lib/74xx/counter/74590.dig rename to src/main/dig/lib/DIL Chips/74xx/counter/74590.dig diff --git a/src/main/dig/lib/74xx/counter/74779-inc.dig b/src/main/dig/lib/DIL Chips/74xx/counter/74779-inc.dig similarity index 100% rename from src/main/dig/lib/74xx/counter/74779-inc.dig rename to src/main/dig/lib/DIL Chips/74xx/counter/74779-inc.dig diff --git a/src/main/dig/lib/74xx/counter/74779.dig b/src/main/dig/lib/DIL Chips/74xx/counter/74779.dig similarity index 100% rename from src/main/dig/lib/74xx/counter/74779.dig rename to src/main/dig/lib/DIL Chips/74xx/counter/74779.dig diff --git a/src/main/dig/lib/74xx/display/7447.dig b/src/main/dig/lib/DIL Chips/74xx/display/7447.dig similarity index 100% rename from src/main/dig/lib/74xx/display/7447.dig rename to src/main/dig/lib/DIL Chips/74xx/display/7447.dig diff --git a/src/main/dig/lib/74xx/display/7448.dig b/src/main/dig/lib/DIL Chips/74xx/display/7448.dig similarity index 100% rename from src/main/dig/lib/74xx/display/7448.dig rename to src/main/dig/lib/DIL Chips/74xx/display/7448.dig diff --git a/src/main/dig/lib/74xx/driver/7406.dig b/src/main/dig/lib/DIL Chips/74xx/driver/7406.dig similarity index 100% rename from src/main/dig/lib/74xx/driver/7406.dig rename to src/main/dig/lib/DIL Chips/74xx/driver/7406.dig diff --git a/src/main/dig/lib/74xx/driver/7407.dig b/src/main/dig/lib/DIL Chips/74xx/driver/7407.dig similarity index 100% rename from src/main/dig/lib/74xx/driver/7407.dig rename to src/main/dig/lib/DIL Chips/74xx/driver/7407.dig diff --git a/src/main/dig/lib/74xx/driver/7416.dig b/src/main/dig/lib/DIL Chips/74xx/driver/7416.dig similarity index 100% rename from src/main/dig/lib/74xx/driver/7416.dig rename to src/main/dig/lib/DIL Chips/74xx/driver/7416.dig diff --git a/src/main/dig/lib/74xx/driver/7417.dig b/src/main/dig/lib/DIL Chips/74xx/driver/7417.dig similarity index 100% rename from src/main/dig/lib/74xx/driver/7417.dig rename to src/main/dig/lib/DIL Chips/74xx/driver/7417.dig diff --git a/src/main/dig/lib/74xx/driver/74244.dig b/src/main/dig/lib/DIL Chips/74xx/driver/74244.dig similarity index 100% rename from src/main/dig/lib/74xx/driver/74244.dig rename to src/main/dig/lib/DIL Chips/74xx/driver/74244.dig diff --git a/src/main/dig/lib/74xx/driver/74245.dig b/src/main/dig/lib/DIL Chips/74xx/driver/74245.dig similarity index 100% rename from src/main/dig/lib/74xx/driver/74245.dig rename to src/main/dig/lib/DIL Chips/74xx/driver/74245.dig diff --git a/src/main/dig/lib/74xx/driver/74540.dig b/src/main/dig/lib/DIL Chips/74xx/driver/74540.dig similarity index 100% rename from src/main/dig/lib/74xx/driver/74540.dig rename to src/main/dig/lib/DIL Chips/74xx/driver/74540.dig diff --git a/src/main/dig/lib/74xx/driver/74541.dig b/src/main/dig/lib/DIL Chips/74xx/driver/74541.dig similarity index 100% rename from src/main/dig/lib/74xx/driver/74541.dig rename to src/main/dig/lib/DIL Chips/74xx/driver/74541.dig diff --git a/src/main/dig/lib/74xx/flipflops/74107.dig b/src/main/dig/lib/DIL Chips/74xx/flipflops/74107.dig similarity index 100% rename from src/main/dig/lib/74xx/flipflops/74107.dig rename to src/main/dig/lib/DIL Chips/74xx/flipflops/74107.dig diff --git a/src/main/dig/lib/74xx/flipflops/74109.dig b/src/main/dig/lib/DIL Chips/74xx/flipflops/74109.dig similarity index 100% rename from src/main/dig/lib/74xx/flipflops/74109.dig rename to src/main/dig/lib/DIL Chips/74xx/flipflops/74109.dig diff --git a/src/main/dig/lib/74xx/flipflops/74112.dig b/src/main/dig/lib/DIL Chips/74xx/flipflops/74112.dig similarity index 100% rename from src/main/dig/lib/74xx/flipflops/74112.dig rename to src/main/dig/lib/DIL Chips/74xx/flipflops/74112.dig diff --git a/src/main/dig/lib/74xx/flipflops/74116.dig b/src/main/dig/lib/DIL Chips/74xx/flipflops/74116.dig similarity index 100% rename from src/main/dig/lib/74xx/flipflops/74116.dig rename to src/main/dig/lib/DIL Chips/74xx/flipflops/74116.dig diff --git a/src/main/dig/lib/74xx/flipflops/74173.dig b/src/main/dig/lib/DIL Chips/74xx/flipflops/74173.dig similarity index 100% rename from src/main/dig/lib/74xx/flipflops/74173.dig rename to src/main/dig/lib/DIL Chips/74xx/flipflops/74173.dig diff --git a/src/main/dig/lib/74xx/flipflops/74174.dig b/src/main/dig/lib/DIL Chips/74xx/flipflops/74174.dig similarity index 100% rename from src/main/dig/lib/74xx/flipflops/74174.dig rename to src/main/dig/lib/DIL Chips/74xx/flipflops/74174.dig diff --git a/src/main/dig/lib/74xx/flipflops/74273.dig b/src/main/dig/lib/DIL Chips/74xx/flipflops/74273.dig similarity index 100% rename from src/main/dig/lib/74xx/flipflops/74273.dig rename to src/main/dig/lib/DIL Chips/74xx/flipflops/74273.dig diff --git a/src/main/dig/lib/74xx/flipflops/74373-D-inc.dig b/src/main/dig/lib/DIL Chips/74xx/flipflops/74373-D-inc.dig similarity index 100% rename from src/main/dig/lib/74xx/flipflops/74373-D-inc.dig rename to src/main/dig/lib/DIL Chips/74xx/flipflops/74373-D-inc.dig diff --git a/src/main/dig/lib/74xx/flipflops/74373.dig b/src/main/dig/lib/DIL Chips/74xx/flipflops/74373.dig similarity index 100% rename from src/main/dig/lib/74xx/flipflops/74373.dig rename to src/main/dig/lib/DIL Chips/74xx/flipflops/74373.dig diff --git a/src/main/dig/lib/74xx/flipflops/74374.dig b/src/main/dig/lib/DIL Chips/74xx/flipflops/74374.dig similarity index 100% rename from src/main/dig/lib/74xx/flipflops/74374.dig rename to src/main/dig/lib/DIL Chips/74xx/flipflops/74374.dig diff --git a/src/main/dig/lib/74xx/flipflops/7474.dig b/src/main/dig/lib/DIL Chips/74xx/flipflops/7474.dig similarity index 100% rename from src/main/dig/lib/74xx/flipflops/7474.dig rename to src/main/dig/lib/DIL Chips/74xx/flipflops/7474.dig diff --git a/src/main/dig/lib/74xx/flipflops/7476.dig b/src/main/dig/lib/DIL Chips/74xx/flipflops/7476.dig similarity index 100% rename from src/main/dig/lib/74xx/flipflops/7476.dig rename to src/main/dig/lib/DIL Chips/74xx/flipflops/7476.dig diff --git a/src/main/dig/lib/74xx/memory/74189.dig b/src/main/dig/lib/DIL Chips/74xx/memory/74189.dig similarity index 100% rename from src/main/dig/lib/74xx/memory/74189.dig rename to src/main/dig/lib/DIL Chips/74xx/memory/74189.dig diff --git a/src/main/dig/lib/74xx/memory/74670-D-inc.dig b/src/main/dig/lib/DIL Chips/74xx/memory/74670-D-inc.dig similarity index 100% rename from src/main/dig/lib/74xx/memory/74670-D-inc.dig rename to src/main/dig/lib/DIL Chips/74xx/memory/74670-D-inc.dig diff --git a/src/main/dig/lib/74xx/memory/74670.dig b/src/main/dig/lib/DIL Chips/74xx/memory/74670.dig similarity index 100% rename from src/main/dig/lib/74xx/memory/74670.dig rename to src/main/dig/lib/DIL Chips/74xx/memory/74670.dig diff --git a/src/main/dig/lib/74xx/memory/7489.dig b/src/main/dig/lib/DIL Chips/74xx/memory/7489.dig similarity index 100% rename from src/main/dig/lib/74xx/memory/7489.dig rename to src/main/dig/lib/DIL Chips/74xx/memory/7489.dig diff --git a/src/main/dig/lib/74xx/plexers/74138.dig b/src/main/dig/lib/DIL Chips/74xx/plexers/74138.dig similarity index 100% rename from src/main/dig/lib/74xx/plexers/74138.dig rename to src/main/dig/lib/DIL Chips/74xx/plexers/74138.dig diff --git a/src/main/dig/lib/74xx/plexers/74139.dig b/src/main/dig/lib/DIL Chips/74xx/plexers/74139.dig similarity index 100% rename from src/main/dig/lib/74xx/plexers/74139.dig rename to src/main/dig/lib/DIL Chips/74xx/plexers/74139.dig diff --git a/src/main/dig/lib/74xx/plexers/74150.dig b/src/main/dig/lib/DIL Chips/74xx/plexers/74150.dig similarity index 100% rename from src/main/dig/lib/74xx/plexers/74150.dig rename to src/main/dig/lib/DIL Chips/74xx/plexers/74150.dig diff --git a/src/main/dig/lib/74xx/plexers/74151.dig b/src/main/dig/lib/DIL Chips/74xx/plexers/74151.dig similarity index 100% rename from src/main/dig/lib/74xx/plexers/74151.dig rename to src/main/dig/lib/DIL Chips/74xx/plexers/74151.dig diff --git a/src/main/dig/lib/74xx/plexers/74153.dig b/src/main/dig/lib/DIL Chips/74xx/plexers/74153.dig similarity index 100% rename from src/main/dig/lib/74xx/plexers/74153.dig rename to src/main/dig/lib/DIL Chips/74xx/plexers/74153.dig diff --git a/src/main/dig/lib/74xx/plexers/74154.dig b/src/main/dig/lib/DIL Chips/74xx/plexers/74154.dig similarity index 100% rename from src/main/dig/lib/74xx/plexers/74154.dig rename to src/main/dig/lib/DIL Chips/74xx/plexers/74154.dig diff --git a/src/main/dig/lib/74xx/plexers/74157.dig b/src/main/dig/lib/DIL Chips/74xx/plexers/74157.dig similarity index 100% rename from src/main/dig/lib/74xx/plexers/74157.dig rename to src/main/dig/lib/DIL Chips/74xx/plexers/74157.dig diff --git a/src/main/dig/lib/74xx/plexers/74238.dig b/src/main/dig/lib/DIL Chips/74xx/plexers/74238.dig similarity index 100% rename from src/main/dig/lib/74xx/plexers/74238.dig rename to src/main/dig/lib/DIL Chips/74xx/plexers/74238.dig diff --git a/src/main/dig/lib/74xx/plexers/74253.dig b/src/main/dig/lib/DIL Chips/74xx/plexers/74253.dig similarity index 100% rename from src/main/dig/lib/74xx/plexers/74253.dig rename to src/main/dig/lib/DIL Chips/74xx/plexers/74253.dig diff --git a/src/main/dig/lib/74xx/plexers/7442.dig b/src/main/dig/lib/DIL Chips/74xx/plexers/7442.dig similarity index 100% rename from src/main/dig/lib/74xx/plexers/7442.dig rename to src/main/dig/lib/DIL Chips/74xx/plexers/7442.dig diff --git a/src/main/dig/lib/74xx/shift register/74164.dig b/src/main/dig/lib/DIL Chips/74xx/shift register/74164.dig similarity index 100% rename from src/main/dig/lib/74xx/shift register/74164.dig rename to src/main/dig/lib/DIL Chips/74xx/shift register/74164.dig diff --git a/src/main/dig/lib/74xx/shift register/74165.dig b/src/main/dig/lib/DIL Chips/74xx/shift register/74165.dig similarity index 100% rename from src/main/dig/lib/74xx/shift register/74165.dig rename to src/main/dig/lib/DIL Chips/74xx/shift register/74165.dig diff --git a/src/main/dig/lib/74xx/shift register/74166.dig b/src/main/dig/lib/DIL Chips/74xx/shift register/74166.dig similarity index 100% rename from src/main/dig/lib/74xx/shift register/74166.dig rename to src/main/dig/lib/DIL Chips/74xx/shift register/74166.dig diff --git a/src/main/dig/lib/EPROMs/27c801.dig b/src/main/dig/lib/DIL Chips/EPROMs/27c801.dig similarity index 100% rename from src/main/dig/lib/EPROMs/27c801.dig rename to src/main/dig/lib/DIL Chips/EPROMs/27c801.dig diff --git a/src/main/dig/lib/EPROMs/28c010.dig b/src/main/dig/lib/DIL Chips/EPROMs/28c010.dig similarity index 100% rename from src/main/dig/lib/EPROMs/28c010.dig rename to src/main/dig/lib/DIL Chips/EPROMs/28c010.dig diff --git a/src/main/dig/lib/EPROMs/28c16.dig b/src/main/dig/lib/DIL Chips/EPROMs/28c16.dig similarity index 100% rename from src/main/dig/lib/EPROMs/28c16.dig rename to src/main/dig/lib/DIL Chips/EPROMs/28c16.dig diff --git a/src/main/dig/lib/EPROMs/28c256.dig b/src/main/dig/lib/DIL Chips/EPROMs/28c256.dig similarity index 100% rename from src/main/dig/lib/EPROMs/28c256.dig rename to src/main/dig/lib/DIL Chips/EPROMs/28c256.dig diff --git a/src/main/dig/lib/EPROMs/28c512.dig b/src/main/dig/lib/DIL Chips/EPROMs/28c512.dig similarity index 100% rename from src/main/dig/lib/EPROMs/28c512.dig rename to src/main/dig/lib/DIL Chips/EPROMs/28c512.dig diff --git a/src/main/dig/lib/EPROMs/28c64.dig b/src/main/dig/lib/DIL Chips/EPROMs/28c64.dig similarity index 100% rename from src/main/dig/lib/EPROMs/28c64.dig rename to src/main/dig/lib/DIL Chips/EPROMs/28c64.dig diff --git a/src/main/dig/lib/RAMs/A623308A.dig b/src/main/dig/lib/DIL Chips/RAMs/A623308A.dig similarity index 100% rename from src/main/dig/lib/RAMs/A623308A.dig rename to src/main/dig/lib/DIL Chips/RAMs/A623308A.dig diff --git a/src/main/dig/lib/RAMs/RAM32Bit.dig b/src/main/dig/lib/RAMs/RAM32Bit.dig new file mode 100644 index 000000000..bca04268a --- /dev/null +++ b/src/main/dig/lib/RAMs/RAM32Bit.dig @@ -0,0 +1,1407 @@ + + + 1 + + + Description + A 32-bit memory that allows byte access and can handle non-aligned +memory addresses. +{{de Ein 32-Bit-Speicher, der Bytezugriff ermöglicht und auch mit nicht +ausgerichteten Speicheradressen umgehen kann.}} + + + isGeneric + true + + + lockedMode + true + + + Width + 4 + + + + + In + + + Description + The address to use. +{{de Die Adresse}} + + + Label + A + + + Bits + 32 + + + generic + if (args.addrBits<3) { + panic("at least 3 bits are required!"); +} + +this.Bits=int(args.addrBits); + + + + + + In + + + Description + The data to store. +{{de Die zu speichernden Daten}} + + + Label + D_in + + + Bits + 32 + + + + + + Out + + + Description + The data output. +{{de Der Datenausgang}} + + + Label + D_out + + + Bits + 32 + + + + + + In + + + Description + write enable +{{de Schreiben einschalten}} + + + Label + we + + + InDefault + + + + + + + Splitter + + + Input Splitting + 32 + + + Output Splitting + 2-17,0-0,1-1,0-1 + + + generic + this.'Input Splitting'=""+args.addrBits; +this.'Output Splitting'="2-"+(args.addrBits-1)+",0-0,1-1,0-1"; + + + + + + RAMDualPort + + + AddrBits + 16 + + + Label + R0 + + + Bits + 8 + + + generic + this.AddrBits=int(args.addrBits-2); + + + + + + RAMDualPort + + + AddrBits + 16 + + + Label + R1 + + + Bits + 8 + + + generic + this.AddrBits=int(args.addrBits-2); + + + + + + RAMDualPort + + + AddrBits + 16 + + + Label + R2 + + + Bits + 8 + + + generic + this.AddrBits=int(args.addrBits-2); + + + + + + RAMDualPort + + + AddrBits + 16 + + + Label + R3 + + + Bits + 8 + + + generic + this.AddrBits=int(args.addrBits-2); + + + + + + Tunnel + + + NetName + A_0 + + + + + + Tunnel + + + NetName + A_1 + + + + + + Multiplexer + + + Bits + 16 + + + generic + this.Bits=int(args.addrBits-2); + + + + + + Multiplexer + + + Bits + 16 + + + generic + this.Bits=int(args.addrBits-2); + + + + + + Multiplexer + + + Bits + 16 + + + generic + this.Bits=int(args.addrBits-2); + + + + + + Add + + + Bits + 16 + + + generic + this.Bits=int(args.addrBits-2); + + + + + + Const + + + Bits + 16 + + + generic + this.Bits=int(args.addrBits-2); + + + + + + Ground + + + + + Tunnel + + + rotation + + + + NetName + A_0 + + + + + + Tunnel + + + rotation + + + + NetName + A_1 + + + + + + Or + + + + + Tunnel + + + rotation + + + + generic + this.Bits=int(args.addrBits-2); + + + NetName + A_1 + + + + + + Tunnel + + + rotation + + + + NetName + A_0 + + + + + + Tunnel + + + rotation + + + + NetName + A_1 + + + + + + And + + + + + Const + + + + + In + + + Description + The addressing mode. +0: word; +1: half word; +2: byte +{{de Der Adressierungsmodus +0: word; +1: half word; +2: byte +}} + + + Label + am + + + Bits + 2 + + + + + + Tunnel + + + NetName + A_01 + + + + + + Tunnel + + + rotation + + + + NetName + A_01 + + + + + + Tunnel + + + NetName + C + + + + + + Tunnel + + + rotation + + + + NetName + C + + + + + + Tunnel + + + rotation + + + + NetName + C + + + + + + Tunnel + + + rotation + + + + NetName + C + + + + + + Tunnel + + + rotation + + + + NetName + C + + + + + + Const + + + + + Const + + + + + Const + + + + + Multiplexer + + + Selector Bits + 2 + + + Bits + 32 + + + + + + Const + + + Value + 0 + + + Bits + 32 + + + + + + In + + + Description + if set, half words and bytes preserve sign. +{{de Wenn gesetzt erhällt das Lesen von half words und bytes das Vorzeichen.}} + + + rotation + + + + Label + signed + + + + + + Testcase + + + Label + read + + + Testdata + + A D_in C am signed D_out + +# 32 bit read +4 0x44332211 c 0 0 x +4 0 0 0 0 0x44332211 +3 0 0 0 0 0x33221100 +2 0 0 0 0 0x22110000 +1 0 0 0 0 0x11000000 +5 0 0 0 0 0x00443322 +6 0 0 0 0 0x00004433 +7 0 0 0 0 0x00000044 + +# 16 bit read unsigned +4 0x83828180 c 0 0 x +4 0 0 1 0 0x8180 +3 0 0 1 0 0x8000 +2 0 0 1 0 0x0000 +5 0 0 1 0 0x8281 +6 0 0 1 0 0x8382 +7 0 0 1 0 0x0083 + +# 16 bit read signed +4 0 0 1 1 0xffff8180 +3 0 0 1 1 0xffff8000 +2 0 0 1 1 0x00000000 +5 0 0 1 1 0xffff8281 +6 0 0 1 1 0xffff8382 +7 0 0 1 1 0x00000083 + +# 8 bit read +4 0 0 2 0 0x80 +3 0 0 2 0 0x00 +2 0 0 2 0 0x00 +5 0 0 2 0 0x81 +6 0 0 2 0 0x82 +7 0 0 2 0 0x83 + +# 8 bit read signed +4 0 0 2 1 0xffffff80 +3 0 0 2 1 0x00 +2 0 0 2 1 0x00 +5 0 0 2 1 0xffffff81 +6 0 0 2 1 0xffffff82 +7 0 0 2 1 0xffffff83 + + + + + + + + Testcase + + + Label + write + + + Testdata + + A D_in C am signed D_out + +# 32 bit write +0 0 c 0 0 x +4 0 c 0 0 x +1 0x44332211 c 0 0 x +0 0 0 0 0 0x33221100 +4 0 0 0 0 0x00000044 + +0 0 c 0 0 x +4 0 c 0 0 x +2 0x44332211 c 0 0 x +0 0 0 0 0 0x22110000 +4 0 0 0 0 0x00004433 + +0 0 c 0 0 x +4 0 c 0 0 x +3 0x44332211 c 0 0 x +0 0 0 0 0 0x11000000 +4 0 0 0 0 0x00443322 + +# 16 bit write +0 0 c 0 0 x +4 0 c 0 0 x +0 0x2211 c 1 0 x +0 0 0 0 0 0x00002211 +1 0x3320 c 1 0 x +0 0 0 0 0 0x00332011 +2 0x4430 c 1 0 x +0 0 0 0 0 0x44302011 +3 0x5540 c 1 0 x +0 0 0 0 0 0x40302011 +4 0 0 0 0 0x00000055 + +# 0 bit write +0 0 c 0 0 x +4 0 c 0 0 x +0 0x11 c 2 0 x +0 0 0 0 0 0x00000011 +1 0x22 c 2 0 x +0 0 0 0 0 0x00002211 +2 0x33 c 2 0 x +0 0 0 0 0 0x00332211 +3 0x44 c 2 0 x +0 0 0 0 0 0x44332211 + + + + + + + + Tunnel + + + rotation + + + + NetName + A_01 + + + + + + Tunnel + + + rotation + + + + NetName + A_01 + + + + + + Tunnel + + + NetName + addr + + + + + + Tunnel + + + rotation + + + + NetName + addr + + + + + + Tunnel + + + rotation + + + + NetName + addr + + + + + + Tunnel + + + rotation + + + + NetName + addr + + + + + + Tunnel + + + rotation + + + + NetName + addr + + + + + + Tunnel + + + NetName + addr+1 + + + + + + Tunnel + + + rotation + + + + NetName + addr+1 + + + + + + Tunnel + + + rotation + + + + NetName + addr+1 + + + + + + Tunnel + + + rotation + + + + NetName + addr+1 + + + + + + Tunnel + + + NetName + D_0 + + + + + + Tunnel + + + NetName + D_1 + + + + + + Tunnel + + + NetName + D_2 + + + + + + Tunnel + + + NetName + D_3 + + + + + + Tunnel + + + rotation + + + + NetName + D_0 + + + + + + Tunnel + + + rotation + + + + NetName + D_1 + + + + + + Tunnel + + + rotation + + + + NetName + D_2 + + + + + + Tunnel + + + rotation + + + + NetName + D_3 + + + + + + Tunnel + + + NetName + str_0 + + + + + + Tunnel + + + NetName + str_1 + + + + + + Tunnel + + + NetName + str_2 + + + + + + Tunnel + + + NetName + str_3 + + + + + + Tunnel + + + rotation + + + + NetName + str_0 + + + + + + Tunnel + + + rotation + + + + NetName + str_1 + + + + + + Tunnel + + + rotation + + + + NetName + str_2 + + + + + + Tunnel + + + rotation + + + + NetName + str_3 + + + + + + outDataGen-inc.dig + + + + + strDataGen-inc.dig + + + + + strGen-inc.dig + + + + + Clock + + + Label + C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/main/dig/lib/RAMs/outDataGen-inc.dig b/src/main/dig/lib/RAMs/outDataGen-inc.dig new file mode 100644 index 000000000..824703558 --- /dev/null +++ b/src/main/dig/lib/RAMs/outDataGen-inc.dig @@ -0,0 +1,678 @@ + + + 1 + + + Description + Rotates the output bytes to the right order. +{{de rotiert die Ausgabebytes in die richtige Reihenfolge.}} + + + lockedMode + true + + + Width + 4 + + + + + In + + + rotation + + + + Label + in_0 + + + Bits + 8 + + + intFormat + bin + + + + + + In + + + rotation + + + + Label + in_1 + + + Bits + 8 + + + intFormat + bin + + + + + + Multiplexer + + + Selector Bits + 2 + + + Bits + 32 + + + + + + Splitter + + + Input Splitting + 8*4 + + + Output Splitting + 32 + + + + + + Splitter + + + Input Splitting + 8*4 + + + Output Splitting + 32 + + + + + + Splitter + + + Input Splitting + 8*4 + + + Output Splitting + 32 + + + + + + Splitter + + + splitterSpreading + 5 + + + Input Splitting + 32 + + + Output Splitting + 0-15,0-7 + + + + + + Splitter + + + Input Splitting + 16,16 + + + Output Splitting + 32 + + + + + + Const + + + Value + 0 + + + Bits + 16 + + + + + + Splitter + + + Input Splitting + 8,24 + + + Output Splitting + 32 + + + + + + Const + + + Value + 0 + + + Bits + 24 + + + + + + Multiplexer + + + Bits + 32 + + + flipSelPos + true + + + + + + BitExtender + + + inputBits + 16 + + + outputBits + 32 + + + + + + Multiplexer + + + Bits + 32 + + + flipSelPos + true + + + + + + BitExtender + + + outputBits + 32 + + + + + + Out + + + Label + D_32 + + + Bits + 32 + + + + + + Out + + + Label + D_16 + + + Bits + 32 + + + + + + Out + + + Label + D_8 + + + Bits + 32 + + + + + + In + + + rotation + + + + Label + in_2 + + + Bits + 8 + + + intFormat + bin + + + + + + In + + + rotation + + + + Label + in_3 + + + Bits + 8 + + + intFormat + bin + + + + + + In + + + rotation + + + + Label + sh + + + Bits + 2 + + + + + + In + + + Description + signed output + + + Label + sign + + + + + + Splitter + + + Input Splitting + 8*4 + + + Output Splitting + 32 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/main/dig/lib/RAMs/strDataGen-inc.dig b/src/main/dig/lib/RAMs/strDataGen-inc.dig new file mode 100644 index 000000000..8f10b58c6 --- /dev/null +++ b/src/main/dig/lib/RAMs/strDataGen-inc.dig @@ -0,0 +1,404 @@ + + + 1 + + + Description + Rotates the bytes to match the correct ram components. +{{de Rotiert die Bytes um die richtigen RAM bausteine zu beschreiben.}} + + + lockedMode + true + + + + + In + + + Label + in + + + Bits + 32 + + + intFormat + bin + + + + + + In + + + rotation + + + + Label + sh + + + Bits + 2 + + + + + + Out + + + Label + D_0 + + + Bits + 8 + + + intFormat + bin + + + + + + Multiplexer + + + Selector Bits + 2 + + + Bits + 32 + + + + + + Splitter + + + rotation + + + + Input Splitting + 32 + + + Output Splitting + 8*4 + + + + + + Splitter + + + Input Splitting + 8*4 + + + Output Splitting + 32 + + + + + + Splitter + + + Input Splitting + 8*4 + + + Output Splitting + 32 + + + + + + Splitter + + + Input Splitting + 8*4 + + + Output Splitting + 32 + + + + + + Splitter + + + splitterSpreading + 2 + + + Input Splitting + 32 + + + Output Splitting + 8*4 + + + + + + Out + + + Label + D_1 + + + Bits + 8 + + + intFormat + bin + + + + + + Out + + + Label + D_2 + + + Bits + 8 + + + intFormat + bin + + + + + + Out + + + Label + D_3 + + + Bits + 8 + + + intFormat + bin + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/main/dig/lib/RAMs/strGen-inc.dig b/src/main/dig/lib/RAMs/strGen-inc.dig new file mode 100644 index 000000000..f45d4d554 --- /dev/null +++ b/src/main/dig/lib/RAMs/strGen-inc.dig @@ -0,0 +1,544 @@ + + + 1 + + + Description + Creates the four store enable signals. +{{de Erzeugt die vier Speicherfreigaben für die RAMs.}} + + + lockedMode + true + + + Width + 4 + + + + + In + + + rotation + + + + Label + sh + + + Bits + 2 + + + + + + In + + + rotation + + + + Label + we + + + + + + Out + + + Label + str_0 + + + intFormat + bin + + + + + + Multiplexer + + + Selector Bits + 2 + + + Bits + 4 + + + + + + Splitter + + + rotation + + + + Input Splitting + 4 + + + Output Splitting + 1*4 + + + + + + Splitter + + + Input Splitting + 1*4 + + + Output Splitting + 4 + + + + + + Splitter + + + Input Splitting + 1*4 + + + Output Splitting + 4 + + + + + + Splitter + + + Input Splitting + 1*4 + + + Output Splitting + 4 + + + + + + Splitter + + + splitterSpreading + 2 + + + Input Splitting + 4 + + + Output Splitting + 1*4 + + + + + + Out + + + Label + str_1 + + + intFormat + bin + + + + + + Out + + + Label + str_2 + + + intFormat + bin + + + + + + Out + + + Label + str_3 + + + intFormat + bin + + + + + + Multiplexer + + + Selector Bits + 2 + + + Bits + 4 + + + + + + Const + + + Value + 15 + + + Bits + 4 + + + intFormat + bin + + + + + + Const + + + Bits + 4 + + + intFormat + bin + + + + + + Const + + + Value + 3 + + + Bits + 4 + + + intFormat + bin + + + + + + Const + + + Value + 0 + + + Bits + 4 + + + + + + Multiplexer + + + Bits + 4 + + + + + + Ground + + + Bits + 4 + + + + + + In + + + Label + am + + + Bits + 2 + + + intFormat + bin + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/test/java/de/neemann/digital/hdl/verilog2/VerilogSimulatorTest.java b/src/test/java/de/neemann/digital/hdl/verilog2/VerilogSimulatorTest.java index 687de998e..999e90a2b 100644 --- a/src/test/java/de/neemann/digital/hdl/verilog2/VerilogSimulatorTest.java +++ b/src/test/java/de/neemann/digital/hdl/verilog2/VerilogSimulatorTest.java @@ -54,8 +54,8 @@ public class VerilogSimulatorTest extends TestCase { File examples = new File(Resources.getRoot(), "/dig/test/vhdl"); try { int tested = new FileScanner(this::checkVerilogExport).noOutput().scan(examples); - assertEquals(56, tested); - assertEquals(49, testBenches); + assertEquals(57, tested); + assertEquals(51, testBenches); } catch (FileScanner.SkipAllException e) { // if iverilog is not installed its also ok } diff --git a/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLSimulatorTest.java b/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLSimulatorTest.java index 5315c6c75..eba86287d 100644 --- a/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLSimulatorTest.java +++ b/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLSimulatorTest.java @@ -14,7 +14,6 @@ import de.neemann.digital.draw.library.ElementNotFoundException; import de.neemann.digital.gui.Settings; import de.neemann.digital.hdl.model2.HDLException; import de.neemann.digital.hdl.printer.CodePrinter; -import de.neemann.digital.hdl.printer.CodePrinterStr; import de.neemann.digital.integration.FileScanner; import de.neemann.digital.integration.Resources; import de.neemann.digital.integration.TestExamples; @@ -47,8 +46,8 @@ public class VHDLSimulatorTest extends TestCase { File examples = new File(Resources.getRoot(), "/dig/test/vhdl"); try { int tested = new FileScanner(this::checkVHDLExport).noOutput().scan(examples); - assertEquals(56, tested); - assertEquals(49, testBenches); + assertEquals(57, tested); + assertEquals(51, testBenches); } catch (FileScanner.SkipAllException e) { // if ghdl is not installed its also ok } @@ -141,14 +140,14 @@ public class VHDLSimulatorTest extends TestCase { } private void runGHDL(File vhdlFile, ArrayList testFileWritten) throws IOException, FileScanner.SkipAllException, HDLException { - checkWarn(vhdlFile, startProcess(vhdlFile.getParentFile(), GHDL, "-a", "--ieee=synopsys", vhdlFile.getName())); - checkWarn(vhdlFile, startProcess(vhdlFile.getParentFile(), GHDL, "-e", "--ieee=synopsys", "main")); + checkWarn(vhdlFile, startProcess(vhdlFile.getParentFile(), GHDL, "-a", "--std=08", "--ieee=synopsys", vhdlFile.getName())); + checkWarn(vhdlFile, startProcess(vhdlFile.getParentFile(), GHDL, "-e", "--std=08", "--ieee=synopsys", "main")); for (File testbench : testFileWritten) { String name = testbench.getName(); - checkWarn(testbench, startProcess(vhdlFile.getParentFile(), GHDL, "-a", "--ieee=synopsys", name)); + checkWarn(testbench, startProcess(vhdlFile.getParentFile(), GHDL, "-a", "--std=08", "--ieee=synopsys", name)); String module = name.substring(0, name.length() - 5); - checkWarn(testbench, startProcess(vhdlFile.getParentFile(), GHDL, "-e", "--ieee=synopsys", module)); - String result = startProcess(vhdlFile.getParentFile(), GHDL, "-r", "--ieee=synopsys", module, "--vcd=" + module + ".vcd"); + checkWarn(testbench, startProcess(vhdlFile.getParentFile(), GHDL, "-e", "--std=08", "--ieee=synopsys", module)); + String result = startProcess(vhdlFile.getParentFile(), GHDL, "-r", "--std=08", "--ieee=synopsys", module, "--vcd=" + module + ".vcd"); if (result.contains("(assertion error)")) throw new HDLException("test bench " + name + " failed:\n" + result); checkWarn(testbench, result); diff --git a/src/test/java/de/neemann/digital/integration/TestExamples.java b/src/test/java/de/neemann/digital/integration/TestExamples.java index 3e6347d47..61aa376a0 100644 --- a/src/test/java/de/neemann/digital/integration/TestExamples.java +++ b/src/test/java/de/neemann/digital/integration/TestExamples.java @@ -32,8 +32,8 @@ public class TestExamples extends TestCase { */ public void testDistExamples() throws Exception { File examples = new File(Resources.getRoot().getParentFile().getParentFile(), "/main/dig"); - assertEquals(265, new FileScanner(this::check).scan(examples)); - assertEquals(181, testCasesInFiles); + assertEquals(269, new FileScanner(this::check).scan(examples)); + assertEquals(184, testCasesInFiles); } /** @@ -43,8 +43,8 @@ public class TestExamples extends TestCase { */ public void testTestExamples() throws Exception { File examples = new File(Resources.getRoot(), "/dig/test"); - assertEquals(181, new FileScanner(this::check).scan(examples)); - assertEquals(168, testCasesInFiles); + assertEquals(182, new FileScanner(this::check).scan(examples)); + assertEquals(170, testCasesInFiles); } /** diff --git a/src/test/java/de/neemann/digital/integration/TestLib.java b/src/test/java/de/neemann/digital/integration/TestLib.java index 67e6d07ff..d1d10c3a9 100644 --- a/src/test/java/de/neemann/digital/integration/TestLib.java +++ b/src/test/java/de/neemann/digital/integration/TestLib.java @@ -40,7 +40,7 @@ public class TestLib extends TestCase { private void check(File dig) throws PinException, NodeException, ElementNotFoundException, IOException { Circuit circuit = new ToBreakRunner(dig).getCircuit(); - boolean is74xx = !dig.getName().endsWith("-inc.dig"); + boolean is74xx = !dig.getName().endsWith("-inc.dig") && dig.getPath().contains("DIL Chips"); if (is74xx) { assertEquals("is not DIL", CustomCircuitShapeType.DIL, circuit.getAttributes().get(Keys.SHAPE_TYPE)); diff --git a/src/test/resources/dig/test/vhdl/generics/Ram32BitTest.dig b/src/test/resources/dig/test/vhdl/generics/Ram32BitTest.dig new file mode 100644 index 000000000..daff54f3a --- /dev/null +++ b/src/test/resources/dig/test/vhdl/generics/Ram32BitTest.dig @@ -0,0 +1,257 @@ + + + 1 + + + + Out + + + Label + D_out + + + Bits + 32 + + + + + + In + + + Label + A + + + Bits + 8 + + + + + + In + + + Label + D_in + + + Bits + 32 + + + + + + In + + + Label + we + + + + + + In + + + Label + am + + + Bits + 2 + + + + + + In + + + Label + signed + + + + + + Clock + + + Label + C + + + + + + Testcase + + + Label + read + + + Testdata + + A we D_in C am signed D_out + +# 32 bit read +0 1 0x0 c 0 0 x +4 1 0x44332211 c 0 0 x +8 1 0x0 c 0 0 x +4 0 0 0 0 0 0x44332211 +3 0 0 0 0 0 0x33221100 +2 0 0 0 0 0 0x22110000 +1 0 0 0 0 0 0x11000000 +5 0 0 0 0 0 0x00443322 +6 0 0 0 0 0 0x00004433 +7 0 0 0 0 0 0x00000044 + +# 16 bit read unsigned +4 1 0x83828180 c 0 0 x +4 0 0 0 1 0 0x8180 +3 0 0 0 1 0 0x8000 +2 0 0 0 1 0 0x0000 +5 0 0 0 1 0 0x8281 +6 0 0 0 1 0 0x8382 +7 0 0 0 1 0 0x0083 + +# 0 16 bit read signed +4 0 0 0 1 1 0xffff8180 +3 0 0 0 1 1 0xffff8000 +2 0 0 0 1 1 0x00000000 +5 0 0 0 1 1 0xffff8281 +6 0 0 0 1 1 0xffff8382 +7 0 0 0 1 1 0x00000083 + +# 8 bit read +4 0 0 0 2 0 0x80 +3 0 0 0 2 0 0x00 +2 0 0 0 2 0 0x00 +5 0 0 0 2 0 0x81 +6 0 0 0 2 0 0x82 +7 0 0 0 2 0 0x83 + +# 8 bit read signed +4 0 0 0 2 1 0xffffff80 +3 0 0 0 2 1 0x00 +2 0 0 0 2 1 0x00 +5 0 0 0 2 1 0xffffff81 +6 0 0 0 2 1 0xffffff82 +7 0 0 0 2 1 0xffffff83 + + + + + + + + Testcase + + + Label + write + + + Testdata + + A we D_in C am signed D_out + +# 32 bit write +0 1 0 c 0 0 x +4 1 0 c 0 0 x +1 1 0x44332211 c 0 0 x +0 0 0 0 0 0 0x33221100 +4 0 0 0 0 0 0x00000044 + +0 1 0 c 0 0 x +4 1 0 c 0 0 x +2 1 0x44332211 c 0 0 x +0 0 0 0 0 0 0x22110000 +4 0 0 0 0 0 0x00004433 + +0 1 0 c 0 0 x +4 1 0 c 0 0 x +3 1 0x44332211 c 0 0 x +0 0 0 0 0 0 0x11000000 +4 0 0 0 0 0 0x00443322 + +# 16 bit write +0 1 0 c 0 0 x +4 1 0 c 0 0 x +0 1 0x2211 c 1 0 x +0 0 0 0 0 0 0x00002211 +1 1 0x3320 c 1 0 x +0 0 0 0 0 0 0x00332011 +2 1 0x4430 c 1 0 x +0 0 0 0 0 0 0x44302011 +3 1 0x5540 c 1 0 x +0 0 0 0 0 0 0x40302011 +4 0 0 0 0 0 0x00000055 + +# 0 bit write +0 1 0 c 0 0 x +4 1 0 c 0 0 x +0 1 0x11 c 2 0 x +0 0 0 0 0 0 0x00000011 +1 1 0x22 c 2 0 x +0 0 0 0 0 0 0x00002211 +2 1 0x33 c 2 0 x +0 0 0 0 0 0 0x00332211 +3 1 0x44 c 2 0 x +0 0 0 0 0 0 0x44332211 + + + + + + + + RAM32Bit.dig + + + generic + addrBits := 8; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file