diff --git a/src/main/java/de/neemann/digital/hdl/model2/HDLCircuit.java b/src/main/java/de/neemann/digital/hdl/model2/HDLCircuit.java index 048808c13..e7b7dae9a 100644 --- a/src/main/java/de/neemann/digital/hdl/model2/HDLCircuit.java +++ b/src/main/java/de/neemann/digital/hdl/model2/HDLCircuit.java @@ -19,7 +19,6 @@ import de.neemann.digital.core.wiring.Clock; import de.neemann.digital.core.wiring.Splitter; import de.neemann.digital.draw.elements.*; import de.neemann.digital.draw.library.GenericInitCode; -import de.neemann.digital.draw.model.InverterConfig; import de.neemann.digital.draw.model.Net; import de.neemann.digital.draw.model.NetList; import de.neemann.digital.gui.components.data.DummyElement; @@ -147,18 +146,6 @@ public class HDLCircuit implements Iterable, HDLModel.BitProvider, Prin for (HDLNet n : listOfNets) n.checkPinControlUsage(); - // fix inverted inputs - ArrayList newNodes = new ArrayList<>(); - for (HDLNode n : nodes) { - InverterConfig iv = n.getElementAttributes().get(Keys.INVERTER_CONFIG); - if (!iv.isEmpty()) { - for (HDLPort p : n.getInputs()) - if (iv.contains(p.getName())) - newNodes.add(createNot(p, n)); - } - } - nodes.addAll(newNodes); - for (HDLPort i : inputs) if (i.getNet() != null) { i.getNet().setIsInput(i.getName()); @@ -206,23 +193,28 @@ public class HDLCircuit implements Iterable, HDLModel.BitProvider, Prin nodes.add(oneToMany); } - private HDLNode createNot(HDLPort p, HDLNode node) throws HDLException, NodeException, PinException { - final ElementAttributes attr = new ElementAttributes().setBits(p.getBits()); - HDLNodeAssignment n = new HDLNodeAssignment(Not.DESCRIPTION.getName(), attr, name -> p.getBits()); + HDLNet createNot(HDLNet inNet) throws HDLException, NodeException, PinException { + int bits = 1; + final ElementAttributes attr = new ElementAttributes().setBits(bits); + HDLNodeAssignment n = new HDLNodeAssignment(Not.DESCRIPTION.getName(), attr, name -> bits); HDLNet outNet = new HDLNet(null); listOfNets.add(outNet); - HDLNet inNet = p.getNet(); - inNet.remove(p); - n.addPort(new HDLPort(Not.DESCRIPTION.getInputDescription(attr).get(0).getName(), inNet, HDLPort.Direction.IN, p.getBits())); - n.addPort(new HDLPort(Not.DESCRIPTION.getOutputDescriptions(attr).get(0).getName(), outNet, HDLPort.Direction.OUT, p.getBits())); + HDLPort notOut = new HDLPort(Not.DESCRIPTION.getOutputDescriptions(attr).get(0).getName(), outNet, HDLPort.Direction.OUT, 0); + n.addPort(notOut); + n.addPort(new HDLPort(Not.DESCRIPTION.getInputDescription(attr).get(0).getName(), inNet, HDLPort.Direction.IN, 0) { + @Override + public void setBits(int bits) { + super.setBits(bits); + notOut.setBits(bits); + } + }); - p.setNet(outNet); - node.replaceNet(inNet, outNet); + n.setExpression(new ExprNot(new ExprVar(inNet))); - n.setExpression(new ExprNot(new ExprVar(n.getInputs().get(0).getNet()))); + nodes.add(n); - return n; + return outNet; } private void addOutput(HDLPort port) { diff --git a/src/main/java/de/neemann/digital/hdl/model2/HDLModel.java b/src/main/java/de/neemann/digital/hdl/model2/HDLModel.java index f87d1d701..a9cb21672 100644 --- a/src/main/java/de/neemann/digital/hdl/model2/HDLModel.java +++ b/src/main/java/de/neemann/digital/hdl/model2/HDLModel.java @@ -19,6 +19,7 @@ import de.neemann.digital.draw.library.ElementLibrary; import de.neemann.digital.draw.library.ElementNotFoundException; import de.neemann.digital.draw.library.ElementTypeDescriptionCustom; import de.neemann.digital.draw.library.ResolveGenerics; +import de.neemann.digital.draw.model.InverterConfig; import de.neemann.digital.hdl.model2.clock.HDLClockIntegrator; import de.neemann.digital.hdl.model2.expression.*; @@ -33,12 +34,12 @@ import static de.neemann.digital.draw.model.ModelCreator.fixGenerics; * Ensures that every circuit is only processed one time. */ public class HDLModel implements Iterable { - private ElementLibrary elementLibrary; - private HashMap circuitMap; + private final ElementLibrary elementLibrary; + private final HashMap circuitMap; + private final ResolveGenerics resolveGenerics = new ResolveGenerics(); + private final HashMap genericInstanceNumbers; private HDLCircuit main; private Renaming renaming; - private ResolveGenerics resolveGenerics = new ResolveGenerics(); - private HashMap genericInstanceNumbers; /** * Creates a new instance @@ -166,7 +167,7 @@ public class HDLModel implements Iterable { return new ExprOperate(op, list); } - private HDLNodeAssignment createExpression(VisualElement v, HDLCircuit parent, ElementTypeDescription td) throws HDLException, PinException { + private HDLNodeAssignment createExpression(VisualElement v, HDLCircuit parent, ElementTypeDescription td) throws HDLException, PinException, NodeException { return addInputsOutputs(new HDLNodeAssignment(v.getElementName(), v.getElementAttributes(), new ObservableValuesBitsProvider( @@ -174,11 +175,15 @@ public class HDLModel implements Iterable { v, parent); } - private N addInputsOutputs(N node, VisualElement v, HDLCircuit c) throws HDLException { + private N addInputsOutputs(N node, VisualElement v, HDLCircuit c) throws HDLException, NodeException, PinException { for (Pin p : v.getPins()) { HDLNet net = c.getNetOfPin(p); switch (p.getDirection()) { case input: + InverterConfig ic = v.getElementAttributes().get(Keys.INVERTER_CONFIG); + if (ic.contains(p.getName())) + net = c.createNot(net); + node.addPort(new HDLPort(p.getName(), net, HDLPort.Direction.IN, 0)); break; case output: diff --git a/src/test/java/de/neemann/digital/hdl/verilog2/VerilogSimulatorTest.java b/src/test/java/de/neemann/digital/hdl/verilog2/VerilogSimulatorTest.java index eaf5a5209..34345a17d 100644 --- a/src/test/java/de/neemann/digital/hdl/verilog2/VerilogSimulatorTest.java +++ b/src/test/java/de/neemann/digital/hdl/verilog2/VerilogSimulatorTest.java @@ -62,7 +62,7 @@ public class VerilogSimulatorTest extends TestCase { File examples = new File(Resources.getRoot(), "/dig/hdl"); try { int tested = new FileScanner(this::checkVerilogExport).noOutput().scan(examples); - assertEquals(48, tested); + assertEquals(51, tested); } catch (FileScanner.SkipAllException e) { // if iverilog is not installed its also ok } @@ -187,7 +187,7 @@ public class VerilogSimulatorTest extends TestCase { } private String getTime() { - DateFormat f = new SimpleDateFormat("YY-MM-dd_HH-mm_ss"); + DateFormat f = new SimpleDateFormat("yy-MM-dd_HH-mm_ss"); return f.format(new Date()); } diff --git a/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLSimulatorTest.java b/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLSimulatorTest.java index 360133913..67d84b901 100644 --- a/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLSimulatorTest.java +++ b/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLSimulatorTest.java @@ -54,7 +54,7 @@ public class VHDLSimulatorTest extends TestCase { File examples = new File(Resources.getRoot(), "/dig/hdl"); try { int tested = new FileScanner(this::checkVHDLExport).noOutput().scan(examples); - assertEquals(48, tested); + assertEquals(51, tested); } catch (FileScanner.SkipAllException e) { // if ghdl is not installed its also ok } @@ -179,7 +179,7 @@ public class VHDLSimulatorTest extends TestCase { } private String getTime() { - DateFormat f = new SimpleDateFormat("YY-MM-dd_HH-mm_ss"); + DateFormat f = new SimpleDateFormat("yy-MM-dd_HH-mm_ss"); return f.format(new Date()); } diff --git a/src/test/resources/dig/hdl/model2/inputInvert3.dig b/src/test/resources/dig/hdl/model2/inputInvert3.dig new file mode 100644 index 000000000..6f1e05c93 --- /dev/null +++ b/src/test/resources/dig/hdl/model2/inputInvert3.dig @@ -0,0 +1,98 @@ + + + 1 + + + + In + + + Label + D + + + + + + In + + + Label + C + + + + + + Out + + + Label + Y + + + + + + Testcase + + + Testdata + + C D Y +0 0 0 +1 0 1 +0 0 1 +1 0 1 +0 1 1 +1 1 0 + + + + + + + D_FF + + + inverterConfig + + D + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/test/resources/dig/hdl/model2/inputInvert4.dig b/src/test/resources/dig/hdl/model2/inputInvert4.dig new file mode 100644 index 000000000..c0b6d580f --- /dev/null +++ b/src/test/resources/dig/hdl/model2/inputInvert4.dig @@ -0,0 +1,112 @@ + + + 1 + + + + In + + + Label + D + + + Bits + 2 + + + + + + In + + + Label + C + + + + + + Out + + + Label + Y + + + Bits + 2 + + + + + + Testcase + + + Testdata + + C D Y +0 0 0 +1 0 3 +0 0 3 +1 0 3 +0 1 3 +1 1 2 +0 0 2 +1 0 3 + + + + + + + D_FF + + + Bits + 2 + + + inverterConfig + + D + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/test/resources/dig/hdl/model2/inputInvert5.dig b/src/test/resources/dig/hdl/model2/inputInvert5.dig new file mode 100644 index 000000000..4318a678c --- /dev/null +++ b/src/test/resources/dig/hdl/model2/inputInvert5.dig @@ -0,0 +1,136 @@ + + + 1 + + + + In + + + Label + D + + + + + + In + + + Label + C + + + + + + Out + + + Label + Q + + + + + + Testcase + + + Testdata + + C D Set Clr Q nQ +C 0 1 1 0 1 +C 1 1 1 1 0 +C 0 1 1 0 1 +0 0 1 1 0 1 +0 0 0 1 1 0 +0 0 1 1 1 0 +0 0 1 0 0 1 +0 0 1 1 0 1 + + + + + + + + D_FF_AS + + + inverterConfig + + Set + Clr + + + + + + + Out + + + Label + nQ + + + + + + In + + + Label + Set + + + + + + In + + + Label + Clr + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file