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converted most VHDLEntity classes to templates

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This commit is contained in:
hneemann 2018-03-14 21:21:23 +01:00
parent 656c0837b6
commit 49f8288b9c
32 changed files with 747 additions and 742 deletions
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51
src/main/java/de/neemann/digital/hdl/hgs/Parser.java
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@ -98,7 +98,10 @@ public class Parser {
return c -> ref.set(c, val.value(c));
} else if (isToken(ADD)) {
expect(ADD);
return c -> ref.set(c, Value.add(ref.get(c), 1));
return c -> ref.set(c, Value.toLong(ref.get(c)) + 1);
} else if (isToken(SUB)) {
expect(SUB);
return c -> ref.set(c, Value.toLong(ref.get(c)) - 1);
} else if (isToken(SEMICOLON)) {
return ref::get;
} else
@ -156,6 +159,14 @@ public class Parser {
inc.execute(c);
}
};
} else if (isToken(PANIC)) {
expect(OPEN);
Expression message = parseExpression();
expect(CLOSE);
expect(SEMICOLON);
return c -> {
throw new HGSEvalException(message.value(c).toString());
};
} else
throw newUnexpectedToken(tok.next());
}
@ -227,26 +238,52 @@ public class Parser {
* @throws IOException IOException
* @throws ParserException IOException
*/
public Expression parseExpression() throws IOException, ParserException {
Expression ac = parseGreater();
while (isToken(Tokenizer.Token.SMALER)) {
public Expression parseExp() throws IOException, ParserException {
Expression ex = parseExpression();
expect(EOF);
return ex;
}
private Expression parseExpression() throws IOException, ParserException {
Expression ac = parseLessEquals();
while (isToken(Tokenizer.Token.LESS)) {
Expression a = ac;
Expression b = parseGreater();
Expression b = parseLessEquals();
ac = c -> Value.toLong(a.value(c)) < Value.toLong(b.value(c));
}
return ac;
}
private Expression parseLessEquals() throws IOException, ParserException {
Expression ac = parseGreater();
while (isToken(Tokenizer.Token.LESSEQUAL)) {
Expression a = ac;
Expression b = parseGreater();
ac = c -> Value.toLong(a.value(c)) <= Value.toLong(b.value(c));
}
return ac;
}
private Expression parseGreater() throws IOException, ParserException {
Expression ac = parseEquals();
Expression ac = parseGreaterEquals();
while (isToken(Tokenizer.Token.GREATER)) {
Expression a = ac;
Expression b = parseEquals();
Expression b = parseGreaterEquals();
ac = c -> Value.toLong(a.value(c)) > Value.toLong(b.value(c));
}
return ac;
}
private Expression parseGreaterEquals() throws IOException, ParserException {
Expression ac = parseEquals();
while (isToken(Tokenizer.Token.GREATEREQUAL)) {
Expression a = ac;
Expression b = parseEquals();
ac = c -> Value.toLong(a.value(c)) >= Value.toLong(b.value(c));
}
return ac;
}
private Expression parseEquals() throws IOException, ParserException {
Expression ac = parseNotEquals();
while (isToken(Tokenizer.Token.EQUAL)) {

11
src/main/java/de/neemann/digital/hdl/hgs/Tokenizer.java
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@ -16,8 +16,8 @@ class Tokenizer {
enum Token {
UNKNOWN, IDENT, AND, OR, XOR, NOT, OPEN, CLOSE, NUMBER, EOL, EOF, SHIFTLEFT, SHIFTRIGHT, COMMA, EQUAL,
ADD, SUB, MUL, GREATER, SMALER, DIV, MOD, END, IF, ELSE, FOR, WHILE, SEMICOLON, NOTEQUAL, STRING,
OPENBRACE, CLOSEDBRACE, CODEEND, OPENSQUARE, CLOSEDSQUARE, DOT, PRINT, STATIC, FUNC, PRINTF
ADD, SUB, MUL, GREATER, LESS, DIV, MOD, END, IF, ELSE, FOR, WHILE, SEMICOLON, NOTEQUAL, STRING,
OPENBRACE, CLOSEDBRACE, CODEEND, OPENSQUARE, CLOSEDSQUARE, DOT, PRINT, STATIC, FUNC, PRINTF, GREATEREQUAL, LESSEQUAL, PANIC
}
private static HashMap<String, Token> statementMap = new HashMap<>();
@ -30,6 +30,7 @@ class Tokenizer {
statementMap.put("print", Token.PRINT);
statementMap.put("printf", Token.PRINTF);
statementMap.put("func", Token.FUNC);
statementMap.put("panic", Token.PANIC);
}
private final Reader in;
@ -150,13 +151,17 @@ class Tokenizer {
case '<':
if (isNextChar('<')) {
token = Token.SHIFTLEFT;
} else if (isNextChar('=')) {
token = Token.LESSEQUAL;
} else {
token = Token.SMALER;
token = Token.LESS;
}
break;
case '>':
if (isNextChar('>')) {
token = Token.SHIFTRIGHT;
} else if (isNextChar('=')) {
token = Token.GREATEREQUAL;
} else {
token = Token.GREATER;
}

2
src/main/java/de/neemann/digital/hdl/vhdl/VHDLGenerator.java
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@ -67,7 +67,7 @@ public class VHDLGenerator implements Closeable {
public VHDLGenerator(ElementLibrary library, CodePrinter out) throws IOException {
this.library = library;
this.out = out;
vhdlLibrary = new VHDLLibrary(library);
vhdlLibrary = new VHDLLibrary();
}
/**

17
src/main/java/de/neemann/digital/hdl/vhdl/VHDLLibrary.java
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@ -10,8 +10,6 @@ import de.neemann.digital.core.basic.*;
import de.neemann.digital.core.element.ElementTypeDescription;
import de.neemann.digital.core.extern.External;
import de.neemann.digital.core.memory.ROM;
import de.neemann.digital.core.wiring.*;
import de.neemann.digital.draw.library.ElementLibrary;
import de.neemann.digital.hdl.model.HDLException;
import de.neemann.digital.hdl.model.HDLNode;
import de.neemann.digital.hdl.model.Port;
@ -32,17 +30,14 @@ public class VHDLLibrary {
private static final Logger LOGGER = LoggerFactory.getLogger(VHDLLibrary.class);
private final HashMap<String, VHDLEntity> map;
private final ElementLibrary elementLibrary;
private ArrayList<HDLNode> nodeList = new ArrayList<>();
/**
* Creates a new instance
*
* @param elementLibrary the elements library
* @throws IOException IOException
*/
public VHDLLibrary(ElementLibrary elementLibrary) throws IOException {
this.elementLibrary = elementLibrary;
public VHDLLibrary() throws IOException {
map = new HashMap<>();
put(And.DESCRIPTION, new OperateVHDL("AND", false, And.DESCRIPTION));
put(NAnd.DESCRIPTION, new OperateVHDL("AND", true, NAnd.DESCRIPTION));
@ -50,18 +45,8 @@ public class VHDLLibrary {
put(NOr.DESCRIPTION, new OperateVHDL("OR", true, NOr.DESCRIPTION));
put(XOr.DESCRIPTION, new OperateVHDL("XOR", false, XOr.DESCRIPTION));
put(XNOr.DESCRIPTION, new OperateVHDL("XOR", true, XNOr.DESCRIPTION));
put(Not.DESCRIPTION, new NotVHDL());
//put(Multiplexer.DESCRIPTION, new MultiplexerVHDL());
put(Decoder.DESCRIPTION, new DecoderVHDL());
put(Demultiplexer.DESCRIPTION, new DemultiplexerVHDL());
put(BitSelector.DESCRIPTION, new BitSelectorVHDL());
put(Driver.DESCRIPTION, new DriverVHDL(false));
put(DriverInvSel.DESCRIPTION, new DriverVHDL(true));
put(Comparator.DESCRIPTION, new ComparatorVHDL());
// put(BitExtender.DESCRIPTION, new BitExtenderVHDL());
put(PriorityEncoder.DESCRIPTION, new PriorityEncoderVHDL());
put(External.DESCRIPTION, new ExternalVHDL());
put(ROM.DESCRIPTION, new ROMVHDL());

63
src/main/java/de/neemann/digital/hdl/vhdl/lib/BitSelectorVHDL.java
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@ -1,63 +0,0 @@
/*
* Copyright (c) 2017 Helmut Neemann
* Use of this source code is governed by the GPL v3 license
* that can be found in the LICENSE file.
*/
package de.neemann.digital.hdl.vhdl.lib;
import de.neemann.digital.core.element.Keys;
import de.neemann.digital.core.wiring.BitSelector;
import de.neemann.digital.hdl.model.HDLNode;
import de.neemann.digital.hdl.model.Port;
import de.neemann.digital.hdl.printer.CodePrinter;
import java.io.IOException;
import java.util.ArrayList;
import java.util.HashSet;
import static de.neemann.digital.hdl.vhdl.lib.MultiplexerVHDL.getBin;
/**
* The BitSelector VHDL entity
*/
public class BitSelectorVHDL extends VHDLEntitySimple {
private HashSet<Integer> first = new HashSet<>();
/**
* Creates a new instance
*/
public BitSelectorVHDL() {
super(BitSelector.DESCRIPTION);
}
@Override
public String getName(HDLNode node) {
int sel = node.get(Keys.SELECTOR_BITS);
return "BIT_SEL_" + sel;
}
@Override
public boolean needsOutput(HDLNode node) {
int sel = node.get(Keys.SELECTOR_BITS);
return !first.contains(sel);
}
@Override
public void writeArchitecture(CodePrinter out, HDLNode node) throws IOException {
int sel = node.get(Keys.SELECTOR_BITS);
ArrayList<Port> inputs = node.getPorts().getInputs();
out.println("with " + inputs.get(1).getName() + " select").inc();
out.print(node.getPorts().getOutputs().get(0).getName()).println(" <=").inc();
int inBits = 1 << sel;
for (int i = 0; i < inBits; i++)
out.print(inputs.get(0).getName()).print("(").print(i).print(") when ").print(getBin(i, sel)).println(",");
out.println("'0' when others;");
out.dec().dec();
first.add(sel);
}
}

58
src/main/java/de/neemann/digital/hdl/vhdl/lib/DecoderVHDL.java
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@ -1,58 +0,0 @@
/*
* Copyright (c) 2017 Helmut Neemann
* Use of this source code is governed by the GPL v3 license
* that can be found in the LICENSE file.
*/
package de.neemann.digital.hdl.vhdl.lib;
import de.neemann.digital.core.element.Keys;
import de.neemann.digital.core.wiring.Decoder;
import de.neemann.digital.hdl.model.HDLException;
import de.neemann.digital.hdl.model.HDLNode;
import de.neemann.digital.hdl.model.Port;
import de.neemann.digital.hdl.printer.CodePrinter;
import java.io.IOException;
import java.util.ArrayList;
import java.util.HashSet;
/**
* The decoder VHDL entity
*/
public class DecoderVHDL extends VHDLEntitySimple {
private HashSet<Integer> written = new HashSet<>();
/**
* Creates a new instance
*/
public DecoderVHDL() {
super(Decoder.DESCRIPTION);
}
@Override
public boolean needsOutput(HDLNode node) {
return !written.contains(node.get(Keys.SELECTOR_BITS));
}
@Override
public String getName(HDLNode node) {
int sel = node.get(Keys.SELECTOR_BITS);
return "MUX_GATE_" + sel;
}
@Override
public void writeArchitecture(CodePrinter out, HDLNode node) throws IOException, HDLException {
int sel = node.get(Keys.SELECTOR_BITS);
ArrayList<Port> outputs = node.getPorts().getOutputs();
for (int i = 0; i < outputs.size(); i++) {
out.print(outputs.get(i).getName());
out.print(" <= '1' when ");
out.print(node.getPorts().getInputs().get(0).getName());
out.print(" = ");
out.print(MultiplexerVHDL.getBin(i, sel));
out.println(" else '0';");
}
written.add(node.get(Keys.SELECTOR_BITS));
}
}

106
src/main/java/de/neemann/digital/hdl/vhdl/lib/DemultiplexerVHDL.java
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@ -1,106 +0,0 @@
/*
* Copyright (c) 2017 Helmut Neemann
* Use of this source code is governed by the GPL v3 license
* that can be found in the LICENSE file.
*/
package de.neemann.digital.hdl.vhdl.lib;
import de.neemann.digital.core.element.Keys;
import de.neemann.digital.core.wiring.Demultiplexer;
import de.neemann.digital.hdl.model.HDLException;
import de.neemann.digital.hdl.model.HDLNode;
import de.neemann.digital.hdl.model.Port;
import de.neemann.digital.hdl.printer.CodePrinter;
import java.io.IOException;
import java.util.ArrayList;
import java.util.HashSet;
import static de.neemann.digital.hdl.vhdl.lib.MultiplexerVHDL.getBin;
/**
* the demultiplexer VHDL entity
*/
public class DemultiplexerVHDL extends VHDLEntitySimple {
private HashSet<Integer> first = new HashSet<>();
private HashSet<Integer> firstBus = new HashSet<>();
/**
* Creates a new instance
*/
public DemultiplexerVHDL() {
super(Demultiplexer.DESCRIPTION);
}
@Override
public String getName(HDLNode node) {
int sel = node.get(Keys.SELECTOR_BITS);
if (node.get(Keys.BITS) > 1)
return "DEMUX_GATE_BUS_" + sel;
else
return "DEMUX_GATE_" + sel;
}
@Override
public boolean needsOutput(HDLNode node) {
int sel = node.get(Keys.SELECTOR_BITS);
if (node.get(Keys.BITS) > 1)
return !firstBus.contains(sel);
else
return !first.contains(sel);
}
@Override
public void writeDeclaration(CodePrinter out, HDLNode node) throws IOException, HDLException {
if (node.get(Keys.BITS) > 1) {
out.println("generic ( bitCount : integer );");
out.println("port (").inc();
ArrayList<Port> inputs = node.getPorts().getInputs();
writePort(out, inputs.get(0));
out.println(";");
writePortGeneric(out, node.getPorts().getInputs().get(1));
ArrayList<Port> outputs = node.getPorts().getOutputs();
for (Port o : outputs) {
out.println(";");
writePortGeneric(out, o);
}
out.println(" );").dec();
} else
super.writeDeclaration(out, node);
}
@Override
public void writeArchitecture(CodePrinter out, HDLNode node) throws IOException {
int sel = node.get(Keys.SELECTOR_BITS);
out.inc();
ArrayList<Port> outputs = node.getPorts().getOutputs();
Port s = node.getPorts().getInputs().get(0);
Port input = node.getPorts().getInputs().get(1);
for (int i = 0; i < outputs.size(); i++) {
out.print(outputs.get(i).getName());
out.print(" <= ");
out.print(input.getName());
out.print(" when ");
out.print(s.getName());
out.print(" = ");
out.print(getBin(i, s.getBits()));
out.print(" else ");
if (node.get(Keys.BITS) > 1)
out.println("(others => '0');");
else
out.println("'0';");
}
out.dec();
if (node.get(Keys.BITS) > 1)
firstBus.add(sel);
else
first.add(sel);
}
@Override
public void writeGenericMap(CodePrinter out, HDLNode node) throws IOException {
if (node.get(Keys.BITS) > 1)
out.print("generic map ( bitCount => ").print(node.get(Keys.BITS)).println(")");
}
}

71
src/main/java/de/neemann/digital/hdl/vhdl/lib/DriverVHDL.java
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@ -1,71 +0,0 @@
/*
* Copyright (c) 2017 Helmut Neemann
* Use of this source code is governed by the GPL v3 license
* that can be found in the LICENSE file.
*/
package de.neemann.digital.hdl.vhdl.lib;
import de.neemann.digital.core.element.Keys;
import de.neemann.digital.core.wiring.Driver;
import de.neemann.digital.hdl.model.HDLNode;
import de.neemann.digital.hdl.printer.CodePrinter;
import java.io.IOException;
/**
* the driver VHDL entity
*/
public class DriverVHDL extends VHDLEntityBus {
private final boolean invert;
private boolean first = true;
private boolean firstBus = true;
/**
* creates a new instance
*
* @param invert true if inverted input
*/
public DriverVHDL(boolean invert) {
super(Driver.DESCRIPTION);
this.invert = invert;
}
@Override
public String getName(HDLNode node) {
if (node.get(Keys.BITS) > 1)
return "DRIVER_GATE_BUS";
else
return "DRIVER_GATE";
}
@Override
public boolean needsOutput(HDLNode node) {
if (node.get(Keys.BITS) > 1)
return firstBus;
else
return first;
}
@Override
public void writeArchitecture(CodePrinter out, HDLNode node) throws IOException {
out.print(node.getPorts().getOutputs().get(0).getName());
out.print(" <= ");
out.print(node.getPorts().getInputs().get(0).getName());
out.print(" when ");
out.print(node.getPorts().getInputs().get(1).getName());
if (invert)
out.print(" = '0' else ");
else
out.print(" = '1' else ");
if (node.get(Keys.BITS) > 1)
out.println("(others => 'Z');");
else
out.println("'Z';");
if (node.get(Keys.BITS) > 1)
firstBus = false;
else
first = false;
}
}

119
src/main/java/de/neemann/digital/hdl/vhdl/lib/MultiplexerVHDL.java
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@ -1,119 +0,0 @@
/*
* Copyright (c) 2017 Helmut Neemann
* Use of this source code is governed by the GPL v3 license
* that can be found in the LICENSE file.
*/
package de.neemann.digital.hdl.vhdl.lib;
import de.neemann.digital.core.element.Keys;
import de.neemann.digital.core.wiring.Multiplexer;
import de.neemann.digital.hdl.model.HDLException;
import de.neemann.digital.hdl.model.HDLNode;
import de.neemann.digital.hdl.model.Port;
import de.neemann.digital.hdl.printer.CodePrinter;
import java.io.IOException;
import java.util.ArrayList;
import java.util.HashSet;
/**
* the multiplexer VHDL entity
*/
public class MultiplexerVHDL extends VHDLEntitySimple {
private HashSet<Integer> first = new HashSet<>();
private HashSet<Integer> firstBus = new HashSet<>();
/**
* Creates a new instance
*/
public MultiplexerVHDL() {
super(Multiplexer.DESCRIPTION);
}
@Override
public String getName(HDLNode node) {
int sel = node.get(Keys.SELECTOR_BITS);
if (node.get(Keys.BITS) > 1)
return "MUX_GATE_BUS_" + sel;
else
return "MUX_GATE_" + sel;
}
@Override
public boolean needsOutput(HDLNode node) {
int sel = node.get(Keys.SELECTOR_BITS);
if (node.get(Keys.BITS) > 1)
return !firstBus.contains(sel);
else
return !first.contains(sel);
}
@Override
public void writeDeclaration(CodePrinter out, HDLNode node) throws IOException, HDLException {
if (node.get(Keys.BITS) > 1) {
out.println("generic ( bitCount : integer );");
out.println("port (").inc();
ArrayList<Port> inputs = node.getPorts().getInputs();
writePort(out, inputs.get(0));
out.println(";");
writePortGeneric(out, node.getPorts().getOutputs().get(0));
for (int i = 1; i < inputs.size(); i++) {
out.println(";");
writePortGeneric(out, inputs.get(i));
}
out.println(" );").dec();
} else
super.writeDeclaration(out, node);
}
@Override
public void writeArchitecture(CodePrinter out, HDLNode node) throws IOException {
int sel = node.get(Keys.SELECTOR_BITS);
ArrayList<Port> inputs = node.getPorts().getInputs();
out.println("with " + inputs.get(0).getName() + " select").inc();
out.print(node.getPorts().getOutputs().get(0).getName()).println(" <=").inc();
for (int i = 1; i < inputs.size(); i++)
out.print(inputs.get(i).getName()).print(" when ").print(getBin(i - 1, sel)).println(",");
if (node.get(Keys.BITS) == 1)
out.println("'0' when others;");
else
out.println("(others => '0') when others;");
out.dec().dec();
if (node.get(Keys.BITS) > 1)
firstBus.add(sel);
else
first.add(sel);
}
/**
* Returns the given value as a VHDL string
*
* @param val the value
* @param bits the number of bits
* @return the string representation
*/
public static String getBin(int val, int bits) {
String s = Integer.toBinaryString(val);
while (s.length() < bits)
s = "0" + s;
if (bits > 1)
s = "\"" + s + "\"";
else
s = "'" + s + "'";
return s;
}
@Override
public void writeGenericMap(CodePrinter out, HDLNode node) throws IOException {
if (node.get(Keys.BITS) > 1)
out.print("generic map ( bitCount => ").print(node.get(Keys.BITS)).println(")");
}
}

58
src/main/java/de/neemann/digital/hdl/vhdl/lib/NotVHDL.java
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@ -1,58 +0,0 @@
/*
* Copyright (c) 2017 Helmut Neemann
* Use of this source code is governed by the GPL v3 license
* that can be found in the LICENSE file.
*/
package de.neemann.digital.hdl.vhdl.lib;
import de.neemann.digital.core.basic.Not;
import de.neemann.digital.core.element.Keys;
import de.neemann.digital.hdl.model.HDLNode;
import de.neemann.digital.hdl.printer.CodePrinter;
import java.io.IOException;
/**
* the not VHDL entity
*/
public class NotVHDL extends VHDLEntityBus {
private boolean first = true;
private boolean firstBus = true;
/**
* Creates a new instance
*/
public NotVHDL() {
super(Not.DESCRIPTION);
}
@Override
public String getName(HDLNode node) {
if (node.get(Keys.BITS) > 1)
return "NOT_GATE_BUS";
else
return "NOT_GATE";
}
@Override
public boolean needsOutput(HDLNode node) {
if (node.get(Keys.BITS) > 1)
return firstBus;
else
return first;
}
@Override
public void writeArchitecture(CodePrinter out, HDLNode node) throws IOException {
out.print(node.getPorts().getOutputs().get(0).getName());
out.print(" <= ");
out.print(" NOT( ");
out.print(node.getPorts().getInputs().get(0).getName());
out.println(" );");
if (node.get(Keys.BITS) > 1)
firstBus = false;
else
first = false;
}
}

88
src/main/java/de/neemann/digital/hdl/vhdl/lib/PriorityEncoderVHDL.java
View File

@ -1,88 +0,0 @@
/*
* Copyright (c) 2017 Helmut Neemann
* Use of this source code is governed by the GPL v3 license
* that can be found in the LICENSE file.
*/
package de.neemann.digital.hdl.vhdl.lib;
import de.neemann.digital.core.element.Keys;
import de.neemann.digital.core.wiring.PriorityEncoder;
import de.neemann.digital.hdl.model.HDLNode;
import de.neemann.digital.hdl.model.Port;
import de.neemann.digital.hdl.printer.CodePrinter;
import java.io.IOException;
import java.util.ArrayList;
import java.util.HashSet;
/**
* The priority encoder VHDL entity.
*/
public class PriorityEncoderVHDL extends VHDLEntitySimple {
private HashSet<Integer> first = new HashSet<>();
/**
* Creates a new instance
*/
public PriorityEncoderVHDL() {
super(PriorityEncoder.DESCRIPTION);
}
@Override
public String getName(HDLNode node) {
int sel = node.get(Keys.SELECTOR_BITS);
return "PRIORITY_GATE_" + sel;
}
@Override
public boolean needsOutput(HDLNode node) {
int sel = node.get(Keys.SELECTOR_BITS);
return !first.contains(sel);
}
@Override
public void writeArchitecture(CodePrinter out, HDLNode node) throws IOException {
int sel = node.get(Keys.SELECTOR_BITS);
ArrayList<Port> inputs = node.getPorts().getInputs();
out.print(node.getPorts().getOutputs().get(0).getName()).println(" <=").inc();
for (int i = inputs.size() - 1; i >= 1; i--)
out.print(getBin(i, sel)).print(" when ").print(inputs.get(i).getName()).println(" = '1' else");
out.print(getBin(0, sel)).println(" ;");
out.dec();
out.print(node.getPorts().getOutputs().get(1).getName()).print(" <= ");
for (int i = 0; i < inputs.size(); i++) {
if (i > 0)
out.print(" OR ");
out.print(inputs.get(i).getName());
}
out.println(";");
first.add(sel);
}
/**
* Returns the given value as a VHDL string
*
* @param val the value
* @param bits the number of bits
* @return the string representation
*/
public static String getBin(int val, int bits) {
String s = Integer.toBinaryString(val);
while (s.length() < bits)
s = "0" + s;
if (bits > 1)
s = "\"" + s + "\"";
else
s = "'" + s + "'";
return s;
}
}

6
src/main/java/de/neemann/digital/hdl/vhdl/lib/VHDLEntityBus.java
View File

@ -32,14 +32,14 @@ public abstract class VHDLEntityBus extends VHDLEntitySimple {
@Override
public void writeDeclaration(CodePrinter out, HDLNode node) throws IOException, HDLException {
if (node.get(Keys.BITS) > 1) {
out.println("generic ( bitCount : integer );");
out.println("generic ( Bits : integer );");
out.println("port (").inc();
Separator semic = new Separator(";\n");
for (Port p : node.getPorts()) {
semic.check(out);
out.print(p.getName()).print(": ").print(getDirection(p));
if (p.getBits()>1)
out.print(" std_logic_vector ((bitCount-1) downto 0)");
out.print(" std_logic_vector ((Bits-1) downto 0)");
else
out.print(" std_logic");
}
@ -51,7 +51,7 @@ public abstract class VHDLEntityBus extends VHDLEntitySimple {
@Override
public void writeGenericMap(CodePrinter out, HDLNode node) throws IOException {
if (node.get(Keys.BITS) > 1)
out.print("generic map ( bitCount => ").print(node.get(Keys.BITS)).println(")");
out.print("generic map ( Bits => ").print(node.get(Keys.BITS)).println(")");
}
}

26
src/main/java/de/neemann/digital/hdl/vhdl/lib/VHDLTemplate.java
View File

@ -170,7 +170,7 @@ public class VHDLTemplate implements VHDLEntity {
try {
String port = getEntity(node).getPortDecl();
if (port != null) {
out.print(port);
out.dec().print(port).inc();
} else {
out.println("port (").inc();
Separator semic = new Separator(";\n");
@ -351,7 +351,7 @@ public class VHDLTemplate implements VHDLEntity {
}
private final static class FunctionValue extends Function {
private final static class FunctionValue extends FuncAdapter {
/**
* Creates a new function
*/
@ -360,11 +360,25 @@ public class VHDLTemplate implements VHDLEntity {
}
@Override
public Object calcValue(Context c, ArrayList<Expression> args) throws HGSEvalException {
int val = Value.toInt(args.get(0).value(c));
int bits = Value.toInt(args.get(1).value(c));
return MultiplexerVHDL.getBin(val, bits);
protected Object f(Object... args) throws HGSEvalException {
int val = Value.toInt(args[0]);
int bits = Value.toInt(args[1]);
return getBin(val, bits);
}
private static String getBin(int val, int bits) {
String s = Integer.toBinaryString(val);
while (s.length() < bits)
s = "0" + s;
if (bits > 1)
s = "\"" + s + "\"";
else
s = "'" + s + "'";
return s;
}
}
private static final class Generic {

23
src/main/resources/vhdl/DIG_BitSelector.tem Normal file
View File

@ -0,0 +1,23 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
<?
entityName="BIT_SEL_"+elem.'Selector Bits';
Bits=1<<elem.'Selector Bits';
?>
entity <?=entityName?> is
port (
PORT_out: out std_logic;
PORT_in: in <?=type(Bits)?>;
PORT_sel: in <?=type(elem.'Selector Bits')?> );
end <?=entityName?>;
architecture <?=entityName?>_arch of <?=entityName?> is
begin
with PORT_sel select
PORT_out <=
<? for (n=0;n<Bits;n++) { ?>
PORT_in(<?=n?>) when <?=value(n, elem.'Selector Bits') ?>,
<? } print(zero(elem.Bits));?> when others;
end <?=entityName?>_arch;

21
src/main/resources/vhdl/DIG_Decoder.tem Normal file
View File

@ -0,0 +1,21 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
<?
entityName="DECODER_"+elem.'Selector Bits';
outputs=1<<elem.'Selector Bits';
?>
entity <?=entityName?> is
port (
<? for (i=0;i<outputs;i++) {?>
PORT_out_<?=i?>: out std_logic;
<? } ?>
PORT_sel: in <?=type(elem.'Selector Bits')?> );
end <?=entityName?>;
architecture <?=entityName?>_arch of <?=entityName?> is
begin
<? for (i=0;i<outputs;i++) {?>
PORT_out_<?=i?> <= '1' when PORT_sel = <?=value(i,elem.'Selector Bits')?> else '0';
<? } ?>
end <?=entityName?>_arch;

31
src/main/resources/vhdl/DIG_Demultiplexer.tem Normal file
View File

@ -0,0 +1,31 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
<?
if (elem.Bits=1)
entityName="DEMUX_GATE_"+elem.'Selector Bits';
else
entityName="DEMUX_GATE_BUS_"+elem.'Selector Bits';
outputs=1<<elem.'Selector Bits';
?>
entity <?=entityName?> is
<? beginGenericPort();?>
<? if (elem.Bits>1) { ?>
generic ( Bits : integer );<? registerGeneric("Bits");?>
<? } ?>
port (
<? for (i=0;i<outputs;i++) {?>
PORT_out_<?=i?>: out <?=genericType(elem.Bits)?>;
<? } ?>
PORT_sel: in <?=type(elem.'Selector Bits')?>;
PORT_in: in <?=genericType(elem.Bits)?> );
<? endGenericPort();?>
end <?=entityName?>;
architecture <?=entityName?>_arch of <?=entityName?> is
begin
<? for (i=0;i<outputs;i++) {?>
PORT_out_<?=i?> <= PORT_in when PORT_sel = <?=value(i,elem.'Selector Bits')?> else <?=zero(elem.Bits)?>;
<? } ?>
end <?=entityName?>_arch;

24
src/main/resources/vhdl/DIG_Driver.tem Normal file
View File

@ -0,0 +1,24 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
<?
if (elem.Bits=1)
entityName="DRIVER_INV_GATE";
else
entityName="DRIVER_INV_GATE_BUS";
?>
entity <?=entityName?> is
<?beginGenericPort();?>
<?if (elem.Bits>1) {?>generic ( Bits : integer ); <?registerGeneric("Bits"); }?>
port (
PORT_out: out <?=genericType(elem.Bits)?>;
PORT_in: in <?=genericType(elem.Bits)?>;
PORT_sel: in std_logic );
<?endGenericPort();?>
end <?=entityName?>;
architecture <?=entityName?>_arch of <?=entityName?> is
begin
PORT_out <= PORT_in when PORT_sel = '1' else <? if (elem.Bits=1) { ?>'Z'<?} else {?>(others => 'Z')<? } ?>;
end <?=entityName?>_arch;

24
src/main/resources/vhdl/DIG_DriverInvSel.tem Normal file
View File

@ -0,0 +1,24 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
<?
if (elem.Bits=1)
entityName="DRIVER_INV_GATE";
else
entityName="DRIVER_INV_GATE_BUS";
?>
entity <?=entityName?> is
<?beginGenericPort();?>
<?if (elem.Bits>1) {?>generic ( Bits : integer ); <?registerGeneric("Bits"); }?>
port (
PORT_out: out <?=genericType(elem.Bits)?>;
PORT_in: in <?=genericType(elem.Bits)?>;
PORT_sel: in std_logic );
<?endGenericPort();?>
end <?=entityName?>;
architecture <?=entityName?>_arch of <?=entityName?> is
begin
PORT_out <= PORT_in when PORT_sel = '0' else <? if (elem.Bits=1) { ?>'Z'<?} else {?>(others => 'Z')<? } ?>;
end <?=entityName?>_arch;

23
src/main/resources/vhdl/DIG_Not.tem Normal file
View File

@ -0,0 +1,23 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
<?
if (elem.Bits=1)
entityName="NOT_GATE";
else
entityName="NOT_GATE_BUS";
?>
entity <?=entityName?> is
<?beginGenericPort();?>
<?if (elem.Bits>1) {?>generic ( Bits : integer );<?registerGeneric("Bits"); }?>
port (
PORT_out: out <?=genericType(elem.Bits)?>;
PORT_in: in <?=genericType(elem.Bits)?> );
<?endGenericPort();?>
end <?=entityName?>;
architecture <?=entityName?>_arch of <?=entityName?> is
begin
PORT_out <= NOT( PORT_in );
end <?=entityName?>_arch;

30
src/main/resources/vhdl/DIG_PriorityEncoder.tem Normal file
View File

@ -0,0 +1,30 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
<?
entityName="PRIORITY_GATE_"+elem.'Selector Bits';
inputs=1<<elem.'Selector Bits';
?>
entity <?=entityName?> is
port (
PORT_num: out <?=type(elem.'Selector Bits')?>;
PORT_any: out std_logic;
<? for (n=0;n<inputs;n++) { ?>
PORT_in<?=n?>: in std_logic<?if (n=inputs-1) print(" )"); ?>;
<? } ?>
end <?=entityName?>;
architecture <?=entityName?>_arch of <?=entityName?> is
begin
PORT_num <=
<? for (n=inputs-1;n>0;n--) { ?>
<?=value(n,elem.'Selector Bits')?> when PORT_in<?=n?> = '1' else
<? } ?>
<?=value(0,elem.'Selector Bits')?> ;
PORT_any <= <?
for (n=0;n<inputs;n++) {
print("PORT_in",n);
if (n<inputs-1) print(" OR ");
}?>;
end <?=entityName?>_arch;

90
src/test/java/de/neemann/digital/hdl/hgs/ParserTest.java
View File

@ -19,64 +19,72 @@ import java.util.Map;
public class ParserTest extends TestCase {
public void testParseExpressionArith() throws IOException, ParserException, HGSEvalException {
assertEquals(3L, new Parser("1+2").parseExpression().value(new Context()));
assertEquals("HelloWorld", new Parser("\"Hello\"+\"World\"").parseExpression().value(new Context()));
assertEquals(3L, new Parser("5-2").parseExpression().value(new Context()));
assertEquals(10L, new Parser("5*2").parseExpression().value(new Context()));
assertEquals(2L, new Parser("6/3").parseExpression().value(new Context()));
assertEquals(8L, new Parser("1<<3").parseExpression().value(new Context()));
assertEquals(2L, new Parser("16>>3").parseExpression().value(new Context()));
assertEquals(4L, new Parser("9%5").parseExpression().value(new Context()));
public void testparseExpArith() throws IOException, ParserException, HGSEvalException {
assertEquals(3L, new Parser("1+2").parseExp().value(new Context()));
assertEquals("HelloWorld", new Parser("\"Hello\"+\"World\"").parseExp().value(new Context()));
assertEquals(3L, new Parser("5-2").parseExp().value(new Context()));
assertEquals(10L, new Parser("5*2").parseExp().value(new Context()));
assertEquals(2L, new Parser("6/3").parseExp().value(new Context()));
assertEquals(8L, new Parser("1<<3").parseExp().value(new Context()));
assertEquals(2L, new Parser("16>>3").parseExp().value(new Context()));
assertEquals(4L, new Parser("9%5").parseExp().value(new Context()));
assertEquals(-5L, new Parser("-5").parseExpression().value(new Context()));
assertEquals(6L, new Parser("2*(1+2)").parseExpression().value(new Context()));
assertEquals(-5L, new Parser("-5").parseExp().value(new Context()));
assertEquals(6L, new Parser("2*(1+2)").parseExp().value(new Context()));
try {
new Parser("1+").parseExpression().value(new Context());
new Parser("1+").parseExp().value(new Context());
fail();
} catch (ParserException e) {
assertTrue(true);
}
assertEquals("Hallo4", new Parser("\"Hallo\" + (2*2)").parseExpression().value(new Context()));
assertEquals("Hallo_true", new Parser("\"Hallo_\" + (1<2)").parseExpression().value(new Context()));
assertEquals("Hallo4", new Parser("\"Hallo\" + (2*2)").parseExp().value(new Context()));
assertEquals("Hallo_true", new Parser("\"Hallo_\" + (1<2)").parseExp().value(new Context()));
}
public void testParseExpressionCompare() throws IOException, ParserException, HGSEvalException {
assertEquals(true, new Parser("5=5").parseExpression().value(new Context()));
assertEquals(true, new Parser("\"Hello\"=\"Hello\"").parseExpression().value(new Context()));
assertEquals(false, new Parser("\"Hello\"=\"World\"").parseExpression().value(new Context()));
assertEquals(false, new Parser("5!=5").parseExpression().value(new Context()));
assertEquals(false, new Parser("\"Hello\"!=\"Hello\"").parseExpression().value(new Context()));
assertEquals(true, new Parser("\"Hello\"!=\"World\"").parseExpression().value(new Context()));
public void testparseExpCompare() throws IOException, ParserException, HGSEvalException {
assertEquals(true, new Parser("5=5").parseExp().value(new Context()));
assertEquals(true, new Parser("\"Hello\"=\"Hello\"").parseExp().value(new Context()));
assertEquals(false, new Parser("\"Hello\"=\"World\"").parseExp().value(new Context()));
assertEquals(false, new Parser("5!=5").parseExp().value(new Context()));
assertEquals(false, new Parser("\"Hello\"!=\"Hello\"").parseExp().value(new Context()));
assertEquals(true, new Parser("\"Hello\"!=\"World\"").parseExp().value(new Context()));
assertEquals(false, new Parser("5<5").parseExpression().value(new Context()));
assertEquals(true, new Parser("4<5").parseExpression().value(new Context()));
assertEquals(false, new Parser("5>5").parseExpression().value(new Context()));
assertEquals(false, new Parser("4>5").parseExpression().value(new Context()));
assertEquals(false, new Parser("5<5").parseExp().value(new Context()));
assertEquals(true, new Parser("4<5").parseExp().value(new Context()));
assertEquals(false, new Parser("5>5").parseExp().value(new Context()));
assertEquals(false, new Parser("4>5").parseExp().value(new Context()));
assertEquals(false, new Parser("4>=5").parseExp().value(new Context()));
assertEquals(true, new Parser("5>=5").parseExp().value(new Context()));
assertEquals(true, new Parser("6>=5").parseExp().value(new Context()));
assertEquals(true, new Parser("4<=5").parseExp().value(new Context()));
assertEquals(true, new Parser("5<=5").parseExp().value(new Context()));
assertEquals(false, new Parser("6<=5").parseExp().value(new Context()));
}
public void testParseExpressionBool() throws IOException, ParserException, HGSEvalException {
assertEquals(3L, new Parser("1|2").parseExpression().value(new Context()));
assertEquals(true, new Parser("a|b").parseExpression()
public void testparseExpBool() throws IOException, ParserException, HGSEvalException {
assertEquals(3L, new Parser("1|2").parseExp().value(new Context()));
assertEquals(true, new Parser("a|b").parseExp()
.value(new Context()
.setVar("a", true)
.setVar("b", false)));
assertEquals(0L, new Parser("1&2").parseExpression().value(new Context()));
assertEquals(false, new Parser("a&b").parseExpression()
assertEquals(0L, new Parser("1&2").parseExp().value(new Context()));
assertEquals(false, new Parser("a&b").parseExp()
.value(new Context()
.setVar("a", true)
.setVar("b", false)));
assertEquals(3L, new Parser("1^2").parseExpression()
assertEquals(3L, new Parser("1^2").parseExp()
.value(new Context()));
assertEquals(true, new Parser("a^b").parseExpression()
assertEquals(true, new Parser("a^b").parseExp()
.value(new Context()
.setVar("a", true)
.setVar("b", false)));
assertEquals(-2L, new Parser("~1").parseExpression().value(new Context()));
assertEquals(false, new Parser("~a").parseExpression()
assertEquals(-2L, new Parser("~1").parseExp().value(new Context()));
assertEquals(false, new Parser("~a").parseExp()
.value(new Context()
.setVar("a", true)));
@ -310,4 +318,18 @@ public class ParserTest extends TestCase {
exec("<? f=func(a){ ?>testtext<? print(a*3); return=output; }; print(f(4),f(5));?>").toString());
}
public void testPanic() throws IOException, ParserException, HGSEvalException {
Statement s = new Parser("<? if (i>1) panic(\"myError\"); ?>").parse();
exec(s, new Context().setVar("i", 0));
exec(s, new Context().setVar("i", 1));
try {
exec(s, new Context().setVar("i", 2));
fail();
} catch (HGSEvalException e) {
assertEquals("myError", e.getMessage());
}
}
}

18
src/test/java/de/neemann/digital/hdl/vhdl/ConstantTest.java
View File

@ -71,18 +71,18 @@ public class ConstantTest extends TestCase {
"end main;\n" +
"architecture main_arch of main is\n" +
" component XOR_GATE_BUS_2\n" +
" generic ( bitCount : integer );\n" +
" generic ( Bits : integer );\n" +
" port (\n" +
" PORT_out: out std_logic_vector ((bitCount-1) downto 0);\n" +
" PORT_In_1: in std_logic_vector ((bitCount-1) downto 0);\n" +
" PORT_In_2: in std_logic_vector ((bitCount-1) downto 0) );\n" +
" PORT_out: out std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_In_1: in std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_In_2: in std_logic_vector ((Bits-1) downto 0) );\n" +
" end component;\n" +
" signal S0: std_logic_vector (2 downto 0);\n" +
" signal S1: std_logic_vector (2 downto 0);\n" +
"begin\n" +
" S1 <= \"000\";\n" +
" gate0 : XOR_GATE_BUS_2\n" +
" generic map ( bitCount => 3)\n" +
" generic map ( Bits => 3)\n" +
" port map (\n" +
" PORT_out => S0,\n" +
" PORT_In_1 => PORT_A,\n" +
@ -92,11 +92,11 @@ public class ConstantTest extends TestCase {
"LIBRARY ieee;\n" +
"USE ieee.std_logic_1164.all;\n" +
"entity XOR_GATE_BUS_2 is\n" +
" generic ( bitCount : integer );\n" +
" generic ( Bits : integer );\n" +
" port (\n" +
" PORT_out: out std_logic_vector ((bitCount-1) downto 0);\n" +
" PORT_In_1: in std_logic_vector ((bitCount-1) downto 0);\n" +
" PORT_In_2: in std_logic_vector ((bitCount-1) downto 0) );\n" +
" PORT_out: out std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_In_1: in std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_In_2: in std_logic_vector ((Bits-1) downto 0) );\n" +
"end XOR_GATE_BUS_2;\n" +
"architecture XOR_GATE_BUS_2_arch of XOR_GATE_BUS_2 is\n" +
"begin\n" +

11
src/test/java/de/neemann/digital/hdl/vhdl/TestInSimulator.java
View File

@ -14,6 +14,7 @@ import de.neemann.digital.draw.library.ElementNotFoundException;
import de.neemann.digital.gui.Settings;
import de.neemann.digital.hdl.model.HDLException;
import de.neemann.digital.hdl.printer.CodePrinter;
import de.neemann.digital.hdl.printer.CodePrinterStr;
import de.neemann.digital.integration.FileScanner;
import de.neemann.digital.integration.Resources;
import de.neemann.digital.integration.TestExamples;
@ -30,6 +31,8 @@ import java.text.SimpleDateFormat;
import java.util.ArrayList;
import java.util.Date;
import static de.neemann.digital.integration.TestExamples.check;
/**
* Test vhdl files in ghdl simulator
*/
@ -43,7 +46,7 @@ public class TestInSimulator extends TestCase {
File examples = new File(Resources.getRoot(), "/dig/test/vhdl");
try {
int tested = new FileScanner(this::checkVHDLExport).noOutput().scan(examples);
assertEquals(27, tested);
assertEquals(28, tested);
assertEquals(tested, testBenches);
} catch (FileScanner.SkipAllException e) {
// if ghdl is not installed its also ok
@ -98,14 +101,14 @@ public class TestInSimulator extends TestCase {
int tested = new FileScanner(f -> {
checkVHDLExport(f);
// check simulation in Digital
TestExamples.check(f);
check(f);
}).noOutput().scan(source);
assertEquals(4, tested);
}
/*
//*
public void testInSimulatorDebug() throws Exception {
File file = new File(Resources.getRoot(),"dig/test/vhdl/registerFile.dig");
File file = new File(Resources.getRoot(),"dig/test/vhdl/BitSelect.dig");
ToBreakRunner br = new ToBreakRunner(file);
System.out.println(new VHDLGenerator(br.getLibrary(), new CodePrinterStr(true)).export(br.getCircuit()));

56
src/test/java/de/neemann/digital/hdl/vhdl/VHDLGeneratorTest.java
View File

@ -326,24 +326,24 @@ public class VHDLGeneratorTest extends TestCase {
"end main;\n" +
"architecture main_arch of main is\n" +
" component AND_GATE_BUS_2\n" +
" generic ( bitCount : integer );\n" +
" generic ( Bits : integer );\n" +
" port (\n" +
" PORT_out: out std_logic_vector ((bitCount-1) downto 0);\n" +
" PORT_In_1: in std_logic_vector ((bitCount-1) downto 0);\n" +
" PORT_In_2: in std_logic_vector ((bitCount-1) downto 0) );\n" +
" PORT_out: out std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_In_1: in std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_In_2: in std_logic_vector ((Bits-1) downto 0) );\n" +
" end component;\n" +
" component OR_GATE_BUS_2\n" +
" generic ( bitCount : integer );\n" +
" generic ( Bits : integer );\n" +
" port (\n" +
" PORT_out: out std_logic_vector ((bitCount-1) downto 0);\n" +
" PORT_In_1: in std_logic_vector ((bitCount-1) downto 0);\n" +
" PORT_In_2: in std_logic_vector ((bitCount-1) downto 0) );\n" +
" PORT_out: out std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_In_1: in std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_In_2: in std_logic_vector ((Bits-1) downto 0) );\n" +
" end component;\n" +
" component NOT_GATE_BUS\n" +
" generic ( bitCount : integer );\n" +
" generic ( Bits : integer );\n" +
" port (\n" +
" PORT_out: out std_logic_vector ((bitCount-1) downto 0);\n" +
" PORT_in: in std_logic_vector ((bitCount-1) downto 0) );\n" +
" PORT_out: out std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_in: in std_logic_vector ((Bits-1) downto 0) );\n" +
" end component;\n" +
" signal S0: std_logic_vector (1 downto 0);\n" +
" signal S1: std_logic_vector (1 downto 0);\n" +
@ -352,30 +352,32 @@ public class VHDLGeneratorTest extends TestCase {
" signal PORT_B_Neg: std_logic_vector (1 downto 0);\n" +
"begin\n" +
" gate0 : AND_GATE_BUS_2\n" +
" generic map ( bitCount => 2)\n" +
" generic map ( Bits => 2)\n" +
" port map (\n" +
" PORT_out => S1,\n" +
" PORT_In_1 => PORT_A_Neg,\n" +
" PORT_In_2 => PORT_B );\n" +
" gate1 : AND_GATE_BUS_2\n" +
" generic map ( bitCount => 2)\n" +
" generic map ( Bits => 2)\n" +
" port map (\n" +
" PORT_out => S2,\n" +
" PORT_In_1 => PORT_A,\n" +
" PORT_In_2 => PORT_B_Neg );\n" +
" gate2 : OR_GATE_BUS_2\n" +
" generic map ( bitCount => 2)\n" +
" generic map ( Bits => 2)\n" +
" port map (\n" +
" PORT_out => S0,\n" +
" PORT_In_1 => S1,\n" +
" PORT_In_2 => S2 );\n" +
" gate3 : NOT_GATE_BUS\n" +
" generic map ( bitCount => 2)\n" +
" generic map (\n" +
" Bits => 2)\n" +
" port map (\n" +
" PORT_out => PORT_A_Neg,\n" +
" PORT_in => PORT_A );\n" +
" gate4 : NOT_GATE_BUS\n" +
" generic map ( bitCount => 2)\n" +
" generic map (\n" +
" Bits => 2)\n" +
" port map (\n" +
" PORT_out => PORT_B_Neg,\n" +
" PORT_in => PORT_B );\n" +
@ -384,11 +386,11 @@ public class VHDLGeneratorTest extends TestCase {
"LIBRARY ieee;\n" +
"USE ieee.std_logic_1164.all;\n" +
"entity AND_GATE_BUS_2 is\n" +
" generic ( bitCount : integer );\n" +
" generic ( Bits : integer );\n" +
" port (\n" +
" PORT_out: out std_logic_vector ((bitCount-1) downto 0);\n" +
" PORT_In_1: in std_logic_vector ((bitCount-1) downto 0);\n" +
" PORT_In_2: in std_logic_vector ((bitCount-1) downto 0) );\n" +
" PORT_out: out std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_In_1: in std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_In_2: in std_logic_vector ((Bits-1) downto 0) );\n" +
"end AND_GATE_BUS_2;\n" +
"architecture AND_GATE_BUS_2_arch of AND_GATE_BUS_2 is\n" +
"begin\n" +
@ -397,11 +399,11 @@ public class VHDLGeneratorTest extends TestCase {
"LIBRARY ieee;\n" +
"USE ieee.std_logic_1164.all;\n" +
"entity OR_GATE_BUS_2 is\n" +
" generic ( bitCount : integer );\n" +
" generic ( Bits : integer );\n" +
" port (\n" +
" PORT_out: out std_logic_vector ((bitCount-1) downto 0);\n" +
" PORT_In_1: in std_logic_vector ((bitCount-1) downto 0);\n" +
" PORT_In_2: in std_logic_vector ((bitCount-1) downto 0) );\n" +
" PORT_out: out std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_In_1: in std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_In_2: in std_logic_vector ((Bits-1) downto 0) );\n" +
"end OR_GATE_BUS_2;\n" +
"architecture OR_GATE_BUS_2_arch of OR_GATE_BUS_2 is\n" +
"begin\n" +
@ -410,10 +412,10 @@ public class VHDLGeneratorTest extends TestCase {
"LIBRARY ieee;\n" +
"USE ieee.std_logic_1164.all;\n" +
"entity NOT_GATE_BUS is\n" +
" generic ( bitCount : integer );\n" +
" generic ( Bits : integer );\n" +
" port (\n" +
" PORT_out: out std_logic_vector ((bitCount-1) downto 0);\n" +
" PORT_in: in std_logic_vector ((bitCount-1) downto 0) );\n" +
" PORT_out: out std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_in: in std_logic_vector ((Bits-1) downto 0) );\n" +
"end NOT_GATE_BUS;\n" +
"architecture NOT_GATE_BUS_arch of NOT_GATE_BUS is\n" +
"begin\n" +

34
src/test/java/de/neemann/digital/hdl/vhdl/boards/ClockIntegratorARTIX7Test.java
View File

@ -36,14 +36,14 @@ public class ClockIntegratorARTIX7Test extends TestCase {
" PORT_in: in std_logic );\n" +
" end component;\n" +
" component DIG_MMCME2_BASE\n" +
" generic (\n" +
" D_PARAM : integer;\n" +
" M_PARAM : real;\n" +
" DIV_PARAM : real;\n" +
" PERIOD_PARAM: real);\n" +
" port (\n" +
" PORT_in: in std_logic;\n" +
" PORT_out: out std_logic );\n" +
" generic (\n" +
" D_PARAM : integer;\n" +
" M_PARAM : real;\n" +
" DIV_PARAM : real;\n" +
" PERIOD_PARAM: real);\n" +
" port (\n" +
" PORT_in: in std_logic;\n" +
" PORT_out: out std_logic );\n" +
" end component;\n" +
" signal S0: std_logic;\n" +
" signal S1: std_logic;\n" +
@ -156,15 +156,15 @@ public class ClockIntegratorARTIX7Test extends TestCase {
" PORT_in: in std_logic );\n" +
" end component;\n" +
" component DIG_MMCME2_BASE\n" +
" generic (\n" +
" D_PARAM : integer;\n" +
" M_PARAM : real;\n" +
" DIV_PARAM : integer;\n" +
" DIV4_PARAM : integer;\n" +
" PERIOD_PARAM: real);\n" +
" port (\n" +
" PORT_in: in std_logic;\n" +
" PORT_out: out std_logic );\n" +
" generic (\n" +
" D_PARAM : integer;\n" +
" M_PARAM : real;\n" +
" DIV_PARAM : integer;\n" +
" DIV4_PARAM : integer;\n" +
" PERIOD_PARAM: real);\n" +
" port (\n" +
" PORT_in: in std_logic;\n" +
" PORT_out: out std_logic );\n" +
" end component;\n" +
" signal S0: std_logic;\n" +
" signal S1: std_logic;\n" +

130
src/test/java/de/neemann/digital/hdl/vhdl/lib/BitSelectorTest.java Normal file
View File

@ -0,0 +1,130 @@
/*
* Copyright (c) 2017 Helmut Neemann
* Use of this source code is governed by the GPL v3 license
* that can be found in the LICENSE file.
*/
package de.neemann.digital.hdl.vhdl.lib;
import de.neemann.digital.core.NodeException;
import de.neemann.digital.draw.elements.PinException;
import de.neemann.digital.draw.library.ElementNotFoundException;
import de.neemann.digital.hdl.vhdl.TestHelper;
import de.neemann.digital.hdl.vhdl.VHDLGenerator;
import de.neemann.digital.integration.ToBreakRunner;
import junit.framework.TestCase;
import java.io.IOException;
public class BitSelectorTest extends TestCase {
public void testSimple() throws IOException, ElementNotFoundException, PinException, NodeException {
ToBreakRunner br = new ToBreakRunner("dig/test/vhdl/BitSelect.dig");
String vhdl = new VHDLGenerator(br.getLibrary()).export(br.getCircuit()).toString();
assertEquals(
"LIBRARY ieee;\n" +
"USE ieee.std_logic_1164.all;\n" +
"USE ieee.numeric_std.all;\n" +
"entity main is\n" +
" port (\n" +
" PORT_A: in std_logic_vector (3 downto 0);\n" +
" PORT_sel: in std_logic_vector (1 downto 0);\n" +
" PORT_Y: out std_logic );\n" +
"end main;\n" +
"architecture main_arch of main is\n" +
" component BIT_SEL_2\n" +
" port (\n" +
" PORT_out: out std_logic;\n" +
" PORT_in: in std_logic_vector (3 downto 0);\n" +
" PORT_sel: in std_logic_vector (1 downto 0) );\n" +
" end component;\n" +
" signal S0: std_logic;\n" +
"begin\n" +
" gate0 : BIT_SEL_2\n" +
" port map (\n" +
" PORT_out => S0,\n" +
" PORT_in => PORT_A,\n" +
" PORT_sel => PORT_sel );\n" +
" PORT_Y <= S0;\n" +
"end main_arch;\n" +
"LIBRARY ieee;\n" +
"USE ieee.std_logic_1164.all;\n" +
"entity BIT_SEL_2 is\n" +
" port (\n" +
" PORT_out: out std_logic;\n" +
" PORT_in: in std_logic_vector (3 downto 0);\n" +
" PORT_sel: in std_logic_vector (1 downto 0) );\n" +
"end BIT_SEL_2;\n" +
"architecture BIT_SEL_2_arch of BIT_SEL_2 is\n" +
"begin\n" +
" with PORT_sel select\n" +
" PORT_out <=\n" +
" PORT_in(0) when \"00\",\n" +
" PORT_in(1) when \"01\",\n" +
" PORT_in(2) when \"10\",\n" +
" PORT_in(3) when \"11\",\n" +
" '0' when others;\n" +
"end BIT_SEL_2_arch;", TestHelper.removeCommentLines(vhdl));
}
public void testSimple2() throws IOException, ElementNotFoundException, PinException, NodeException {
ToBreakRunner br = new ToBreakRunner("dig/test/vhdl/BitSelect2.dig");
String vhdl = new VHDLGenerator(br.getLibrary()).export(br.getCircuit()).toString();
assertEquals(
"LIBRARY ieee;\n" +
"USE ieee.std_logic_1164.all;\n" +
"USE ieee.numeric_std.all;\n" +
"entity main is\n" +
" port (\n" +
" PORT_A: in std_logic_vector (15 downto 0);\n" +
" PORT_sel: in std_logic_vector (3 downto 0);\n" +
" PORT_Y: out std_logic );\n" +
"end main;\n" +
"architecture main_arch of main is\n" +
" component BIT_SEL_4\n" +
" port (\n" +
" PORT_out: out std_logic;\n" +
" PORT_in: in std_logic_vector (15 downto 0);\n" +
" PORT_sel: in std_logic_vector (3 downto 0) );\n" +
" end component;\n" +
" signal S0: std_logic;\n" +
"begin\n" +
" gate0 : BIT_SEL_4\n" +
" port map (\n" +
" PORT_out => S0,\n" +
" PORT_in => PORT_A,\n" +
" PORT_sel => PORT_sel );\n" +
" PORT_Y <= S0;\n" +
"end main_arch;\n" +
"LIBRARY ieee;\n" +
"USE ieee.std_logic_1164.all;\n" +
"entity BIT_SEL_4 is\n" +
" port (\n" +
" PORT_out: out std_logic;\n" +
" PORT_in: in std_logic_vector (15 downto 0);\n" +
" PORT_sel: in std_logic_vector (3 downto 0) );\n" +
"end BIT_SEL_4;\n" +
"architecture BIT_SEL_4_arch of BIT_SEL_4 is\n" +
"begin\n" +
" with PORT_sel select\n" +
" PORT_out <=\n" +
" PORT_in(0) when \"0000\",\n" +
" PORT_in(1) when \"0001\",\n" +
" PORT_in(2) when \"0010\",\n" +
" PORT_in(3) when \"0011\",\n" +
" PORT_in(4) when \"0100\",\n" +
" PORT_in(5) when \"0101\",\n" +
" PORT_in(6) when \"0110\",\n" +
" PORT_in(7) when \"0111\",\n" +
" PORT_in(8) when \"1000\",\n" +
" PORT_in(9) when \"1001\",\n" +
" PORT_in(10) when \"1010\",\n" +
" PORT_in(11) when \"1011\",\n" +
" PORT_in(12) when \"1100\",\n" +
" PORT_in(13) when \"1101\",\n" +
" PORT_in(14) when \"1110\",\n" +
" PORT_in(15) when \"1111\",\n" +
" '0' when others;\n" +
"end BIT_SEL_4_arch;", TestHelper.removeCommentLines(vhdl));
}
}

24
src/test/java/de/neemann/digital/hdl/vhdl/lib/DecoderVHDLTest.java
View File

@ -30,7 +30,7 @@ public class DecoderVHDLTest extends TestCase {
" PORT_B: out std_logic );\n" +
"end main;\n" +
"architecture main_arch of main is\n" +
" component MUX_GATE_1\n" +
" component DECODER_1\n" +
" port (\n" +
" PORT_out_0: out std_logic;\n" +
" PORT_out_1: out std_logic;\n" +
@ -39,7 +39,7 @@ public class DecoderVHDLTest extends TestCase {
" signal S0: std_logic;\n" +
" signal S1: std_logic;\n" +
"begin\n" +
" gate0 : MUX_GATE_1\n" +
" gate0 : DECODER_1\n" +
" port map (\n" +
" PORT_out_0 => S0,\n" +
" PORT_out_1 => S1,\n" +
@ -49,17 +49,17 @@ public class DecoderVHDLTest extends TestCase {
"end main_arch;\n" +
"LIBRARY ieee;\n" +
"USE ieee.std_logic_1164.all;\n" +
"entity MUX_GATE_1 is\n" +
"entity DECODER_1 is\n" +
" port (\n" +
" PORT_out_0: out std_logic;\n" +
" PORT_out_1: out std_logic;\n" +
" PORT_sel: in std_logic );\n" +
"end MUX_GATE_1;\n" +
"architecture MUX_GATE_1_arch of MUX_GATE_1 is\n" +
"end DECODER_1;\n" +
"architecture DECODER_1_arch of DECODER_1 is\n" +
"begin\n" +
" PORT_out_0 <= '1' when PORT_sel = '0' else '0';\n" +
" PORT_out_1 <= '1' when PORT_sel = '1' else '0';\n" +
"end MUX_GATE_1_arch;", TestHelper.removeCommentLines(vhdl));
"end DECODER_1_arch;", TestHelper.removeCommentLines(vhdl));
}
public void testSimple2() throws IOException, ElementNotFoundException, PinException, NodeException {
@ -77,7 +77,7 @@ public class DecoderVHDLTest extends TestCase {
" PORT_D: out std_logic );\n" +
"end main;\n" +
"architecture main_arch of main is\n" +
" component MUX_GATE_2\n" +
" component DECODER_2\n" +
" port (\n" +
" PORT_out_0: out std_logic;\n" +
" PORT_out_1: out std_logic;\n" +
@ -90,7 +90,7 @@ public class DecoderVHDLTest extends TestCase {
" signal S2: std_logic;\n" +
" signal S3: std_logic;\n" +
"begin\n" +
" gate0 : MUX_GATE_2\n" +
" gate0 : DECODER_2\n" +
" port map (\n" +
" PORT_out_0 => S0,\n" +
" PORT_out_1 => S1,\n" +
@ -104,21 +104,21 @@ public class DecoderVHDLTest extends TestCase {
"end main_arch;\n" +
"LIBRARY ieee;\n" +
"USE ieee.std_logic_1164.all;\n" +
"entity MUX_GATE_2 is\n" +
"entity DECODER_2 is\n" +
" port (\n" +
" PORT_out_0: out std_logic;\n" +
" PORT_out_1: out std_logic;\n" +
" PORT_out_2: out std_logic;\n" +
" PORT_out_3: out std_logic;\n" +
" PORT_sel: in std_logic_vector (1 downto 0) );\n" +
"end MUX_GATE_2;\n" +
"architecture MUX_GATE_2_arch of MUX_GATE_2 is\n" +
"end DECODER_2;\n" +
"architecture DECODER_2_arch of DECODER_2 is\n" +
"begin\n" +
" PORT_out_0 <= '1' when PORT_sel = \"00\" else '0';\n" +
" PORT_out_1 <= '1' when PORT_sel = \"01\" else '0';\n" +
" PORT_out_2 <= '1' when PORT_sel = \"10\" else '0';\n" +
" PORT_out_3 <= '1' when PORT_sel = \"11\" else '0';\n" +
"end MUX_GATE_2_arch;", TestHelper.removeCommentLines(vhdl));
"end DECODER_2_arch;", TestHelper.removeCommentLines(vhdl));
}

46
src/test/java/de/neemann/digital/hdl/vhdl/lib/DemultiplexerTest.java
View File

@ -81,18 +81,19 @@ public class DemultiplexerTest extends TestCase {
"end main;\n" +
"architecture main_arch of main is\n" +
" component DEMUX_GATE_BUS_1\n" +
" generic ( bitCount : integer );\n" +
" generic ( Bits : integer );\n" +
" port (\n" +
" PORT_out_0: out std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_out_1: out std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_sel: in std_logic;\n" +
" PORT_in: in std_logic_vector ( (bitCount-1) downto 0);\n" +
" PORT_out_0: out std_logic_vector ( (bitCount-1) downto 0);\n" +
" PORT_out_1: out std_logic_vector ( (bitCount-1) downto 0) );\n" +
" PORT_in: in std_logic_vector ((Bits-1) downto 0) );\n" +
" end component;\n" +
" signal S0: std_logic_vector (7 downto 0);\n" +
" signal S1: std_logic_vector (7 downto 0);\n" +
"begin\n" +
" gate0 : DEMUX_GATE_BUS_1\n" +
" generic map ( bitCount => 8)\n" +
" generic map (\n" +
" Bits => 8)\n" +
" port map (\n" +
" PORT_out_0 => S0,\n" +
" PORT_out_1 => S1,\n" +
@ -104,12 +105,12 @@ public class DemultiplexerTest extends TestCase {
"LIBRARY ieee;\n" +
"USE ieee.std_logic_1164.all;\n" +
"entity DEMUX_GATE_BUS_1 is\n" +
" generic ( bitCount : integer );\n" +
" generic ( Bits : integer );\n" +
" port (\n" +
" PORT_out_0: out std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_out_1: out std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_sel: in std_logic;\n" +
" PORT_in: in std_logic_vector ( (bitCount-1) downto 0);\n" +
" PORT_out_0: out std_logic_vector ( (bitCount-1) downto 0);\n" +
" PORT_out_1: out std_logic_vector ( (bitCount-1) downto 0) );\n" +
" PORT_in: in std_logic_vector ((Bits-1) downto 0) );\n" +
"end DEMUX_GATE_BUS_1;\n" +
"architecture DEMUX_GATE_BUS_1_arch of DEMUX_GATE_BUS_1 is\n" +
"begin\n" +
@ -135,14 +136,14 @@ public class DemultiplexerTest extends TestCase {
"end main;\n" +
"architecture main_arch of main is\n" +
" component DEMUX_GATE_BUS_2\n" +
" generic ( bitCount : integer );\n" +
" generic ( Bits : integer );\n" +
" port (\n" +
" PORT_out_0: out std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_out_1: out std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_out_2: out std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_out_3: out std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_sel: in std_logic_vector (1 downto 0);\n" +
" PORT_in: in std_logic_vector ( (bitCount-1) downto 0);\n" +
" PORT_out_0: out std_logic_vector ( (bitCount-1) downto 0);\n" +
" PORT_out_1: out std_logic_vector ( (bitCount-1) downto 0);\n" +
" PORT_out_2: out std_logic_vector ( (bitCount-1) downto 0);\n" +
" PORT_out_3: out std_logic_vector ( (bitCount-1) downto 0) );\n" +
" PORT_in: in std_logic_vector ((Bits-1) downto 0) );\n" +
" end component;\n" +
" signal S0: std_logic_vector (7 downto 0);\n" +
" signal S1: std_logic_vector (7 downto 0);\n" +
@ -150,7 +151,8 @@ public class DemultiplexerTest extends TestCase {
" signal S3: std_logic_vector (7 downto 0);\n" +
"begin\n" +
" gate0 : DEMUX_GATE_BUS_2\n" +
" generic map ( bitCount => 8)\n" +
" generic map (\n" +
" Bits => 8)\n" +
" port map (\n" +
" PORT_out_0 => S0,\n" +
" PORT_out_1 => S1,\n" +
@ -166,14 +168,14 @@ public class DemultiplexerTest extends TestCase {
"LIBRARY ieee;\n" +
"USE ieee.std_logic_1164.all;\n" +
"entity DEMUX_GATE_BUS_2 is\n" +
" generic ( bitCount : integer );\n" +
" generic ( Bits : integer );\n" +
" port (\n" +
" PORT_out_0: out std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_out_1: out std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_out_2: out std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_out_3: out std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_sel: in std_logic_vector (1 downto 0);\n" +
" PORT_in: in std_logic_vector ( (bitCount-1) downto 0);\n" +
" PORT_out_0: out std_logic_vector ( (bitCount-1) downto 0);\n" +
" PORT_out_1: out std_logic_vector ( (bitCount-1) downto 0);\n" +
" PORT_out_2: out std_logic_vector ( (bitCount-1) downto 0);\n" +
" PORT_out_3: out std_logic_vector ( (bitCount-1) downto 0) );\n" +
" PORT_in: in std_logic_vector ((Bits-1) downto 0) );\n" +
"end DEMUX_GATE_BUS_2;\n" +
"architecture DEMUX_GATE_BUS_2_arch of DEMUX_GATE_BUS_2 is\n" +
"begin\n" +

102
src/test/java/de/neemann/digital/hdl/vhdl/lib/PriorityEncoderTest.java Normal file
View File

@ -0,0 +1,102 @@
/*
* Copyright (c) 2017 Helmut Neemann
* Use of this source code is governed by the GPL v3 license
* that can be found in the LICENSE file.
*/
package de.neemann.digital.hdl.vhdl.lib;
import de.neemann.digital.core.NodeException;
import de.neemann.digital.draw.elements.PinException;
import de.neemann.digital.draw.library.ElementNotFoundException;
import de.neemann.digital.hdl.vhdl.TestHelper;
import de.neemann.digital.hdl.vhdl.VHDLGenerator;
import de.neemann.digital.integration.ToBreakRunner;
import junit.framework.TestCase;
import java.io.IOException;
public class PriorityEncoderTest extends TestCase {
public void testSimple() throws IOException, ElementNotFoundException, PinException, NodeException {
ToBreakRunner br = new ToBreakRunner("dig/test/vhdl/priorityEncoder.dig");
String vhdl = new VHDLGenerator(br.getLibrary()).export(br.getCircuit()).toString();
assertEquals(
"LIBRARY ieee;\n" +
"USE ieee.std_logic_1164.all;\n" +
"USE ieee.numeric_std.all;\n" +
"entity main is\n" +
" port (\n" +
" PORT_A0: in std_logic;\n" +
" PORT_A1: in std_logic;\n" +
" PORT_A2: in std_logic;\n" +
" PORT_A3: in std_logic;\n" +
" PORT_A4: in std_logic;\n" +
" PORT_A5: in std_logic;\n" +
" PORT_A6: in std_logic;\n" +
" PORT_A7: in std_logic;\n" +
" PORT_any: out std_logic;\n" +
" PORT_num: out std_logic_vector (2 downto 0) );\n" +
"end main;\n" +
"architecture main_arch of main is\n" +
" component PRIORITY_GATE_3\n" +
" port (\n" +
" PORT_num: out std_logic_vector (2 downto 0);\n" +
" PORT_any: out std_logic;\n" +
" PORT_in0: in std_logic;\n" +
" PORT_in1: in std_logic;\n" +
" PORT_in2: in std_logic;\n" +
" PORT_in3: in std_logic;\n" +
" PORT_in4: in std_logic;\n" +
" PORT_in5: in std_logic;\n" +
" PORT_in6: in std_logic;\n" +
" PORT_in7: in std_logic );\n" +
" end component;\n" +
" signal S0: std_logic;\n" +
" signal S1: std_logic_vector (2 downto 0);\n" +
"begin\n" +
" gate0 : PRIORITY_GATE_3\n" +
" port map (\n" +
" PORT_num => S1,\n" +
" PORT_any => S0,\n" +
" PORT_in0 => PORT_A0,\n" +
" PORT_in1 => PORT_A1,\n" +
" PORT_in2 => PORT_A2,\n" +
" PORT_in3 => PORT_A3,\n" +
" PORT_in4 => PORT_A4,\n" +
" PORT_in5 => PORT_A5,\n" +
" PORT_in6 => PORT_A6,\n" +
" PORT_in7 => PORT_A7 );\n" +
" PORT_any <= S0;\n" +
" PORT_num <= S1;\n" +
"end main_arch;\n" +
"LIBRARY ieee;\n" +
"USE ieee.std_logic_1164.all;\n" +
"entity PRIORITY_GATE_3 is\n" +
" port (\n" +
" PORT_num: out std_logic_vector (2 downto 0);\n" +
" PORT_any: out std_logic;\n" +
" PORT_in0: in std_logic;\n" +
" PORT_in1: in std_logic;\n" +
" PORT_in2: in std_logic;\n" +
" PORT_in3: in std_logic;\n" +
" PORT_in4: in std_logic;\n" +
" PORT_in5: in std_logic;\n" +
" PORT_in6: in std_logic;\n" +
" PORT_in7: in std_logic );\n" +
"end PRIORITY_GATE_3;\n" +
"architecture PRIORITY_GATE_3_arch of PRIORITY_GATE_3 is\n" +
"begin\n" +
" PORT_num <=\n" +
" \"111\" when PORT_in7 = '1' else\n" +
" \"110\" when PORT_in6 = '1' else\n" +
" \"101\" when PORT_in5 = '1' else\n" +
" \"100\" when PORT_in4 = '1' else\n" +
" \"011\" when PORT_in3 = '1' else\n" +
" \"010\" when PORT_in2 = '1' else\n" +
" \"001\" when PORT_in1 = '1' else\n" +
" \"000\" ;\n" +
" PORT_any <= PORT_in0 OR PORT_in1 OR PORT_in2 OR PORT_in3 OR PORT_in4 OR PORT_in5 OR PORT_in6 OR PORT_in7;\n" +
"end PRIORITY_GATE_3_arch;", TestHelper.removeCommentLines(vhdl));
}
}

15
src/test/java/de/neemann/digital/hdl/vhdl/lib/SplitterTest.java
View File

@ -94,10 +94,10 @@ public class SplitterTest extends TestCase {
"end main;\n" +
"architecture main_arch of main is\n" +
" component NOT_GATE_BUS\n" +
" generic ( bitCount : integer );\n" +
" generic ( Bits : integer );\n" +
" port (\n" +
" PORT_out: out std_logic_vector ((bitCount-1) downto 0);\n" +
" PORT_in: in std_logic_vector ((bitCount-1) downto 0) );\n" +
" PORT_out: out std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_in: in std_logic_vector ((Bits-1) downto 0) );\n" +
" end component;\n" +
" signal S0: std_logic_vector (7 downto 0);\n" +
" signal S1: std_logic_vector (7 downto 0);\n" +
@ -107,7 +107,8 @@ public class SplitterTest extends TestCase {
" S2(7 downto 4) <= PORT_B;\n" +
" S0 <= S2(7 downto 0);\n" +
" gate0 : NOT_GATE_BUS\n" +
" generic map ( bitCount => 8)\n" +
" generic map (\n" +
" Bits => 8)\n" +
" port map (\n" +
" PORT_out => S1,\n" +
" PORT_in => S0 );\n" +
@ -117,10 +118,10 @@ public class SplitterTest extends TestCase {
"LIBRARY ieee;\n" +
"USE ieee.std_logic_1164.all;\n" +
"entity NOT_GATE_BUS is\n" +
" generic ( bitCount : integer );\n" +
" generic ( Bits : integer );\n" +
" port (\n" +
" PORT_out: out std_logic_vector ((bitCount-1) downto 0);\n" +
" PORT_in: in std_logic_vector ((bitCount-1) downto 0) );\n" +
" PORT_out: out std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_in: in std_logic_vector ((Bits-1) downto 0) );\n" +
"end NOT_GATE_BUS;\n" +
"architecture NOT_GATE_BUS_arch of NOT_GATE_BUS is\n" +
"begin\n" +

22
src/test/java/de/neemann/digital/hdl/vhdl/lib/VHDLFileTest.java
View File

@ -35,18 +35,18 @@ public class VHDLFileTest extends TestCase {
"end main;\n" +
"architecture main_arch of main is\n" +
" component DIG_D_FF\n" +
" port ( PORT_D : in std_logic;\n" +
" PORT_C : in std_logic;\n" +
" PORT_Q : out std_logic;\n" +
" PORT_notQ : out std_logic );\n" +
" end component;\n" +
" port ( PORT_D : in std_logic;\n" +
" PORT_C : in std_logic;\n" +
" PORT_Q : out std_logic;\n" +
" PORT_notQ : out std_logic );\n" +
" end component;\n" +
" component DIG_D_FF_BUS\n" +
" generic ( Bits: integer ); \n" +
" port ( PORT_D : in std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_C : in std_logic;\n" +
" PORT_Q : out std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_notQ : out std_logic_vector ((Bits-1) downto 0) );\n" +
" end component;\n" +
" generic ( Bits: integer ); \n" +
" port ( PORT_D : in std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_C : in std_logic;\n" +
" PORT_Q : out std_logic_vector ((Bits-1) downto 0);\n" +
" PORT_notQ : out std_logic_vector ((Bits-1) downto 0) );\n" +
" end component;\n" +
" signal S0: std_logic;\n" +
" signal S1: std_logic;\n" +
" signal S2: std_logic_vector (2 downto 0);\n" +

89
src/test/resources/dig/test/vhdl/BitSelect2.dig Normal file
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@ -0,0 +1,89 @@
<?xml version="1.0" encoding="utf-8"?>
<circuit>
<version>1</version>
<attributes/>
<visualElements>
<visualElement>
<elementName>BitSelector</elementName>
<elementAttributes>
<entry>
<string>Selector Bits</string>
<int>4</int>
</entry>
</elementAttributes>
<pos x="380" y="180"/>
</visualElement>
<visualElement>
<elementName>In</elementName>
<elementAttributes>
<entry>
<string>Label</string>
<string>A</string>
</entry>
<entry>
<string>Bits</string>
<int>16</int>
</entry>
</elementAttributes>
<pos x="340" y="180"/>
</visualElement>
<visualElement>
<elementName>In</elementName>
<elementAttributes>
<entry>
<string>Label</string>
<string>sel</string>
</entry>
<entry>
<string>Bits</string>
<int>4</int>
</entry>
</elementAttributes>
<pos x="340" y="220"/>
</visualElement>
<visualElement>
<elementName>Out</elementName>
<elementAttributes>
<entry>
<string>Label</string>
<string>Y</string>
</entry>
</elementAttributes>
<pos x="460" y="180"/>
</visualElement>
<visualElement>
<elementName>Testcase</elementName>
<elementAttributes>
<entry>
<string>Testdata</string>
<testData>
<dataString>A sel Y
loop (n,16)
0 (n) 0
(1&lt;&lt;n) (n) 1
end loop</dataString>
</testData>
</entry>
</elementAttributes>
<pos x="360" y="240"/>
</visualElement>
</visualElements>
<wires>
<wire>
<p1 x="340" y="180"/>
<p2 x="380" y="180"/>
</wire>
<wire>
<p1 x="420" y="180"/>
<p2 x="460" y="180"/>
</wire>
<wire>
<p1 x="340" y="220"/>
<p2 x="400" y="220"/>
</wire>
<wire>
<p1 x="400" y="200"/>
<p2 x="400" y="220"/>
</wire>
</wires>
</circuit>