diff --git a/src/main/dig/test/JK-MS.dig b/src/main/dig/test/JK-MS.dig
index a4b97e1ed..57a216eb3 100644
--- a/src/main/dig/test/JK-MS.dig
+++ b/src/main/dig/test/JK-MS.dig
@@ -144,7 +144,7 @@
           </testData>
         </entry>
       </elementAttributes>
-      <pos x="280" y="420"/>
+      <pos x="600" y="300"/>
     </visualElement>
   </visualElements>
   <wires>
diff --git a/src/main/resources/lang/lang_en.xml b/src/main/resources/lang/lang_en.xml
index e2ef56305..a47ffba7d 100644
--- a/src/main/resources/lang/lang_en.xml
+++ b/src/main/resources/lang/lang_en.xml
@@ -249,7 +249,7 @@ To analyse you can run the circuit in single gate step mode.</string>
     <string name="lib_wires">Wires</string>
     <string name="lib_test">Test</string>
     <string name="menu_about">About</string>
-    <string name="menu_analyse">Analyse</string>
+    <string name="menu_analyse">Analysis</string>
     <string name="menu_analyse_tt">Analyses the actual circuit</string>
     <string name="menu_copy">Copy</string>
     <string name="menu_custom">Custom</string>