diff --git a/src/main/dig/processor/ProcessorMux.dig b/src/main/dig/processor/ProcessorMux.dig
index abc74f290..27cfe3b8d 100644
--- a/src/main/dig/processor/ProcessorMux.dig
+++ b/src/main/dig/processor/ProcessorMux.dig
@@ -542,11 +542,6 @@ Single-Cycle CPU.}}
-
- RegisterOpt.dig
-
-
-
Out
@@ -928,6 +923,11 @@ Single-Cycle CPU.}}
+
+ Register.dig
+
+
+
diff --git a/src/main/dig/processor/ProcessorTest.dig b/src/main/dig/processor/ProcessorTest.dig
new file mode 100644
index 000000000..a85a42f9f
--- /dev/null
+++ b/src/main/dig/processor/ProcessorTest.dig
@@ -0,0 +1,780 @@
+
+
+ 1
+
+
+
+ Clock
+
+
+ runRealTime
+ true
+
+
+ Label
+ Clk
+
+
+ Frequency
+ 200
+
+
+
+
+
+ Processor.dig
+
+
+
+
+ Testcase
+
+
+ Label
+ MOV
+
+
+ Testdata
+
+ # auto generated, do not modify
+Clk R1 R2
+init R1=3;
+init R2=4;
+# mov r2,r1
+program(0x121)
+C X X
+0 3 3
+# R1=3
+# R2=3
+
+
+
+
+
+
+
+ Testcase
+
+
+ Label
+ ADD no carry
+
+
+ Testdata
+
+ # auto generated, do not modify
+Clk Carry R2
+init R1=3;
+init R2=4;
+# add r2,r1
+program(0x221)
+C X X
+0 0 7
+# Carry=0
+# R2=7
+
+
+
+
+
+
+
+ Testcase
+
+
+ Label
+ ADD carry
+
+
+ Testdata
+
+ # auto generated, do not modify
+Clk Carry R2
+init R1=-1;
+init R2=-1;
+# add r2,r1
+program(0x221)
+C X X
+0 1 65534
+# Carry=1
+# R2=65534
+
+
+
+
+
+
+
+ Testcase
+
+
+ Label
+ ADC no carry
+
+
+ Testdata
+
+ # auto generated, do not modify
+Clk Carry R2
+init R1=3;
+init R2=4;
+# adc r2,r1
+program(0x321)
+C X X
+0 0 7
+# Carry=0
+# R2=7
+
+
+
+
+
+
+
+ Testcase
+
+
+ Label
+ ADC carry
+
+
+ Testdata
+
+ # auto generated, do not modify
+Clk Carry R2
+init R1=3;
+init R2=4;
+init Carry=1;
+# adc r2,r1
+program(0x321)
+C X X
+0 0 8
+# Carry=0
+# R2=8
+
+
+
+
+
+
+
+ Testcase
+
+
+ Label
+ ADC carry out
+
+
+ Testdata
+
+ # auto generated, do not modify
+Clk Carry R2
+init R1=-1;
+init R2=-1;
+# adc r2,r1
+program(0x321)
+C X X
+0 1 65534
+# Carry=1
+# R2=65534
+
+
+
+
+
+
+
+ Testcase
+
+
+ Label
+ ADDI small
+
+
+ Testdata
+
+ # auto generated, do not modify
+Clk R1
+init R1=3;
+# addi r1,4
+program(0xc14)
+C X
+0 7
+# R1=7
+
+
+
+
+
+
+
+ Testcase
+
+
+ Label
+ ADDI large
+
+
+ Testdata
+
+ # auto generated, do not modify
+Clk R1
+init R1=3;
+# addi r1,20
+program(0x8014,0xb10)
+repeat (2) C X
+0 23
+# R1=23
+
+
+
+
+
+
+
+ Testcase
+
+
+ Label
+ ADCI small
+
+
+ Testdata
+
+ # auto generated, do not modify
+Clk R1
+init R1=3;
+# adci r1,4
+program(0xe14)
+C X
+0 7
+# R1=7
+
+
+
+
+
+
+
+ Testcase
+
+
+ Label
+ ADCI large
+
+
+ Testdata
+
+ # auto generated, do not modify
+Clk R1
+init R1=3;
+# adci r1,20
+program(0x8014,0xd10)
+repeat (2) C X
+0 23
+# R1=23
+
+
+
+
+
+
+
+ Testcase
+
+
+ Label
+ ADCI small, carry
+
+
+ Testdata
+
+ # auto generated, do not modify
+Clk R1
+init R1=3;
+init Carry=1;
+# adci r1,4
+program(0xe14)
+C X
+0 8
+# R1=8
+
+
+
+
+
+
+
+ Testcase
+
+
+ Label
+ ADCI large, carry
+
+
+ Testdata
+
+ # auto generated, do not modify
+Clk R1
+init R1=3;
+init Carry=1;
+# adci r1,20
+program(0x8014,0xd10)
+repeat (2) C X
+0 24
+# R1=24
+
+
+
+
+
+
+
+ Testcase
+
+
+ Label
+ SUB
+
+
+ Testdata
+
+ # auto generated, do not modify
+Clk Carry R2
+init R1=3;
+init R2=4;
+# sub r2,r1
+program(0x421)
+C X X
+0 0 1
+# Carry=0
+# R2=1
+
+
+
+
+
+
+
+ Testcase
+
+
+ Label
+ SUB carry out
+
+
+ Testdata
+
+ # auto generated, do not modify
+Clk Carry R2
+init R1=4;
+init R2=3;
+# sub r2,r1
+program(0x421)
+C X X
+0 1 65535
+# Carry=1
+# R2=65535
+
+
+
+
+
+
+
+ Testcase
+
+
+ Label
+ SBC
+
+
+ Testdata
+
+ # auto generated, do not modify
+Clk Carry R2
+init R1=3;
+init R2=4;
+# sbc r2,r1
+program(0x521)
+C X X
+0 0 1
+# Carry=0
+# R2=1
+
+
+
+
+
+
+
+ Testcase
+
+
+ Label
+ SBC carry in
+
+
+ Testdata
+
+ # auto generated, do not modify
+Clk Carry R2
+init R1=3;
+init R2=5;
+init Carry=1;
+# sbc r2,r1
+program(0x521)
+C X X
+0 0 1
+# Carry=0
+# R2=1
+
+
+
+
+
+
+
+ Testcase
+
+
+ Label
+ SUBI small
+
+
+ Testdata
+
+ # auto generated, do not modify
+Clk R1
+init R1=4;
+# subi r1,2
+program(0x1012)
+C X
+0 2
+# R1=2
+
+
+
+
+
+
+
+ Testcase
+
+
+ Label
+ SUBI large
+
+
+ Testdata
+
+ # auto generated, do not modify
+Clk R1
+init R1=30;
+# subi r1,20
+program(0x8014,0xf10)
+repeat (2) C X
+0 10
+# R1=10
+
+
+
+
+
+
+
+ Testcase
+
+
+ Label
+ SBCI no carry, small
+
+
+ Testdata
+
+ # auto generated, do not modify
+Clk R1
+init R1=6;
+# sbci r1,4
+program(0x1214)
+C X
+0 2
+# R1=2
+
+
+
+
+
+
+
+ Testcase
+
+
+ Label
+ SBCI no carry, large
+
+
+ Testdata
+
+ # auto generated, do not modify
+Clk R1
+init R1=30;
+# sbci r1,20
+program(0x8014,0x1110)
+repeat (2) C X
+0 10
+# R1=10
+
+
+
+
+
+
+
+ Testcase
+
+
+ Label
+ SBCI carry in, small
+
+
+ Testdata
+
+ # auto generated, do not modify
+Clk R1
+init R1=6;
+init Carry=1;
+# sbci r1,4
+program(0x1214)
+C X
+0 1
+# R1=1
+
+
+
+
+
+
+
+ Testcase
+
+
+ Label
+ SBCI carry in, large
+
+
+ Testdata
+
+ # auto generated, do not modify
+Clk R1
+init R1=30;
+init Carry=1;
+# sbci r1,20
+program(0x8014,0x1110)
+repeat (2) C X
+0 9
+# R1=9
+
+
+
+
+
+
+
+ Testcase
+
+
+ Label
+ NOT
+
+
+ Testdata
+
+ # auto generated, do not modify
+Clk R1
+init R1=0;
+# not r1
+program(0x1a10)
+C X
+0 65535
+# R1=65535
+
+
+
+
+
+
+
+ Testcase
+
+
+ Label
+ NEG
+
+
+ Testdata
+
+ # auto generated, do not modify
+Clk R1
+init R1=1;
+# neg r1
+program(0x1310)
+C X
+0 65535
+# R1=65535
+
+
+
+
+
+
+
+ Testcase
+
+
+ Label
+ SWAP
+
+
+ Testdata
+
+ # auto generated, do not modify
+Clk R1
+init R1=4660;
+# swap r1
+# brk
+program(0x2910,0x4400)
+repeat (2) C X
+0 13330
+# R1=13330
+
+
+
+
+
+
+
+ Testcase
+
+
+ Label
+ SWAPN
+
+
+ Testdata
+
+ # auto generated, do not modify
+Clk R1
+init R1=4660;
+# swapn r1
+program(0x2a10)
+C X
+0 8515
+# R1=8515
+
+
+
+
+
+
+
+ Testcase
+
+
+ Label
+ LDI small
+
+
+ Testdata
+
+ # auto generated, do not modify
+Clk R1
+# ldi r1,5
+program(0xa15)
+C X
+0 5
+# R1=5
+
+
+
+
+
+
+
+ Testcase
+
+
+ Label
+ LDI small
+
+
+ Testdata
+
+ # auto generated, do not modify
+Clk R1
+# ldi r1,15
+program(0xa1f)
+C X
+0 15
+# R1=15
+
+
+
+
+
+
+
+ Testcase
+
+
+ Label
+ LDI large
+
+
+ Testdata
+
+ # auto generated, do not modify
+Clk R1
+# ldi r1,16
+program(0x8010,0x910)
+repeat (2) C X
+0 16
+# R1=16
+
+
+
+
+
+
+
+ Testcase
+
+
+ Label
+ LDI large
+
+
+ Testdata
+
+ # auto generated, do not modify
+Clk R1
+# ldi r1,0x8000
+program(0x8000,0x911)
+repeat (2) C X
+0 32768
+# R1=32768
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/src/main/resources/lang/lang_en.xml b/src/main/resources/lang/lang_en.xml
index 28bae2add..831e100f7 100644
--- a/src/main/resources/lang/lang_en.xml
+++ b/src/main/resources/lang/lang_en.xml
@@ -555,6 +555,7 @@
Clock input. A rising edge stores the value at the D pin.
Enable pin. Storing a value works only if this pin is set high.
Returns the stored value.
+
ROM
A non-volatile memory component.
The stored data can be edited in the attributes dialog.
@@ -563,6 +564,18 @@
The selected data word if the sel input is high.
If the input is high, the output is activated. If it is low, the data output is in high Z state.
+ ROM dual port
+ ROM
+ A non-volatile memory component.
+ The stored data can be edited in the attributes dialog.
+
+ This pin defines the address of data word to be output on D1.
+ The selected data word if the s1 input is high.
+ If the input is high, the output D1 is activated. If it is low, the data output is in high Z state.
+ This pin defines the address of data word to be output on D2.
+ The selected data word if the s2 input is high.
+ If the input is high, the output D2 is activated. If it is low, the data output is in high Z state.
+
RAM, separated Ports
RAM
A RAM module with separate inputs for storing and output for reading the stored data.
diff --git a/src/test/java/de/neemann/digital/integration/TestExamples.java b/src/test/java/de/neemann/digital/integration/TestExamples.java
index fe5508d39..5a51a853d 100644
--- a/src/test/java/de/neemann/digital/integration/TestExamples.java
+++ b/src/test/java/de/neemann/digital/integration/TestExamples.java
@@ -39,8 +39,8 @@ public class TestExamples extends TestCase {
*/
public void testDistExamples() throws Exception {
File examples = new File(Resources.getRoot().getParentFile().getParentFile(), "/main/dig");
- assertEquals(302, new FileScanner(this::check).scan(examples));
- assertEquals(203, testCasesInFiles);
+ assertEquals(301, new FileScanner(this::check).scan(examples));
+ assertEquals(233, testCasesInFiles);
}
/**
diff --git a/src/test/resources/dig/backtrack/AllComponents.dig b/src/test/resources/dig/backtrack/AllComponents.dig
index a398569b6..927087c8b 100644
--- a/src/test/resources/dig/backtrack/AllComponents.dig
+++ b/src/test/resources/dig/backtrack/AllComponents.dig
@@ -315,12 +315,12 @@
D_FF
-
+
T_FF
-
+
ROM
@@ -334,7 +334,7 @@
8
-
+
GraphicCard
@@ -352,7 +352,7 @@
8
-
+
Add
@@ -522,7 +522,7 @@
SixteenSeg
-
+
In
@@ -532,7 +532,7 @@
16
-
+
PolarityAwareLED
@@ -612,7 +612,7 @@
VGA
-
+
PinControl
@@ -622,7 +622,7 @@
8
-
+
Tunnel
@@ -636,7 +636,7 @@
zz
-
+
StepperMotorUnipolar
@@ -668,12 +668,22 @@
+
+ ROMDualPort
+
+
+ AddrBits
+ 8
+
+
+ Bits
+ 8
+
+
+
+
-
-
-
-
@@ -683,9 +693,13 @@
-
+
+
+
+
+
@@ -698,14 +712,14 @@
-
-
-
-
+
+
+
+
@@ -714,6 +728,10 @@
+
+
+
+
@@ -742,10 +760,6 @@
-
-
-
-
@@ -762,6 +776,10 @@
+
+
+
+
@@ -782,6 +800,10 @@
+
+
+
+
@@ -790,6 +812,10 @@
+
+
+
+
@@ -799,8 +825,8 @@
-
-
+
+
@@ -811,12 +837,12 @@
-
-
+
+
-
-
+
+
@@ -826,6 +852,10 @@
+
+
+
+
@@ -854,10 +884,26 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
@@ -870,6 +916,10 @@
+
+
+
+
@@ -888,16 +938,12 @@
-
+
-
-
-
-
@@ -918,6 +964,10 @@
+
+
+
+
@@ -926,10 +976,6 @@
-
-
-
-
@@ -986,6 +1032,10 @@
+
+
+
+
@@ -1010,10 +1060,6 @@
-
-
-
-
@@ -1034,29 +1080,21 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
-
-
+
+
+
+
+
+
@@ -1114,10 +1152,6 @@
-
-
-
-
@@ -1134,6 +1168,14 @@
+
+
+
+
+
+
+
+
@@ -1147,25 +1189,13 @@
-
-
+
+
-
-
-
-
-
-
-
-
-
+
-
-
-
-
@@ -1182,10 +1212,6 @@
-
-
-
-
@@ -1226,6 +1252,10 @@
+
+
+
+
@@ -1250,6 +1280,22 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
@@ -1267,8 +1313,8 @@
-
-
+
+
@@ -1282,10 +1328,6 @@
-
-
-
-
@@ -1298,10 +1340,6 @@
-
-
-
-
@@ -1322,10 +1360,6 @@
-
-
-
-
@@ -1334,6 +1368,10 @@
+
+
+
+
@@ -1358,14 +1396,14 @@
-
-
-
-
+
+
+
+
@@ -1374,10 +1412,6 @@
-
-
-
-
@@ -1386,10 +1420,6 @@
-
-
-
-
@@ -1422,10 +1452,18 @@
+
+
+
+
+
+
+
+
@@ -1448,7 +1486,7 @@
-
+
@@ -1458,14 +1496,6 @@
-
-
-
-
-
-
-
-
@@ -1575,8 +1605,8 @@
-
-
+
+
@@ -1591,16 +1621,24 @@
-
-
+
+
-
+
+
+
+
+
-
+
+
+
+
+
@@ -1608,15 +1646,15 @@
-
+
-
-
+
+
-
-
+
+
@@ -1739,8 +1777,8 @@
-
-
+
+
@@ -1771,8 +1809,8 @@
-
-
+
+
@@ -1911,12 +1949,12 @@
-
-
+
+
-
-
+
+
@@ -1943,28 +1981,28 @@
-
-
+
+
-
+
-
-
+
+
-
-
+
+
-
-
+
+
-
-
+
+
@@ -2048,15 +2086,23 @@
-
+
-
-
+
+
-
-
+
+
+
+
+
+
+
+
+
+