From 57228748d4e81d5289cc70e63bcf7536402ee622 Mon Sep 17 00:00:00 2001
From: hneemann <helmut.neemann@arcor.de>
Date: Sat, 24 Mar 2018 18:04:33 +0100
Subject: [PATCH] some cleanup

---
 src/main/resources/vhdl2/DIG_Counter.tem      |  4 +-
 .../resources/vhdl2/DIG_Demultiplexer.tem     |  4 +-
 src/main/resources/vhdl2/DIG_Not.tem          | 23 ----------
 src/main/resources/vhdl2/DIG_Operate.tem      | 46 -------------------
 .../resources/vhdl2/DIG_RAMDualAccess.tem     |  4 +-
 5 files changed, 6 insertions(+), 75 deletions(-)
 delete mode 100644 src/main/resources/vhdl2/DIG_Not.tem
 delete mode 100644 src/main/resources/vhdl2/DIG_Operate.tem

diff --git a/src/main/resources/vhdl2/DIG_Counter.tem b/src/main/resources/vhdl2/DIG_Counter.tem
index a1cdceb3c..248e83ad9 100644
--- a/src/main/resources/vhdl2/DIG_Counter.tem
+++ b/src/main/resources/vhdl2/DIG_Counter.tem
@@ -12,7 +12,7 @@ entity DIG_Counter is
     clr: in std_logic );
 end DIG_Counter;
 
-architecture DIG_Counter_arch of DIG_Counter is
+architecture Behavioral of DIG_Counter is
    signal count : std_logic_vector((Bits-1) downto 0) := (others => '0');
 begin
     process (C, clr, en)
@@ -28,4 +28,4 @@ begin
 
     p_out <= count;
     ovf <= en when count = ((2**Bits)-1) else '0';
-end DIG_Counter_arch;
\ No newline at end of file
+end Behavioral;
\ No newline at end of file
diff --git a/src/main/resources/vhdl2/DIG_Demultiplexer.tem b/src/main/resources/vhdl2/DIG_Demultiplexer.tem
index 849fc8417..4c4795718 100644
--- a/src/main/resources/vhdl2/DIG_Demultiplexer.tem
+++ b/src/main/resources/vhdl2/DIG_Demultiplexer.tem
@@ -20,9 +20,9 @@ entity <?=entityName?> is
     p_in: in <?= vhdl.genericType(elem.Bits)?> );
 end <?=entityName?>;
 
-architecture <?=entityName?>_arch of <?=entityName?> is
+architecture Behavioral of <?=entityName?> is
 begin
 <?- for (i:=0;i<outputs;i++) {?>
     out_<?=i?> <= p_in when sel = <?= vhdl.value(i,elem.'Selector Bits')?> else <?= vhdl.zero(elem.Bits)?>;
 <?- } ?>
-end <?=entityName?>_arch;
+end Behavioral;
diff --git a/src/main/resources/vhdl2/DIG_Not.tem b/src/main/resources/vhdl2/DIG_Not.tem
deleted file mode 100644
index 4050332c7..000000000
--- a/src/main/resources/vhdl2/DIG_Not.tem
+++ /dev/null
@@ -1,23 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-<?
-  if (elem.Bits=1)
-      entityName:="NOT_GATE";
-  else
-      entityName:="NOT_GATE_BUS";
-?>
-
-entity <?=entityName?> is
-  <?vhdl.beginGenericPort();?>
-  <?if (elem.Bits>1) {?>generic ( Bits : integer );<?vhdl.registerGeneric("Bits"); }?>
-  port (
-    PORT_out: out <?=vhdl.genericType(elem.Bits)?>;
-    PORT_in: in <?=vhdl.genericType(elem.Bits)?> );
-<?vhdl.endGenericPort();?>
-end <?=entityName?>;
-
-architecture <?=entityName?>_arch of <?=entityName?> is
-begin
-  PORT_out <=  NOT( PORT_in );
-end <?=entityName?>_arch;
diff --git a/src/main/resources/vhdl2/DIG_Operate.tem b/src/main/resources/vhdl2/DIG_Operate.tem
deleted file mode 100644
index 888b4c1d1..000000000
--- a/src/main/resources/vhdl2/DIG_Operate.tem
+++ /dev/null
@@ -1,46 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-<?
-
-  if (param.inv)
-     entityName:="N"+param.op;
-  else
-     entityName:=param.op;
-
-  if (elem.Bits=1)
-      entityName=entityName+"_GATE_"+elem.Inputs;
-  else
-      entityName=entityName+"_GATE_BUS_"+elem.Inputs;
-
-?>
-entity <?=entityName?> is
-  <?vhdl.beginGenericPort();?>
-  <?if (elem.Bits>1) {?>generic ( Bits : integer );<?vhdl.registerGeneric("Bits"); }?>
-  port (
-    PORT_out: out <?=vhdl.genericType(elem.Bits)?>;
-    <? for (i:=0;i<elem.Inputs;i++) { ?>
-    PORT_In_<?=i+1?>: in <?
-      print(vhdl.genericType(elem.Bits));
-      if (i=elem.Inputs-1) print(" )");
-    ?>;
-    <? } ?>
-<?vhdl.endGenericPort();?>
-end <?=entityName?>;
-architecture <?=entityName?>_arch of <?=entityName?> is
-begin
-  PORT_out <= <?
-
-    if (param.inv)
-        print("NOT (");
-
-    for (i:=0;i<elem.Inputs;i++) {
-        print("PORT_In_",i+1);
-        if (i<elem.Inputs-1)
-            print(" ",param.op," ");
-    }
-
-    if (param.inv)
-        print(" )");
-
-  ?>;
-end <?=entityName?>_arch;
\ No newline at end of file
diff --git a/src/main/resources/vhdl2/DIG_RAMDualAccess.tem b/src/main/resources/vhdl2/DIG_RAMDualAccess.tem
index a42100296..d6bea0297 100644
--- a/src/main/resources/vhdl2/DIG_RAMDualAccess.tem
+++ b/src/main/resources/vhdl2/DIG_RAMDualAccess.tem
@@ -17,7 +17,7 @@ entity DIG_RAMDualAccess is
     n2A: in std_logic_vector ((AddrBits-1) downto 0) );
 end DIG_RAMDualAccess;
 
-architecture DIG_RAMDualAccess_arch of DIG_RAMDualAccess is
+architecture Behavioral of DIG_RAMDualAccess is
     -- CAUTION: uses distributed RAM
     type memoryType is array(0 to (2**AddrBits)-1) of STD_LOGIC_VECTOR((Bits-1) downto 0);
     signal memory : memoryType;
@@ -30,4 +30,4 @@ begin
   end process;
   n1D <= memory(to_integer(unsigned(n1A))) when ld='1' else (others => 'Z');
   n2D <= memory(to_integer(unsigned(n2A)));
-end DIG_RAMDualAccess_arch;
+end Behavioral;