mirror of
https://github.com/hneemann/Digital.git
synced 2025-09-10 05:15:51 -04:00
minor update of the readme, closes #554
This commit is contained in:
parent
9abec7ecdb
commit
632eb16459
@ -45,7 +45,8 @@ These are the main features of Digital:
|
|||||||
and works just fine.
|
and works just fine.
|
||||||
- It is possible to use custom components which are implemented in Java and packed in a jar file.
|
- It is possible to use custom components which are implemented in Java and packed in a jar file.
|
||||||
See this [example](https://github.com/hneemann/digitalCustomComponents) for details.
|
See this [example](https://github.com/hneemann/digitalCustomComponents) for details.
|
||||||
- Simple remote TCP interface which e.g. allows an [assembler IDE](https://github.com/hneemann/Assembler) to control
|
- Simple remote [TCP interface](https://github.com/hneemann/Assembler/blob/master/src/main/java/de/neemann/assembler/gui/RemoteInterface.java)
|
||||||
|
which e.g. allows an [assembler IDE](https://github.com/hneemann/Assembler) to control
|
||||||
the simulator.
|
the simulator.
|
||||||
- Components can be described using VHDL or Verilog. The open source VHDL simulator [ghdl](http://ghdl.free.fr/)
|
- Components can be described using VHDL or Verilog. The open source VHDL simulator [ghdl](http://ghdl.free.fr/)
|
||||||
needs to be installed to simulate a VHDL defined component, and the open source Verilog simulator
|
needs to be installed to simulate a VHDL defined component, and the open source Verilog simulator
|
||||||
|
Loading…
x
Reference in New Issue
Block a user