diff --git a/src/main/dig/lib/74xx/flipflops/74112.dig b/src/main/dig/lib/74xx/flipflops/74112.dig new file mode 100644 index 000000000..40922dd90 --- /dev/null +++ b/src/main/dig/lib/74xx/flipflops/74112.dig @@ -0,0 +1,537 @@ + + + 1 + + + isDIL + true + + + pinCount + 16 + + + Description + Dual J-K negative-edge-triggered flip-flop, clear and preset + + + Width + 5 + + + + + In + + + Label + ~1CK + + + pinNumber + 1 + + + + + + In + + + Label + 1K + + + pinNumber + 2 + + + + + + In + + + Label + 1J + + + pinNumber + 3 + + + + + + In + + + Label + ~1PR + + + pinNumber + 4 + + + + + + In + + + Label + ~1CLR + + + pinNumber + 15 + + + + + + In + + + Label + ~2CLR + + + pinNumber + 14 + + + + + + In + + + Label + ~2CK + + + pinNumber + 13 + + + + + + Text + + + Description + 74112 - Dual J-K negative-edge-triggered flip-flop, clear and preset + + + + + + In + + + Label + 2K + + + pinNumber + 12 + + + + + + In + + + Label + 2J + + + pinNumber + 11 + + + + + + In + + + Label + ~2PR + + + pinNumber + 10 + + + + + + JK_FF_AS + + + inverterConfig + + Set + C + Clr + + + + + + + Testcase + + + Label + 74112 - Flip Flop #1 + + + Testdata + + ~1CLR ~1PR 1J 1K ~1CK 1Q ~1Q +0 1 X X X 0 1 +1 0 X X X 1 0 +0 0 X X X 1 1 +1 1 1 0 C 1 0 +1 1 0 1 C 0 1 + +# Tests for "no change" and "toggle" states +1 1 0 1 C 0 1 +1 1 0 0 C 0 1 +1 1 1 1 C 1 0 +1 1 0 0 C 1 0 +1 1 1 1 C 0 1 + + + + + + + Out + + + Label + 1Q + + + pinNumber + 5 + + + + + + Out + + + Label + ~1Q + + + pinNumber + 6 + + + + + + Out + + + Label + 2Q + + + pinNumber + 9 + + + + + + Out + + + Label + ~2Q + + + pinNumber + 7 + + + + + + Testcase + + + Label + 74112 - Flip Flop #2 + + + Testdata + + ~2CLR ~2PR 2J 2K ~2CK 2Q ~2Q +0 1 X X X 0 1 +1 0 X X X 1 0 +0 0 X X X 1 1 +1 1 1 0 C 1 0 +1 1 0 1 C 0 1 + +# Tests for "no change" and "toggle" states +1 1 0 1 C 0 1 +1 1 0 0 C 0 1 +1 1 1 1 C 1 0 +1 1 0 0 C 1 0 +1 1 1 1 C 0 1 + + + + + + + Or + + + + + And + + + inverterConfig + + In_1 + In_2 + + + + + + + JK_FF_AS + + + inverterConfig + + Set + C + Clr + + + + + + + Or + + + + + And + + + inverterConfig + + In_1 + In_2 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/test/java/de/neemann/digital/integration/TestExamples.java b/src/test/java/de/neemann/digital/integration/TestExamples.java index 330aafede..09ffab848 100644 --- a/src/test/java/de/neemann/digital/integration/TestExamples.java +++ b/src/test/java/de/neemann/digital/integration/TestExamples.java @@ -28,8 +28,8 @@ public class TestExamples extends TestCase { */ public void testDistExamples() throws Exception { File examples = new File(Resources.getRoot().getParentFile().getParentFile(), "/main/dig"); - assertEquals(191, new FileScanner(this::check).scan(examples)); - assertEquals(92, testCasesInFiles); + assertEquals(192, new FileScanner(this::check).scan(examples)); + assertEquals(94, testCasesInFiles); } /**