diff --git a/src/main/java/de/neemann/digital/core/element/Keys.java b/src/main/java/de/neemann/digital/core/element/Keys.java index 775745e7d..e72a68cf4 100644 --- a/src/main/java/de/neemann/digital/core/element/Keys.java +++ b/src/main/java/de/neemann/digital/core/element/Keys.java @@ -21,6 +21,9 @@ import de.neemann.gui.language.Language; import java.awt.*; import java.io.File; +import java.lang.reflect.Field; +import java.lang.reflect.Modifier; +import java.util.HashMap; import java.util.Locale; /** @@ -28,6 +31,37 @@ import java.util.Locale; */ public final class Keys { + private static final class InstanceHolder { + private static final HashMap INSTANCE = createMap(); + + private static HashMap createMap() { + HashMap map = new HashMap<>(); + for (Field k : Keys.class.getDeclaredFields()) { + if (Modifier.isStatic(k.getModifiers()) && Key.class.isAssignableFrom(k.getType())) { + try { + Key key = (Key) k.get(null); + map.put(key.getKey(), key); + } catch (IllegalAccessException e) { + throw new RuntimeException("error accessing the Keys"); + } + } + } + return map; + } + } + + /** + * Returns the key of the given name. + * If key does not exist, nul is returned. + * + * @param name the name of the key + * @return the key or null + */ + public static Key getKeyByName(String name) { + return InstanceHolder.INSTANCE.get(name); + } + + private Keys() { } diff --git a/src/main/java/de/neemann/digital/hdl/hgs/Parser.java b/src/main/java/de/neemann/digital/hdl/hgs/Parser.java index 7ec589684..d569781f9 100644 --- a/src/main/java/de/neemann/digital/hdl/hgs/Parser.java +++ b/src/main/java/de/neemann/digital/hdl/hgs/Parser.java @@ -138,6 +138,7 @@ public class Parser { return c -> ref.set(c, Expression.add(ref.get(c), 1)); } else if (isToken(OPEN)) { ArrayList args = parseArgList(); + expect(SEMICOLON); if (ref instanceof ReferenceToVar) { return findFunctionStatement(((ReferenceToVar) ref).getName(), args); } else diff --git a/src/main/java/de/neemann/digital/hdl/hgs/refs/ReferenceToStruct.java b/src/main/java/de/neemann/digital/hdl/hgs/refs/ReferenceToStruct.java index e0d8c625b..12949fc4e 100644 --- a/src/main/java/de/neemann/digital/hdl/hgs/refs/ReferenceToStruct.java +++ b/src/main/java/de/neemann/digital/hdl/hgs/refs/ReferenceToStruct.java @@ -11,9 +11,6 @@ import de.neemann.digital.core.element.Keys; import de.neemann.digital.hdl.hgs.Context; import de.neemann.digital.hdl.hgs.EvalException; -import java.lang.reflect.Field; -import java.lang.reflect.Modifier; -import java.util.HashMap; import java.util.Map; /** @@ -22,20 +19,6 @@ import java.util.Map; public class ReferenceToStruct implements Reference { private final Reference parent; private final String name; - private static final HashMap KEY_MAP = new HashMap<>(); - - static { - for (Field k : Keys.class.getDeclaredFields()) { - if (Modifier.isStatic(k.getModifiers()) && Key.class.isAssignableFrom(k.getType())) { - try { - Key key = (Key) k.get(null); - KEY_MAP.put(key.getKey(), key); - } catch (IllegalAccessException e) { - throw new RuntimeException("error accessing the Keys"); - } - } - } - } /** * Creates a new struct access @@ -63,7 +46,7 @@ public class ReferenceToStruct implements Reference { if (m instanceof Map) return ((Map) m).get(name); else if (m instanceof ElementAttributes) { - Key key = KEY_MAP.get(name); + Key key = Keys.getKeyByName(name); if (key == null) throw new EvalException("invalid key: " + name); return ((ElementAttributes) m).get(key); diff --git a/src/main/java/de/neemann/digital/hdl/vhdl/lib/VHDLTemplate.java b/src/main/java/de/neemann/digital/hdl/vhdl/lib/VHDLTemplate.java index 9aec77665..6001a4a75 100644 --- a/src/main/java/de/neemann/digital/hdl/vhdl/lib/VHDLTemplate.java +++ b/src/main/java/de/neemann/digital/hdl/vhdl/lib/VHDLTemplate.java @@ -5,6 +5,8 @@ */ package de.neemann.digital.hdl.vhdl.lib; +import de.neemann.digital.core.element.Key; +import de.neemann.digital.core.element.Keys; import de.neemann.digital.hdl.hgs.*; import de.neemann.digital.hdl.hgs.function.FuncAdapter; import de.neemann.digital.hdl.hgs.function.Function; @@ -20,6 +22,7 @@ import java.io.InputStreamReader; import java.io.Reader; import java.util.ArrayList; import java.util.HashMap; +import java.util.List; import static de.neemann.digital.hdl.vhdl.lib.VHDLEntitySimple.writePort; @@ -64,6 +67,21 @@ public class VHDLTemplate implements VHDLEntity { c.setVar("portDecl", portDecl); return null; } + }) + .addFunction("registerGeneric", new Function(1) { + @Override + public Object calcValue(Context c, ArrayList args) throws EvalException { + List generics; + if (c.contains("generics")) + generics = (List) c.getVar("generics"); + else { + generics = new ArrayList<>(); + c.setVar("generics", generics); + } + String name = Expression.toString(args.get(0).value(c)); + generics.add(name); + return null; + } }); statements = p.parse(); staticContext = p.getStaticContext(); @@ -80,7 +98,7 @@ public class VHDLTemplate implements VHDLEntity { public void writeHeader(CodePrinter out, HDLNode node) throws IOException { try { Entity e = getEntity(node); - out.print(e.code); + out.print(e.getCode()); e.setWritten(true); } catch (EvalException e) { throw new IOException("error evaluating the template", e); @@ -126,14 +144,32 @@ public class VHDLTemplate implements VHDLEntity { } @Override - public void writeArchitecture(CodePrinter out, HDLNode node) { + public void writeGenericMap(CodePrinter out, HDLNode node) throws HDLException, IOException { + try { + final Entity e = getEntity(node); + if (e.getGenerics() != null) { + out.println("generic map (").inc(); + Separator semic = new Separator(",\n"); + for (String name : e.getGenerics()) { + Key key = Keys.getKeyByName(name); + if (key != null) { + semic.check(out); + out.print(name).print(" => ").print(node.get(key).toString()); + } else + throw new HDLException("unknown generic key: " + name); + } + out.println(")").dec(); + } + } catch (EvalException e) { + throw new IOException("error evaluating the template", e); + } } @Override - public void writeGenericMap(CodePrinter out, HDLNode node) { - + public void writeArchitecture(CodePrinter out, HDLNode node) { } + @Override public String getDescription(HDLNode node) { return null; @@ -167,6 +203,7 @@ public class VHDLTemplate implements VHDLEntity { private final String code; private final String portDecl; private final String name; + private final List generics; private boolean isWritten = false; private Entity(HDLNode node, String name) throws EvalException { @@ -179,6 +216,10 @@ public class VHDLTemplate implements VHDLEntity { portDecl = c.getVar("portDecl").toString(); else portDecl = null; + if (c.contains("generics")) + generics = (List) c.getVar("generics"); + else + generics = null; } private String getCode() { @@ -200,6 +241,10 @@ public class VHDLTemplate implements VHDLEntity { private String getName() { return name; } + + public List getGenerics() { + return generics; + } } private final static class FunctionType extends FuncAdapter { diff --git a/src/main/resources/vhdl/DIG_Multiplexer.tem b/src/main/resources/vhdl/DIG_Multiplexer.tem index dd1bc9341..dd1b3e0bb 100644 --- a/src/main/resources/vhdl/DIG_Multiplexer.tem +++ b/src/main/resources/vhdl/DIG_Multiplexer.tem @@ -14,18 +14,21 @@ inputs=1< entity is - + + 1) { ?> + generic ( Bits : integer ); + port ( PORT_out: out ; PORT_sel: in ; PORT_in_: in ); - + end ; architecture _arch of is @@ -34,6 +37,10 @@ begin PORT_out <= PORT_in_ when , - - when others; + 1) + print("(others => '0')"); + else + print(value(0, elem.Bits)); + ?> when others; end _arch; diff --git a/src/test/java/de/neemann/digital/hdl/hgs/ParserTest.java b/src/test/java/de/neemann/digital/hdl/hgs/ParserTest.java index 540414e8e..1601687da 100644 --- a/src/test/java/de/neemann/digital/hdl/hgs/ParserTest.java +++ b/src/test/java/de/neemann/digital/hdl/hgs/ParserTest.java @@ -245,7 +245,7 @@ public class ParserTest extends TestCase { public void testFunctionAsStatement() throws IOException, ParserException, EvalException { flag = 0; - Statement s = new Parser("a : in ;") + Statement s = new Parser("a : in ;") .addFunction("type", new FuncAdapter() { @Override protected Object f(long n) { diff --git a/src/test/java/de/neemann/digital/hdl/vhdl/TestHelper.java b/src/test/java/de/neemann/digital/hdl/vhdl/TestHelper.java index 3e1bacf77..6e0d40195 100644 --- a/src/test/java/de/neemann/digital/hdl/vhdl/TestHelper.java +++ b/src/test/java/de/neemann/digital/hdl/vhdl/TestHelper.java @@ -10,6 +10,10 @@ import java.util.StringTokenizer; public class TestHelper { static public String removeCommentLines(String code) { + return removeCommentLines(code, false); + } + + static public String removeCommentLines(String code, boolean normalizeWhiteSpace) { StringBuilder sb = new StringBuilder(); StringTokenizer st = new StringTokenizer(code, "\n"); while (st.hasMoreTokens()) { @@ -18,10 +22,29 @@ public class TestHelper { if (!(testLine.length() == 0 || (testLine.length() >= 2 && testLine.startsWith("--")))) { if (sb.length() > 0) sb.append("\n"); - sb.append(line); + if (normalizeWhiteSpace) + normalizeWhiteSpaces(sb, line); + else + sb.append(line); } } return sb.toString(); } + private static void normalizeWhiteSpaces(StringBuilder sb, String line) { + boolean wasBlank = true; + for (int i = 0; i < line.length(); i++) { + char c = line.charAt(i); + if (c == ' ' || c == '\t') { + wasBlank = true; + } else { + if (wasBlank) { + sb.append(' '); + wasBlank = false; + } + sb.append(c); + } + } + } + } diff --git a/src/test/java/de/neemann/digital/hdl/vhdl/TestInSimulator.java b/src/test/java/de/neemann/digital/hdl/vhdl/TestInSimulator.java index 17f29a20c..b0ef1605d 100644 --- a/src/test/java/de/neemann/digital/hdl/vhdl/TestInSimulator.java +++ b/src/test/java/de/neemann/digital/hdl/vhdl/TestInSimulator.java @@ -126,9 +126,9 @@ public class TestInSimulator extends TestCase { out.close(); runGHDL(vhdlFile, tb.getTestFileWritten()); } + ProcessStarter.removeFolder(dir); } finally { br.close(); - ProcessStarter.removeFolder(dir); } } diff --git a/src/test/java/de/neemann/digital/hdl/vhdl/lib/MultiplexerTest.java b/src/test/java/de/neemann/digital/hdl/vhdl/lib/MultiplexerTest.java index 3e7e3877e..cb1ba86cb 100644 --- a/src/test/java/de/neemann/digital/hdl/vhdl/lib/MultiplexerTest.java +++ b/src/test/java/de/neemann/digital/hdl/vhdl/lib/MultiplexerTest.java @@ -20,174 +20,178 @@ public class MultiplexerTest extends TestCase { public void testSimple() throws IOException, ElementNotFoundException, PinException, NodeException { ToBreakRunner br = new ToBreakRunner("dig/hdl/mux.dig"); String vhdl = new VHDLGenerator(br.getLibrary()).export(br.getCircuit()).toString(); - assertEquals("LIBRARY ieee;\n" + - "USE ieee.std_logic_1164.all;\n" + - "USE ieee.numeric_std.all;\n" + - "entity main is\n" + - " port (\n" + - " PORT_A: in std_logic;\n" + - " PORT_B: in std_logic;\n" + - " PORT_C: out std_logic;\n" + - " PORT_Sel: in std_logic );\n" + - "end main;\n" + - "architecture main_arch of main is\n" + - " component MUX_GATE_1\n" + - " port (\n" + - " PORT_out: out std_logic;\n" + - " PORT_sel: in std_logic;\n" + - " PORT_in_0: in std_logic;\n" + - " PORT_in_1: in std_logic );\n" + - " end component;\n" + - " signal S0: std_logic;\n" + - "begin\n" + - " gate0 : MUX_GATE_1\n" + - " port map (\n" + - " PORT_out => S0,\n" + - " PORT_sel => PORT_Sel,\n" + - " PORT_in_0 => PORT_A,\n" + - " PORT_in_1 => PORT_B );\n" + - " PORT_C <= S0;\n" + - "end main_arch;\n" + + assertEquals(TestHelper.removeCommentLines( "LIBRARY ieee;\n" + - "USE ieee.std_logic_1164.all;\n" + - "entity MUX_GATE_1 is\n" + - " port (\n" + - " PORT_out: out std_logic;\n" + - " PORT_sel: in std_logic;\n" + - " PORT_in_0: in std_logic;\n" + - " PORT_in_1: in std_logic );\n" + - "end MUX_GATE_1;\n" + - "architecture MUX_GATE_1_arch of MUX_GATE_1 is\n" + - "begin\n" + - " with PORT_sel select\n" + - " PORT_out <=\n" + - " PORT_in_0 when '0',\n" + - " PORT_in_1 when '1',\n" + - " '0' when others;\n" + - "end MUX_GATE_1_arch;", TestHelper.removeCommentLines(vhdl)); + "USE ieee.std_logic_1164.all;\n" + + "USE ieee.numeric_std.all;\n" + + "entity main is\n" + + " port (\n" + + " PORT_A: in std_logic;\n" + + " PORT_B: in std_logic;\n" + + " PORT_C: out std_logic;\n" + + " PORT_Sel: in std_logic );\n" + + "end main;\n" + + "architecture main_arch of main is\n" + + " component MUX_GATE_1\n" + + " port (\n" + + " PORT_out: out std_logic;\n" + + " PORT_sel: in std_logic;\n" + + " PORT_in_0: in std_logic;\n" + + " PORT_in_1: in std_logic );\n" + + " end component;\n" + + " signal S0: std_logic;\n" + + "begin\n" + + " gate0 : MUX_GATE_1\n" + + " port map (\n" + + " PORT_out => S0,\n" + + " PORT_sel => PORT_Sel,\n" + + " PORT_in_0 => PORT_A,\n" + + " PORT_in_1 => PORT_B );\n" + + " PORT_C <= S0;\n" + + "end main_arch;\n" + + "LIBRARY ieee;\n" + + "USE ieee.std_logic_1164.all;\n" + + "entity MUX_GATE_1 is\n" + + " port (\n" + + " PORT_out: out std_logic;\n" + + " PORT_sel: in std_logic;\n" + + " PORT_in_0: in std_logic;\n" + + " PORT_in_1: in std_logic );\n" + + "end MUX_GATE_1;\n" + + "architecture MUX_GATE_1_arch of MUX_GATE_1 is\n" + + "begin\n" + + " with PORT_sel select\n" + + " PORT_out <=\n" + + " PORT_in_0 when '0',\n" + + " PORT_in_1 when '1',\n" + + " '0' when others;\n" + + "end MUX_GATE_1_arch;", true), TestHelper.removeCommentLines(vhdl, true)); } public void testSimple2() throws IOException, ElementNotFoundException, PinException, NodeException { ToBreakRunner br = new ToBreakRunner("dig/hdl/mux2.dig"); String vhdl = new VHDLGenerator(br.getLibrary()).export(br.getCircuit()).toString(); - assertEquals("LIBRARY ieee;\n" + - "USE ieee.std_logic_1164.all;\n" + - "USE ieee.numeric_std.all;\n" + - "entity main is\n" + - " port (\n" + - " PORT_A: in std_logic;\n" + - " PORT_B: in std_logic;\n" + - " PORT_Y: out std_logic;\n" + - " PORT_Sel: in std_logic_vector (1 downto 0);\n" + - " PORT_C: in std_logic;\n" + - " PORT_D: in std_logic );\n" + - "end main;\n" + - "architecture main_arch of main is\n" + - " component MUX_GATE_2\n" + - " port (\n" + - " PORT_out: out std_logic;\n" + - " PORT_sel: in std_logic_vector (1 downto 0);\n" + - " PORT_in_0: in std_logic;\n" + - " PORT_in_1: in std_logic;\n" + - " PORT_in_2: in std_logic;\n" + - " PORT_in_3: in std_logic );\n" + - " end component;\n" + - " signal S0: std_logic;\n" + - "begin\n" + - " gate0 : MUX_GATE_2\n" + - " port map (\n" + - " PORT_out => S0,\n" + - " PORT_sel => PORT_Sel,\n" + - " PORT_in_0 => PORT_A,\n" + - " PORT_in_1 => PORT_B,\n" + - " PORT_in_2 => PORT_C,\n" + - " PORT_in_3 => PORT_D );\n" + - " PORT_Y <= S0;\n" + - "end main_arch;\n" + + assertEquals(TestHelper.removeCommentLines( "LIBRARY ieee;\n" + - "USE ieee.std_logic_1164.all;\n" + - "entity MUX_GATE_2 is\n" + - " port (\n" + - " PORT_out: out std_logic;\n" + - " PORT_sel: in std_logic_vector (1 downto 0);\n" + - " PORT_in_0: in std_logic;\n" + - " PORT_in_1: in std_logic;\n" + - " PORT_in_2: in std_logic;\n" + - " PORT_in_3: in std_logic );\n" + - "end MUX_GATE_2;\n" + - "architecture MUX_GATE_2_arch of MUX_GATE_2 is\n" + - "begin\n" + - " with PORT_sel select\n" + - " PORT_out <=\n" + - " PORT_in_0 when \"00\",\n" + - " PORT_in_1 when \"01\",\n" + - " PORT_in_2 when \"10\",\n" + - " PORT_in_3 when \"11\",\n" + - " '0' when others;\n" + - "end MUX_GATE_2_arch;", TestHelper.removeCommentLines(vhdl)); + "USE ieee.std_logic_1164.all;\n" + + "USE ieee.numeric_std.all;\n" + + "entity main is\n" + + " port (\n" + + " PORT_A: in std_logic;\n" + + " PORT_B: in std_logic;\n" + + " PORT_Y: out std_logic;\n" + + " PORT_Sel: in std_logic_vector (1 downto 0);\n" + + " PORT_C: in std_logic;\n" + + " PORT_D: in std_logic );\n" + + "end main;\n" + + "architecture main_arch of main is\n" + + " component MUX_GATE_2\n" + + " port (\n" + + " PORT_out: out std_logic;\n" + + " PORT_sel: in std_logic_vector (1 downto 0);\n" + + " PORT_in_0: in std_logic;\n" + + " PORT_in_1: in std_logic;\n" + + " PORT_in_2: in std_logic;\n" + + " PORT_in_3: in std_logic );\n" + + " end component;\n" + + " signal S0: std_logic;\n" + + "begin\n" + + " gate0 : MUX_GATE_2\n" + + " port map (\n" + + " PORT_out => S0,\n" + + " PORT_sel => PORT_Sel,\n" + + " PORT_in_0 => PORT_A,\n" + + " PORT_in_1 => PORT_B,\n" + + " PORT_in_2 => PORT_C,\n" + + " PORT_in_3 => PORT_D );\n" + + " PORT_Y <= S0;\n" + + "end main_arch;\n" + + "LIBRARY ieee;\n" + + "USE ieee.std_logic_1164.all;\n" + + "entity MUX_GATE_2 is\n" + + " port (\n" + + " PORT_out: out std_logic;\n" + + " PORT_sel: in std_logic_vector (1 downto 0);\n" + + " PORT_in_0: in std_logic;\n" + + " PORT_in_1: in std_logic;\n" + + " PORT_in_2: in std_logic;\n" + + " PORT_in_3: in std_logic );\n" + + "end MUX_GATE_2;\n" + + "architecture MUX_GATE_2_arch of MUX_GATE_2 is\n" + + "begin\n" + + " with PORT_sel select\n" + + " PORT_out <=\n" + + " PORT_in_0 when \"00\",\n" + + " PORT_in_1 when \"01\",\n" + + " PORT_in_2 when \"10\",\n" + + " PORT_in_3 when \"11\",\n" + + " '0' when others;\n" + + "end MUX_GATE_2_arch;", true), TestHelper.removeCommentLines(vhdl, true)); } public void testSimple3() throws IOException, ElementNotFoundException, PinException, NodeException { ToBreakRunner br = new ToBreakRunner("dig/hdl/mux3.dig"); String vhdl = new VHDLGenerator(br.getLibrary()).export(br.getCircuit()).toString(); - assertEquals("LIBRARY ieee;\n" + - "USE ieee.std_logic_1164.all;\n" + - "USE ieee.numeric_std.all;\n" + - "entity main is\n" + - " port (\n" + - " PORT_A: in std_logic_vector (3 downto 0);\n" + - " PORT_B: in std_logic_vector (3 downto 0);\n" + - " PORT_Y: out std_logic_vector (3 downto 0);\n" + - " PORT_Sel: in std_logic_vector (1 downto 0);\n" + - " PORT_C: in std_logic_vector (3 downto 0);\n" + - " PORT_D: in std_logic_vector (3 downto 0) );\n" + - "end main;\n" + - "architecture main_arch of main is\n" + - " component MUX_GATE_BUS_2\n" + - " generic ( bitCount : integer );\n" + - " port (\n" + - " PORT_sel: in std_logic_vector (1 downto 0);\n" + - " PORT_out: out std_logic_vector ( (bitCount-1) downto 0);\n" + - " PORT_in_0: in std_logic_vector ( (bitCount-1) downto 0);\n" + - " PORT_in_1: in std_logic_vector ( (bitCount-1) downto 0);\n" + - " PORT_in_2: in std_logic_vector ( (bitCount-1) downto 0);\n" + - " PORT_in_3: in std_logic_vector ( (bitCount-1) downto 0) );\n" + - " end component;\n" + - " signal S0: std_logic_vector (3 downto 0);\n" + - "begin\n" + - " gate0 : MUX_GATE_BUS_2\n" + - " generic map ( bitCount => 4)\n" + - " port map (\n" + - " PORT_out => S0,\n" + - " PORT_sel => PORT_Sel,\n" + - " PORT_in_0 => PORT_A,\n" + - " PORT_in_1 => PORT_B,\n" + - " PORT_in_2 => PORT_C,\n" + - " PORT_in_3 => PORT_D );\n" + - " PORT_Y <= S0;\n" + - "end main_arch;\n" + + assertEquals(TestHelper.removeCommentLines( "LIBRARY ieee;\n" + - "USE ieee.std_logic_1164.all;\n" + - "entity MUX_GATE_BUS_2 is\n" + - " generic ( bitCount : integer );\n" + - " port (\n" + - " PORT_sel: in std_logic_vector (1 downto 0);\n" + - " PORT_out: out std_logic_vector ( (bitCount-1) downto 0);\n" + - " PORT_in_0: in std_logic_vector ( (bitCount-1) downto 0);\n" + - " PORT_in_1: in std_logic_vector ( (bitCount-1) downto 0);\n" + - " PORT_in_2: in std_logic_vector ( (bitCount-1) downto 0);\n" + - " PORT_in_3: in std_logic_vector ( (bitCount-1) downto 0) );\n" + - "end MUX_GATE_BUS_2;\n" + - "architecture MUX_GATE_BUS_2_arch of MUX_GATE_BUS_2 is\n" + - "begin\n" + - " with PORT_sel select\n" + - " PORT_out <=\n" + - " PORT_in_0 when \"00\",\n" + - " PORT_in_1 when \"01\",\n" + - " PORT_in_2 when \"10\",\n" + - " PORT_in_3 when \"11\",\n" + - " (others => '0') when others;\n" + - "end MUX_GATE_BUS_2_arch;", TestHelper.removeCommentLines(vhdl)); + "USE ieee.std_logic_1164.all;\n" + + "USE ieee.numeric_std.all;\n" + + "entity main is\n" + + " port (\n" + + " PORT_A: in std_logic_vector (3 downto 0);\n" + + " PORT_B: in std_logic_vector (3 downto 0);\n" + + " PORT_Y: out std_logic_vector (3 downto 0);\n" + + " PORT_Sel: in std_logic_vector (1 downto 0);\n" + + " PORT_C: in std_logic_vector (3 downto 0);\n" + + " PORT_D: in std_logic_vector (3 downto 0) );\n" + + "end main;\n" + + "architecture main_arch of main is\n" + + " component MUX_GATE_BUS_2\n" + + " generic ( Bits : integer );\n" + + " port (\n" + + " PORT_out: out std_logic_vector ((Bits-1) downto 0);\n" + + " PORT_sel: in std_logic_vector (1 downto 0);\n" + + " PORT_in_0: in std_logic_vector ((Bits-1) downto 0);\n" + + " PORT_in_1: in std_logic_vector ((Bits-1) downto 0);\n" + + " PORT_in_2: in std_logic_vector ((Bits-1) downto 0);\n" + + " PORT_in_3: in std_logic_vector ((Bits-1) downto 0) );\n" + + " end component;\n" + + " signal S0: std_logic_vector (3 downto 0);\n" + + "begin\n" + + " gate0 : MUX_GATE_BUS_2\n" + + " generic map (\n" + + " Bits => 4)\n" + + " port map (\n" + + " PORT_out => S0,\n" + + " PORT_sel => PORT_Sel,\n" + + " PORT_in_0 => PORT_A,\n" + + " PORT_in_1 => PORT_B,\n" + + " PORT_in_2 => PORT_C,\n" + + " PORT_in_3 => PORT_D );\n" + + " PORT_Y <= S0;\n" + + "end main_arch;\n" + + "LIBRARY ieee;\n" + + "USE ieee.std_logic_1164.all;\n" + + "entity MUX_GATE_BUS_2 is\n" + + " generic ( Bits : integer );\n" + + " port (\n" + + " PORT_out: out std_logic_vector ((Bits-1) downto 0);\n" + + " PORT_sel: in std_logic_vector (1 downto 0);\n" + + " PORT_in_0: in std_logic_vector ((Bits-1) downto 0);\n" + + " PORT_in_1: in std_logic_vector ((Bits-1) downto 0);\n" + + " PORT_in_2: in std_logic_vector ((Bits-1) downto 0);\n" + + " PORT_in_3: in std_logic_vector ((Bits-1) downto 0) );\n" + + "end MUX_GATE_BUS_2;\n" + + "architecture MUX_GATE_BUS_2_arch of MUX_GATE_BUS_2 is\n" + + "begin\n" + + " with PORT_sel select\n" + + " PORT_out <=\n" + + " PORT_in_0 when \"00\",\n" + + " PORT_in_1 when \"01\",\n" + + " PORT_in_2 when \"10\",\n" + + " PORT_in_3 when \"11\",\n" + + " (others => '0') when others;\n" + + "end MUX_GATE_BUS_2_arch;", true), TestHelper.removeCommentLines(vhdl, true)); } }