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improved error message on vhdl naming issues

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hneemann 2018-04-13 18:17:33 +02:00
parent 1031b8ee56
commit 70b0f2e665
4 changed files with 32 additions and 13 deletions
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37
src/main/java/de/neemann/digital/hdl/model2/HDLCircuit.java
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@ -34,6 +34,7 @@ import de.neemann.digital.hdl.printer.CodePrinter;
import de.neemann.digital.lang.Lang; import de.neemann.digital.lang.Lang;
import de.neemann.digital.testing.TestCaseElement; import de.neemann.digital.testing.TestCaseElement;
import java.io.File;
import java.io.IOException; import java.io.IOException;
import java.util.*; import java.util.*;
@ -46,6 +47,7 @@ public class HDLCircuit implements Iterable<HDLNode>, HDLModel.BitProvider, Prin
private final ArrayList<HDLPort> inputs; private final ArrayList<HDLPort> inputs;
private final ArrayList<HDLNet> listOfNets; private final ArrayList<HDLNet> listOfNets;
private final String description; private final String description;
private final File origin;
private ArrayList<HDLPort> ports; private ArrayList<HDLPort> ports;
private NetList netList; private NetList netList;
private ArrayList<HDLNode> nodes; private ArrayList<HDLNode> nodes;
@ -93,6 +95,7 @@ public class HDLCircuit implements Iterable<HDLNode>, HDLModel.BitProvider, Prin
listOfNets = new ArrayList<>(); listOfNets = new ArrayList<>();
netList = new NetList(circuit); netList = new NetList(circuit);
description = circuit.getAttributes().get(Keys.DESCRIPTION); description = circuit.getAttributes().get(Keys.DESCRIPTION);
this.origin = circuit.getOrigin();
ArrayList<ClockInfo> clocks = new ArrayList<>(); ArrayList<ClockInfo> clocks = new ArrayList<>();
@ -410,20 +413,25 @@ public class HDLCircuit implements Iterable<HDLNode>, HDLModel.BitProvider, Prin
* @throws HDLException HDLException * @throws HDLException HDLException
*/ */
public void rename(HDLModel.Renaming renaming) throws HDLException { public void rename(HDLModel.Renaming renaming) throws HDLException {
for (HDLPort p : outputs) try {
p.rename(renaming); for (HDLPort p : outputs)
for (HDLPort p : inputs) p.rename(renaming);
p.rename(renaming); for (HDLPort p : inputs)
for (HDLNet p : listOfNets) p.rename(renaming);
p.rename(renaming); for (HDLNet p : listOfNets)
p.rename(renaming);
for (HDLNode n : nodes) for (HDLNode n : nodes)
n.rename(renaming); n.rename(renaming);
hdlEntityName = renaming.checkName(hdlEntityName); hdlEntityName = renaming.checkName(hdlEntityName);
checkUnique(getPorts()); checkUnique(getPorts());
checkUnique(listOfNets); checkUnique(listOfNets);
} catch (HDLException e) {
e.setOrigin(origin);
throw e;
}
} }
private void checkUnique(Collection<? extends HasName> names) throws HDLException { private void checkUnique(Collection<? extends HasName> names) throws HDLException {
@ -498,7 +506,12 @@ public class HDLCircuit implements Iterable<HDLNode>, HDLModel.BitProvider, Prin
* @throws HDLException HDLException * @throws HDLException HDLException
*/ */
public HDLCircuit apply(Optimization optimization) throws HDLException { public HDLCircuit apply(Optimization optimization) throws HDLException {
optimization.optimize(this); try {
optimization.optimize(this);
} catch (HDLException e) {
e.setOrigin(origin);
throw e;
}
return this; return this;
} }

4
src/main/java/de/neemann/digital/hdl/model2/HDLException.java
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@ -5,10 +5,12 @@
*/ */
package de.neemann.digital.hdl.model2; package de.neemann.digital.hdl.model2;
import de.neemann.digital.core.ExceptionWithOrigin;
/** /**
* Exception thrown during model building * Exception thrown during model building
*/ */
public class HDLException extends Exception { public class HDLException extends ExceptionWithOrigin {
/** /**
* Creates a new instance * Creates a new instance
* *

2
src/main/java/de/neemann/digital/hdl/vhdl2/VHDLRenaming.java
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@ -56,6 +56,8 @@ public class VHDLRenaming implements HDLModel.Renaming {
sb.append(c); sb.append(c);
else { else {
switch (c) { switch (c) {
case '/':
case '!':
case '~': case '~':
case '\u00AC': case '\u00AC':
sb.append("not"); sb.append("not");

2
src/test/java/de/neemann/digital/hdl/vhdl2/VHDLRenamingTest.java
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@ -19,6 +19,8 @@ public class VHDLRenamingTest extends TestCase {
assertEquals("a_o_o", r.checkName("a\"o\"o")); assertEquals("a_o_o", r.checkName("a\"o\"o"));
assertEquals("o", r.checkName("\"o\"")); assertEquals("o", r.checkName("\"o\""));
assertEquals("o", r.checkName("_o_")); assertEquals("o", r.checkName("_o_"));
assertEquals("notQ", r.checkName("/Q"));
assertEquals("notQ", r.checkName("!Q"));
assertEquals("notQ", r.checkName("~Q")); assertEquals("notQ", r.checkName("~Q"));
assertEquals("aleb", r.checkName("a<b")); assertEquals("aleb", r.checkName("a<b"));
assertEquals("agrb", r.checkName("a>b")); assertEquals("agrb", r.checkName("a>b"));