diff --git a/src/main/resources/vhdl2/DIG_D_FF.tem b/src/main/resources/vhdl2/DIG_D_FF.tem
index 943689963..3bb550386 100644
--- a/src/main/resources/vhdl2/DIG_D_FF.tem
+++ b/src/main/resources/vhdl2/DIG_D_FF.tem
@@ -3,11 +3,17 @@ USE ieee.std_logic_1164.all;
entity is
- 1) {?>generic ( Bits: integer );
+ generic (1) {?>
+ Default: integer;
+ Bits: integer );
+ Default: std_logic );
port ( D : in ;
C : in std_logic;
Q : out ;
@@ -15,7 +21,7 @@ entity is
end ;
architecture Behavioral of is
- signal state : := ;
+ signal state : := 1) {?>std_logic_vector(to_unsigned(Default, Bits))Default;
begin
Q <= state;
notQ <= NOT( state );
diff --git a/src/test/java/de/neemann/digital/hdl/verilog2/VerilogSimulatorTest.java b/src/test/java/de/neemann/digital/hdl/verilog2/VerilogSimulatorTest.java
index 671d26790..975599e46 100644
--- a/src/test/java/de/neemann/digital/hdl/verilog2/VerilogSimulatorTest.java
+++ b/src/test/java/de/neemann/digital/hdl/verilog2/VerilogSimulatorTest.java
@@ -45,7 +45,7 @@ public class VerilogSimulatorTest extends TestCase {
File examples = new File(Resources.getRoot(), "/dig/test/vhdl");
try {
int tested = new FileScanner(this::checkVerilogExport).noOutput().scan(examples);
- assertEquals(35, tested);
+ assertEquals(37, tested);
assertEquals(tested+2, testBenches);
} catch (FileScanner.SkipAllException e) {
// if iverilog is not installed its also ok
diff --git a/src/test/java/de/neemann/digital/hdl/vhdl2/ClockTest.java b/src/test/java/de/neemann/digital/hdl/vhdl2/ClockTest.java
index ff32bb019..77be0b284 100644
--- a/src/test/java/de/neemann/digital/hdl/vhdl2/ClockTest.java
+++ b/src/test/java/de/neemann/digital/hdl/vhdl2/ClockTest.java
@@ -66,7 +66,8 @@ public class ClockTest extends TestCase {
"USE ieee.std_logic_1164.all;\n" +
"\n" +
"entity DIG_D_FF is\n" +
- " \n" +
+ " generic (\n" +
+ " Default: std_logic ); \n" +
" port ( D : in std_logic;\n" +
" C : in std_logic;\n" +
" Q : out std_logic;\n" +
@@ -74,7 +75,7 @@ public class ClockTest extends TestCase {
"end DIG_D_FF;\n" +
"\n" +
"architecture Behavioral of DIG_D_FF is\n" +
- " signal state : std_logic := '0';\n" +
+ " signal state : std_logic := Default;\n" +
"begin\n" +
" Q <= state;\n" +
" notQ <= NOT( state );\n" +
@@ -109,6 +110,8 @@ public class ClockTest extends TestCase {
" cin => C,\n" +
" cout => s0);\n" +
" gate1: entity work.DIG_D_FF\n" +
+ " generic map (\n" +
+ " Default => '0')\n" +
" port map (\n" +
" D => A,\n" +
" C => s0,\n" +
@@ -229,7 +232,8 @@ public class ClockTest extends TestCase {
"USE ieee.std_logic_1164.all;\n" +
"\n" +
"entity DIG_D_FF is\n" +
- " \n" +
+ " generic (\n" +
+ " Default: std_logic ); \n" +
" port ( D : in std_logic;\n" +
" C : in std_logic;\n" +
" Q : out std_logic;\n" +
@@ -237,7 +241,7 @@ public class ClockTest extends TestCase {
"end DIG_D_FF;\n" +
"\n" +
"architecture Behavioral of DIG_D_FF is\n" +
- " signal state : std_logic := '0';\n" +
+ " signal state : std_logic := Default;\n" +
"begin\n" +
" Q <= state;\n" +
" notQ <= NOT( state );\n" +
@@ -276,6 +280,8 @@ public class ClockTest extends TestCase {
" cin => C,\n" +
" cout => s0);\n" +
" gate1: entity work.DIG_D_FF\n" +
+ " generic map (\n" +
+ " Default => '0')\n" +
" port map (\n" +
" D => A,\n" +
" C => s0,\n" +
diff --git a/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLGeneratorTest.java b/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLGeneratorTest.java
index 1d09044c8..1bc99015f 100644
--- a/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLGeneratorTest.java
+++ b/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLGeneratorTest.java
@@ -28,7 +28,8 @@ public class VHDLGeneratorTest extends TestCase {
"USE ieee.std_logic_1164.all;\n" +
"\n" +
"entity DIG_D_FF is\n" +
- " \n" +
+ " generic (\n" +
+ " Default: std_logic ); \n" +
" port ( D : in std_logic;\n" +
" C : in std_logic;\n" +
" Q : out std_logic;\n" +
@@ -36,7 +37,7 @@ public class VHDLGeneratorTest extends TestCase {
"end DIG_D_FF;\n" +
"\n" +
"architecture Behavioral of DIG_D_FF is\n" +
- " signal state : std_logic := '0';\n" +
+ " signal state : std_logic := Default;\n" +
"begin\n" +
" Q <= state;\n" +
" notQ <= NOT( state );\n" +
@@ -71,9 +72,11 @@ public class VHDLGeneratorTest extends TestCase {
" signal Z_temp: std_logic;\n" +
"begin\n" +
" Y_temp <= (B OR NOT C);\n" +
- " Z_temp <= NOT A;\n"+
+ " Z_temp <= NOT A;\n" +
" s0 <= ((A OR C) AND (Z_temp OR C) AND '1' AND NOT (B OR C) AND Y_temp);\n" +
" gate0: entity work.DIG_D_FF\n" +
+ " generic map (\n" +
+ " Default => '0')\n" +
" port map (\n" +
" D => s0,\n" +
" C => '1',\n" +
diff --git a/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLSimulatorTest.java b/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLSimulatorTest.java
index f053f3d90..4523eb6eb 100644
--- a/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLSimulatorTest.java
+++ b/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLSimulatorTest.java
@@ -47,7 +47,7 @@ public class VHDLSimulatorTest extends TestCase {
File examples = new File(Resources.getRoot(), "/dig/test/vhdl");
try {
int tested = new FileScanner(this::checkVHDLExport).noOutput().scan(examples);
- assertEquals(35, tested);
+ assertEquals(37, tested);
assertEquals(tested+2, testBenches);
} catch (FileScanner.SkipAllException e) {
// if ghdl is not installed its also ok
diff --git a/src/test/java/de/neemann/digital/integration/TestExamples.java b/src/test/java/de/neemann/digital/integration/TestExamples.java
index e89ca1c65..9e0311838 100644
--- a/src/test/java/de/neemann/digital/integration/TestExamples.java
+++ b/src/test/java/de/neemann/digital/integration/TestExamples.java
@@ -43,8 +43,8 @@ public class TestExamples extends TestCase {
*/
public void testTestExamples() throws Exception {
File examples = new File(Resources.getRoot(), "/dig/test");
- assertEquals(148, new FileScanner(this::check).scan(examples));
- assertEquals(140, testCasesInFiles);
+ assertEquals(150, new FileScanner(this::check).scan(examples));
+ assertEquals(142, testCasesInFiles);
}
/**
diff --git a/src/test/resources/dig/test/vhdl/D-Default.dig b/src/test/resources/dig/test/vhdl/D-Default.dig
new file mode 100644
index 000000000..42ae77f38
--- /dev/null
+++ b/src/test/resources/dig/test/vhdl/D-Default.dig
@@ -0,0 +1,119 @@
+
+
+ 1
+
+
+
+ VDD
+
+
+
+
+ VDD
+
+
+
+
+ In
+
+
+ Label
+ C
+
+
+
+
+
+ Out
+
+
+ Label
+ Q1
+
+
+
+
+
+ Out
+
+
+ Label
+ Q2
+
+
+
+
+
+ Testcase
+
+
+ Testdata
+
+ C Q1 Q2
+0 0 1
+C 1 1
+
+
+
+
+
+
+
+ D_FF
+
+
+
+
+ D_FF
+
+
+ Default
+ 1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/src/test/resources/dig/test/vhdl/D-DefaultBus.dig b/src/test/resources/dig/test/vhdl/D-DefaultBus.dig
new file mode 100644
index 000000000..8eb3d0a01
--- /dev/null
+++ b/src/test/resources/dig/test/vhdl/D-DefaultBus.dig
@@ -0,0 +1,150 @@
+
+
+ 1
+
+
+
+ VDD
+
+
+ Bits
+ 4
+
+
+
+
+
+ VDD
+
+
+ Bits
+ 4
+
+
+
+
+
+ In
+
+
+ Label
+ C
+
+
+
+
+
+ Out
+
+
+ Label
+ Q1
+
+
+ Bits
+ 4
+
+
+
+
+
+ Out
+
+
+ Label
+ Q2
+
+
+ Bits
+ 4
+
+
+
+
+
+ Testcase
+
+
+ Testdata
+
+ C Q1 Q2
+0 5 0xA
+C 0xf 0xf
+
+
+
+
+
+
+
+ D_FF
+
+
+ Bits
+ 4
+
+
+ Default
+ 5
+
+
+
+
+
+ D_FF
+
+
+ Bits
+ 4
+
+
+ Default
+ 10
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file