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updated release notes

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hneemann 2017-08-31 16:36:30 +02:00
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Release Notes Release Notes
HEAD, planned as v0.14 v0.14, released on 31. Aug 2017
- Added visualization of KV maps (thanks to roy77)
- Added VHDL export - Added VHDL export
(Not yet complete, but the example processor is running on a FPGA.) (Not yet complete, but the example processor is running on a FPGA.)
- Type of pin numbers changed from int to string to allow FPGA pin names like "U16". - Type of pin numbers changed from int to string to allow FPGA pin names like "U16".
- Added support for BASYS3-Board (*.xdc constrains file is written and the mixed mode - Added support for BASYS3-Board (*.xdc constrains file is written and the mixed mode
clock manager (MMCM) is used if clock frequency exceeds 37kHz) clock manager (MMCM) is used if clock frequency exceeds 37kHz)
- Added visualization of KV maps (thanks to roy77)
- Added shortcut 'B' which sets the number of data bits in all selected components. - Added shortcut 'B' which sets the number of data bits in all selected components.
- Breaking changes: - Breaking changes:
- To generalize the VHDL export, an XML entity in the *.dig files had to be renamed. - To generalize the VHDL export, an XML entity in the *.dig files had to be renamed.