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updated the release notes

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hneemann 2018-06-11 16:43:21 +02:00
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@ -4,6 +4,8 @@ HEAD, planned as v0.19
- Added a tabbed pane to the attributes dialog to make it more beginner friendly.
- Added support for asynchronous sequential circuits such as the Muller-pipeline.
Take a look at the new asynchronous examples for illustration.
- Added export to Verilog. Special thanks to Ivan de Jesus Deras Tabora, who has
implemented the Verilog code generator and all the necessary Verilog templates!
- All examples are translated to english.
- A "test all" function has been added to start all tests in all circuits in
the current folder.