diff --git a/src/main/resources/verilog/DIG_LookUpTable.v b/src/main/resources/verilog/DIG_LookUpTable.v
index 3bfdd2c71..5a622e67f 100644
--- a/src/main/resources/verilog/DIG_LookUpTable.v
+++ b/src/main/resources/verilog/DIG_LookUpTable.v
@@ -32,8 +32,16 @@
 
     initial begin<?
 
+    data := 0;
     for (i := 0; i < lutSize; i++) { ?>
-        my_lut[<?= i ?>] = <?= format("%d'h%x", elem.Bits, elem.Data[i]) ?>;<?
+        my_lut[<?= i ?>] = <?
+        if (i<sizeOf(elem.Data)) {
+            data = elem.Data[i];
+        } else {
+            data = 0;
+        }
+        print(format("%d'h%x", elem.Bits, data));
+?>;<?
     } ?>
     end
 endmodule
diff --git a/src/main/resources/vhdl2/DIG_LookUpTable.tem b/src/main/resources/vhdl2/DIG_LookUpTable.tem
index da658dfe9..ceae2e164 100644
--- a/src/main/resources/vhdl2/DIG_LookUpTable.tem
+++ b/src/main/resources/vhdl2/DIG_LookUpTable.tem
@@ -26,8 +26,14 @@ architecture Behavioral of <?=entityName?> is
     maxCol:=76/(elem.Bits+4);
 
     col:=0;
+    data:=0;
     for (i:=0;i<len;i++) {
-        print( vhdl.value(elem.Data[i],elem.Bits));
+        if (i<sizeOf(elem.Data)) {
+          data = elem.Data[i];
+        } else {
+          data = 0;
+        }
+        print( vhdl.value(data,elem.Bits));
         if (i<len-1) {
             print(", ");
         }
diff --git a/src/test/resources/dig/test/vhdl/lut2.dig b/src/test/resources/dig/test/vhdl/lut2.dig
index 96ce9b956..1e4078082 100644
--- a/src/test/resources/dig/test/vhdl/lut2.dig
+++ b/src/test/resources/dig/test/vhdl/lut2.dig
@@ -16,7 +16,7 @@
         </entry>
         <entry>
           <string>Data</string>
-          <data>0,0,1,0,2,7,0,3</data>
+          <data>0,0,1,0,2,7</data>
         </entry>
         <entry>
           <string>Inputs</string>
@@ -83,7 +83,7 @@
  1   0   0   0
  1   0   1   7
  1   1   0   0
- 1   1   1   3
+ 1   1   1   0
 </dataString>
           </testData>
         </entry>