From 8352fd2d76b14503c85232d5f6f782a3ccb77ffe Mon Sep 17 00:00:00 2001 From: hneemann Date: Sun, 3 Mar 2019 15:27:10 +0100 Subject: [PATCH] fixed a array index issue in the LUT hdl templates --- src/main/resources/verilog/DIG_LookUpTable.v | 10 +++++++++- src/main/resources/vhdl2/DIG_LookUpTable.tem | 8 +++++++- src/test/resources/dig/test/vhdl/lut2.dig | 4 ++-- 3 files changed, 18 insertions(+), 4 deletions(-) diff --git a/src/main/resources/verilog/DIG_LookUpTable.v b/src/main/resources/verilog/DIG_LookUpTable.v index 3bfdd2c71..5a622e67f 100644 --- a/src/main/resources/verilog/DIG_LookUpTable.v +++ b/src/main/resources/verilog/DIG_LookUpTable.v @@ -32,8 +32,16 @@ initial begin - my_lut[] = ;] = ; end endmodule diff --git a/src/main/resources/vhdl2/DIG_LookUpTable.tem b/src/main/resources/vhdl2/DIG_LookUpTable.tem index da658dfe9..ceae2e164 100644 --- a/src/main/resources/vhdl2/DIG_LookUpTable.tem +++ b/src/main/resources/vhdl2/DIG_LookUpTable.tem @@ -26,8 +26,14 @@ architecture Behavioral of is maxCol:=76/(elem.Bits+4); col:=0; + data:=0; for (i:=0;i Data - 0,0,1,0,2,7,0,3 + 0,0,1,0,2,7 Inputs @@ -83,7 +83,7 @@ 1 0 0 0 1 0 1 7 1 1 0 0 - 1 1 1 3 + 1 1 1 0