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makes the download button easier to see
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hneemann
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README.md
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README.md
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[](https://github.com/hneemann/Digital/releases/latest/download/Digital.zip)
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[](https://codecov.io/gh/hneemann/Digital)
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[](https://github.com/hneemann/Digital/releases/latest/download/Digital.zip)
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# Digital #
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@ -34,39 +35,30 @@ These are the main features of Digital:
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- Analysis and synthesis of combinatorial and sequential circuits.
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- Simple testing of circuits: You can create test cases and execute them to verify your design.
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- Many examples: From a transmission gate D-flip-flop to a complete (simple) MIPS-like single cycle CPU.
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- Includes a simple editor for finite state machines (FSM). A FSM can then be converted to a state
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transition table and a circuit implementing the FSM (See [screenshot](#additional-screenshots)).
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- Includes a simple editor for finite state machines (FSM). A FSM can then be converted to a state transition table and a circuit implementing the FSM (See [screenshot](#additional-screenshots)).
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- Contains a library with the most commonly used 74xx series integrated circuits.
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- Supports generic circuits. This allows the creation of circuits that can be parameterized when used.
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In this way, it is possible, for e.g., to create a barrel shifter with a selectable bit width.
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- Supports generic circuits. This allows the creation of circuits that can be parameterized when used. In this way, it is possible, for e.g., to create a barrel shifter with a selectable bit width.
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- Good performance: The example processor can be clocked at 120 kHz.
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- Supports large circuits: The "Conway's Game of Life" example consists of about 2400 active components
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and works just fine.
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- It is possible to use custom components which are implemented in Java and packed in a jar file.
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See this [example](https://github.com/hneemann/digitalCustomComponents) for details.
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- Simple remote [TCP interface](https://github.com/hneemann/Assembler/blob/master/src/main/java/de/neemann/assembler/gui/RemoteInterface.java)
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which e.g. allows an [assembler IDE](https://github.com/hneemann/Assembler) to control
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the simulator.
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- Supports large circuits: The "Conway's Game of Life" example consists of about 2400 active components and works just fine.
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- It is possible to use custom components which are implemented in Java and packed in a jar file. See this [example](https://github.com/hneemann/digitalCustomComponents) for details.
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- Simple remote [TCP interface](https://github.com/hneemann/Assembler/blob/master/src/main/java/de/neemann/assembler/gui/RemoteInterface.java)
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which e.g. allows an [assembler IDE](https://github.com/hneemann/Assembler) to control the simulator.
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- Components can be described using VHDL or Verilog. The open source VHDL simulator [ghdl](http://ghdl.free.fr/)
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needs to be installed to simulate a VHDL defined component, and the open source Verilog simulator
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[Icarus Verilog](http://iverilog.icarus.com/) is required to simulate a Verilog defined component.
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- A circuit can be exported to VHDL or Verilog. There is also direct support for the
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[BASYS3 Board](https://reference.digilentinc.com/reference/programmable-logic/basys-3/start) and the
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[TinyFPGA BX](https://tinyfpga.com/) board.
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See the documentation for details.
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The examples folder contains a variant of the example CPU, which runs on a BASYS3 board.
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[BASYS3 Board](https://reference.digilentinc.com/reference/programmable-logic/basys-3/start) and the
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[TinyFPGA BX](https://tinyfpga.com/) board. See the documentation for details. The examples folder contains a variant of the example CPU, which runs on a BASYS3 board.
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- Direct export of JEDEC files which you can flash to a [GAL16v8](https://www.microchip.com/wwwproducts/en/ATF16V8C)
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or a [GAL22v10](https://www.microchip.com/wwwproducts/en/ATF22V10C). These chips are somewhat outdated (introduced in 1985!)
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or a [GAL22v10](https://www.microchip.com/wwwproducts/en/ATF22V10C). These chips are somewhat outdated (introduced in 1985!)
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but sufficient for beginners exercises, easy to understand and well documented. Also the
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[ATF150x](https://www.microchip.com/design-centers/programmable-logic/spld-cpld/cpld-atf15xx-family) chips are
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supported which offer up to 128 macro-cells and in system programming.
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See the [documentation](https://github.com/hneemann/Digital/releases/latest) for details.
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- SVG export of circuits, including a LaTeX/Inkscape compatible SVG version (see
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[ATF150x](https://www.microchip.com/design-centers/programmable-logic/spld-cpld/cpld-atf15xx-family) chips are
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supported which offer up to 128 macro-cells and in system programming. See the [documentation](https://github.com/hneemann/Digital/releases/latest) for details.
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- SVG export of circuits, including a LaTeX/Inkscape compatible SVG version (see
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[ctan](https://www.ctan.org/tex-archive/info/svg-inkscape))
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- No legacy code.
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- Good test coverage (about 80%; Neither the GUI tests nor the HDL simulator integration tests are running on the
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Travis-CI build servers, so CodeCov measures only about 50%).
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Almost all examples contain test cases which ensure that they work correctly.
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- Good test coverage (about 80%; Neither the GUI tests nor the HDL simulator integration tests are running on the
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Travis-CI build servers, so CodeCov measures only about 50%). Almost all examples contain test cases which ensure that they work correctly.
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The latest changes that have not yet been released are listed in the
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[release notes](distribution/ReleaseNotes.txt).
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@ -117,8 +109,7 @@ In 2014, Carl Burch finally [discontinued](http://www.cburch.com/logisim/retire-
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Logisim. Since Logisim was released as open source, there are a number of forks to continue the work on Logisim:
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- [Logisim-Evolution](https://github.com/reds-heig/logisim-evolution) by people of a group of swiss institutes
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(Haute École Spécialisée Bernoise, Haute École du paysage, d'ingénierie et d'architecture de Genève,
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and Haute École d'Ingénierie et de Gestion du Canton de Vaud)
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(Haute École Spécialisée Bernoise, Haute École du paysage, d'ingénierie et d'architecture de Genève, and Haute École d'Ingénierie et de Gestion du Canton de Vaud)
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- [Logisim](https://github.com/lawrancej/logisim) by Joseph Lawrance at Wentworth Institute of Technology, Boston, MA
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- [Logisim-iitd](https://code.google.com/archive/p/logisim-iitd/) from the Indian Institute of Technology Delhi
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- [Logisim](http://www.cs.cornell.edu/courses/cs3410/2015sp/) from the CS3410 course of the Cornell University
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@ -195,7 +186,7 @@ Because of that approach for instance a embedded AND gate in a sub circuit behav
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inserted at top level although there is actually no difference between these two variants from the
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simulation models perspective.
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Logisim works somewhat different, which sometimes leads to surprises like unexpected signal propagation times and
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which makes it difficult to use bidirectional pins.
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which makes it difficult to use bidirectional pins.
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### Performance ###
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@ -243,7 +234,7 @@ over and over again.
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## How do I get set up? ##
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If you want to build Digital from the source code:
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* At first clone the repository.
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* A JDK (at least JDK 8) is required (either the Oracle JDK or OpenJDK)
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* maven is used as build system, so the easiest way is to install [maven](https://maven.apache.org/).
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@ -258,19 +249,15 @@ If you want to build Digital from the source code:
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* Before you send a pull request, make sure that at least `mvn install` runs without errors.
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* Don't introduce new findbugs issues.
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* Try to keep the test coverage high. The target is a minimum of 80% test coverage.
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* So far, there are only a few GUI tests, so that the overall test coverage is only slightly below 80%.
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Try to keep the amount of untested GUI code low.
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* So far, there are only a few GUI tests, so that the overall test coverage is only slightly below 80%. Try to keep the amount of untested GUI code low.
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## Credits ##
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Many thanks to the following persons for their help:
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* Ivan de Jesus Deras Tabora from the Universidad Tecnológica Centroamericana in Honduras has
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implemented the verilog code generator and almost all the necessary verilog templates.
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* Theldo Cruz Franqueira from the Pontifícia Universidade Católica de Minas Gerais in Brazil
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has provided the Portuguese translation.
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* Ángel Millán from the Instituto de Educación Secundaria Ies Virgen de Villadiego in Peñaflor (Sevilla), Spain
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has provided the Spanish translation.
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* Ivan de Jesus Deras Tabora from the Universidad Tecnológica Centroamericana in Honduras has implemented the verilog code generator and almost all the necessary verilog templates.
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* Theldo Cruz Franqueira from the Pontifícia Universidade Católica de Minas Gerais in Brazil has provided the Portuguese translation.
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* Ángel Millán from the Instituto de Educación Secundaria Ies Virgen de Villadiego in Peñaflor (Sevilla), Spain has provided the Spanish translation.
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* XinJun Ma ([@itviewer](https://github.com/itviewer)) has provided the Chinese translation.
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* Nicolas Maltais ([@maltaisn](https://github.com/maltaisn)) has provided the French translation.
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* Luca Cavallari ([@psiwray](https://github.com/psiwray)) has provided the Italian translation.
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@ -1,8 +1,86 @@
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