makes the download button easier to see

README.md

@@ -1,6 +1,7 @@
+[![Download](distribution/Download.svg)](https://github.com/hneemann/Digital/releases/latest/download/Digital.zip)
+
 ![Build Status](https://travis-ci.com/hneemann/Digital.svg?branch=master)
 [![codecov](https://codecov.io/gh/hneemann/Digital/branch/master/graph/badge.svg)](https://codecov.io/gh/hneemann/Digital)
-[![Download](distribution/Download.svg)](https://github.com/hneemann/Digital/releases/latest/download/Digital.zip)
 
 # Digital #
 
@@ -34,39 +35,30 @@ These are the main features of Digital:
 - Analysis and synthesis of combinatorial and sequential circuits.
 - Simple testing of circuits: You can create test cases and execute them to verify your design.
 - Many examples: From a transmission gate D-flip-flop to a complete (simple) MIPS-like single cycle CPU.
-- Includes a simple editor for finite state machines (FSM). A FSM can then be converted to a state
+- Includes a simple editor for finite state machines (FSM). A FSM can then be converted to a state transition table and a circuit implementing the FSM (See [screenshot](#additional-screenshots)).
-  transition table and a circuit implementing the FSM (See [screenshot](#additional-screenshots)).
 - Contains a library with the most commonly used 74xx series integrated circuits.
-- Supports generic circuits. This allows the creation of circuits that can be parameterized when used. 
+- Supports generic circuits. This allows the creation of circuits that can be parameterized when used. In this way, it is possible, for e.g., to create a barrel shifter with a selectable bit width.
-  In this way, it is possible, for e.g., to create a barrel shifter with a selectable bit width.
 - Good performance: The example processor can be clocked at 120 kHz.
-- Supports large circuits: The "Conway's Game of Life" example consists of about 2400 active components
+- Supports large circuits: The "Conway's Game of Life" example consists of about 2400 active components and works just fine.
-  and works just fine.
+- It is possible to use custom components which are implemented in Java and packed in a jar file. See this [example](https://github.com/hneemann/digitalCustomComponents) for details.   
-- It is possible to use custom components which are implemented in Java and packed in a jar file. 
+- Simple remote [TCP interface](https://github.com/hneemann/Assembler/blob/master/src/main/java/de/neemann/assembler/gui/RemoteInterface.java)
-  See this [example](https://github.com/hneemann/digitalCustomComponents) for details.   
+  which e.g. allows an [assembler IDE](https://github.com/hneemann/Assembler) to control the simulator.
-- Simple remote [TCP interface](https://github.com/hneemann/Assembler/blob/master/src/main/java/de/neemann/assembler/gui/RemoteInterface.java) 
-  which e.g. allows an [assembler IDE](https://github.com/hneemann/Assembler) to control 
-  the simulator.
 - Components can be described using VHDL or Verilog. The open source VHDL simulator [ghdl](http://ghdl.free.fr/)
   needs to be installed to simulate a VHDL defined component, and the open source Verilog simulator
   [Icarus Verilog](http://iverilog.icarus.com/) is required to simulate a Verilog defined component.
 - A circuit can be exported to VHDL or Verilog. There is also direct support for the
-  [BASYS3 Board](https://reference.digilentinc.com/reference/programmable-logic/basys-3/start) and the 
+  [BASYS3 Board](https://reference.digilentinc.com/reference/programmable-logic/basys-3/start) and the
-  [TinyFPGA BX](https://tinyfpga.com/) board.
+  [TinyFPGA BX](https://tinyfpga.com/) board. See the documentation for details. The examples folder contains a variant of the example CPU, which runs on a BASYS3 board.
-  See the documentation for details.
-  The examples folder contains a variant of the example CPU, which runs on a BASYS3 board.
 - Direct export of JEDEC files which you can flash to a [GAL16v8](https://www.microchip.com/wwwproducts/en/ATF16V8C)
-  or a [GAL22v10](https://www.microchip.com/wwwproducts/en/ATF22V10C). These chips are somewhat outdated (introduced in 1985!) 
+  or a [GAL22v10](https://www.microchip.com/wwwproducts/en/ATF22V10C). These chips are somewhat outdated (introduced in 1985!)
   but sufficient for beginners exercises, easy to understand and well documented. Also the
-  [ATF150x](https://www.microchip.com/design-centers/programmable-logic/spld-cpld/cpld-atf15xx-family) chips are 
+  [ATF150x](https://www.microchip.com/design-centers/programmable-logic/spld-cpld/cpld-atf15xx-family) chips are
-  supported which offer up to 128 macro-cells and in system programming.
+  supported which offer up to 128 macro-cells and in system programming. See the [documentation](https://github.com/hneemann/Digital/releases/latest) for details.
-  See the [documentation](https://github.com/hneemann/Digital/releases/latest) for details.
+- SVG export of circuits, including a LaTeX/Inkscape compatible SVG version (see
-- SVG export of circuits, including a LaTeX/Inkscape compatible SVG version (see 
   [ctan](https://www.ctan.org/tex-archive/info/svg-inkscape))
 - No legacy code.
-- Good test coverage (about 80%; Neither the GUI tests nor the HDL simulator integration tests are running on the 
+- Good test coverage (about 80%; Neither the GUI tests nor the HDL simulator integration tests are running on the
-  Travis-CI build servers, so CodeCov measures only about 50%).
+  Travis-CI build servers, so CodeCov measures only about 50%). Almost all examples contain test cases which ensure that they work correctly.
-  Almost all examples contain test cases which ensure that they work correctly.
 
 The latest changes that have not yet been released are listed in the
 [release notes](distribution/ReleaseNotes.txt).
@@ -117,8 +109,7 @@ In 2014, Carl Burch finally [discontinued](http://www.cburch.com/logisim/retire-
 Logisim. Since Logisim was released as open source, there are a number of forks to continue the work on Logisim:
 
 - [Logisim-Evolution](https://github.com/reds-heig/logisim-evolution) by people of a group of swiss institutes
-  (Haute École Spécialisée Bernoise, Haute École du paysage, d'ingénierie et d'architecture de Genève,
+  (Haute École Spécialisée Bernoise, Haute École du paysage, d'ingénierie et d'architecture de Genève, and Haute École d'Ingénierie et de Gestion du Canton de Vaud)
-  and Haute École d'Ingénierie et de Gestion du Canton de Vaud)
 - [Logisim](https://github.com/lawrancej/logisim) by Joseph Lawrance at Wentworth Institute of Technology, Boston, MA 
 - [Logisim-iitd](https://code.google.com/archive/p/logisim-iitd/) from the Indian Institute of Technology Delhi
 - [Logisim](http://www.cs.cornell.edu/courses/cs3410/2015sp/) from the CS3410 course of the Cornell University
@@ -195,7 +186,7 @@ Because of that approach for instance a embedded AND gate in a sub circuit behav
 inserted at top level although there is actually no difference between these two variants from the 
 simulation models perspective.
 Logisim works somewhat different, which sometimes leads to surprises like unexpected signal propagation times and
-which makes it difficult to use bidirectional pins. 
+which makes it difficult to use bidirectional pins.
 
 ### Performance ###
 
@@ -243,7 +234,7 @@ over and over again.
 ## How do I get set up? ##
 
 If you want to build Digital from the source code:
- 
+
 * At first clone the repository.
 * A JDK (at least JDK 8) is required (either the Oracle JDK or OpenJDK)
 * maven is used as build system, so the easiest way is to install [maven](https://maven.apache.org/).
@@ -258,19 +249,15 @@ If you want to build Digital from the source code:
   * Before you send a pull request, make sure that at least `mvn install` runs without errors.
 * Don't introduce new findbugs issues.
 * Try to keep the test coverage high. The target is a minimum of 80% test coverage.
-* So far, there are only a few GUI tests, so that the overall test coverage is only slightly below 80%.
+* So far, there are only a few GUI tests, so that the overall test coverage is only slightly below 80%. Try to keep the amount of untested GUI code low.
-  Try to keep the amount of untested GUI code low.
 
 ## Credits ##
 
 Many thanks to the following persons for their help:
 
-* Ivan de Jesus Deras Tabora from the Universidad Tecnológica Centroamericana in Honduras has
+* Ivan de Jesus Deras Tabora from the Universidad Tecnológica Centroamericana in Honduras has implemented the verilog code generator and almost all the necessary verilog templates.
-  implemented the verilog code generator and almost all the necessary verilog templates.
+* Theldo Cruz Franqueira from the Pontifícia Universidade Católica de Minas Gerais in Brazil has provided the Portuguese translation.
-* Theldo Cruz Franqueira from the Pontifícia Universidade Católica de Minas Gerais in Brazil
+* Ángel Millán from the Instituto de Educación Secundaria Ies Virgen de Villadiego in Peñaflor (Sevilla), Spain has provided the Spanish translation.
-  has provided the Portuguese translation.
-* Ángel Millán from the Instituto de Educación Secundaria Ies Virgen de Villadiego in Peñaflor (Sevilla), Spain
-  has provided the Spanish translation.
 * XinJun Ma ([@itviewer](https://github.com/itviewer)) has provided the Chinese translation.
 * Nicolas Maltais ([@maltaisn](https://github.com/maltaisn)) has provided the French translation.
 * Luca Cavallari ([@psiwray](https://github.com/psiwray)) has provided the Italian translation.

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