From 922a09eef7f2322ce045da61ab07bd28054c1b4f Mon Sep 17 00:00:00 2001
From: Ivan de Jesus Deras <ideras@gmail.com>
Date: Thu, 7 Jun 2018 14:28:06 -0600
Subject: [PATCH] Fixed a problem with the generated verilog code for the ROM
 component

---
 .../de/neemann/digital/hdl/verilog2/lib/VerilogTemplate.java | 1 -
 src/main/resources/verilog/DIG_ROM.v                         | 5 ++---
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/src/main/java/de/neemann/digital/hdl/verilog2/lib/VerilogTemplate.java b/src/main/java/de/neemann/digital/hdl/verilog2/lib/VerilogTemplate.java
index 283ab9884..051a2e1c9 100644
--- a/src/main/java/de/neemann/digital/hdl/verilog2/lib/VerilogTemplate.java
+++ b/src/main/java/de/neemann/digital/hdl/verilog2/lib/VerilogTemplate.java
@@ -32,7 +32,6 @@ public class VerilogTemplate implements VerilogElement {
     private final static String MODULE_PREFIX = "DIG_";
 
     private final String moduleBaseName;
-    private String moduleName;
     private final Statement statements;
     private HashMap<String, Module> modules;
 
diff --git a/src/main/resources/verilog/DIG_ROM.v b/src/main/resources/verilog/DIG_ROM.v
index 1769f0e19..986a5e0f8 100644
--- a/src/main/resources/verilog/DIG_ROM.v
+++ b/src/main/resources/verilog/DIG_ROM.v
@@ -8,12 +8,11 @@
 ?>module <?= moduleName ?> (
     input <?= aBitRange ?> A,
     input sel,
-    output <?= dBitRange ?> D
+    output reg <?= dBitRange ?> D
 );
     reg <?= dBitRange ?> my_rom [0:<?= (romSize - 1) ?>];
-    reg D;
 
-    always @ (A or sel) begin
+    always @ (*) begin
         if (~sel)
             D = <?= elem.Bits ?>'hz;<?
         if (romSize < romMaxSize) {