diff --git a/src/main/resources/lang/lang_zh.xml b/src/main/resources/lang/lang_zh.xml index 0cead1cf5..2967ed9e4 100644 --- a/src/main/resources/lang/lang_zh.xml +++ b/src/main/resources/lang/lang_zh.xml @@ -5,8 +5,7 @@ This makes it very difficult for me to continue to maintain the translation. The only exception are simple typos. Pull requests in which this file is modified beyond simple typos cannot be accepted. In the file howTo.md you can find more details about translations. ---> - +--> 地址 目录 一般使用 @@ -238,8 +237,6 @@ In the file howTo.md you can find more details about translations. 输出位 {0} 双向分裂器 可用于数据总线特别是存储器模块的构建 - When set, the value at the common data terminal D is output to the bit - outputs D[i], if not, the bits D[i] are output to the common output D. 数据位 {0} 上拉电阻 弱高电平 @@ -345,7 +342,7 @@ In the file howTo.md you can find more details about translations. P 沟道场效应晶体管 N 沟道浮动门场效应晶体管 测试用例 - 用于定义测试用例,可用于自动检测电路的行为是否符合该定义。 + 用于定义测试用例,可用于自动检测电路的行为是否符合定义。 异步时序 允许设置异步时序电路如Muller流水线的时序。 电源连接器 @@ -1360,7 +1357,6 @@ In the file howTo.md you can find more details about translations. 无法打开浏览器 无法创建文件夹 "{0}" 不可仅连接输入信号到开关 - The file {0} exists multiple times below {1}. 找不到文件 {0} 执行 "{0}" 时遇到错误 进程 "{0}" 无返回内容! @@ -1555,4 +1551,62 @@ In the file howTo.md you can find more details about translations. 优化时出错! 初始复杂度: 目前最优: + 搜索 + 集合连接 + 异步 RAM + 当 we 为高电平时,每当地址或数据改变时,都会存储数据 D 到地址 A + 读写地址 + 待存储数据 + 写使能 + 输出地址 A 存储的数据 + Register + 计数器 + 位计数器 + 需要 {0} 个值,而不是 {1} + 组件 ''{1}'' 的输入端口 ''{0}'' 没有连接到任何地方 + 逻辑看起来产生震荡,你可以通过单步方式运行电路来进行分析。 + 期待 {0} 个值,但发现 {1} 个,位于行 {2}。 + 未知 token {0},行 {1} + 不支持设置中定义的 ROMS! + 加载编程数据时出错。 + 所有待加载数据必须具有相同的位宽 + 如果要将程序加载到多个RAM中,则所有RAM必须具有不同的名称。 + 未知 HDL:{0} + 替换组件进行分析时出错。 + 全局变量只能写在代码组件中 + 信号 {0} 在行 {1} 声明了两次! + 没有表头 + 没有输出值! + 一行中缺少值 + 一行中包含太多的值 + 小数位数 + 如果选中该选项,则该组件处于活动状态时输出为低电平。 + GHDL + IVerilog + IVerilog 选项 + IVerilog 选项 + IVerilog + ATMISP + Simple + DIL-Chip + Layout + RA + EEPROM + 允许电路中缺少测试用例中定义的输入。 如果有几种可能的解决方案可能取决于不同的输入,这将很有用。 + CSV + 包含完整真值表的 CSV 文件 + 太多内容! + 来自外部 fitter 的消息 + 执行外部 fitter + 逗号分割的值 + 创建 Fixture 测试用例 + 创建 fixture 测试用例修复当前行为 + 创建 Fixture + 在测试用例中创建新的 Fixture + 完成 + 创建测试用例组件 + 创建测试用例时产生错误。 + 没有变化 + 迁移 + 迁移 + 状态 diff --git a/src/main/resources/lang/lang_zh_ref.xml b/src/main/resources/lang/lang_zh_ref.xml index 5e19c6e60..6ed3d2f92 100644 --- a/src/main/resources/lang/lang_zh_ref.xml +++ b/src/main/resources/lang/lang_zh_ref.xml @@ -4,8 +4,7 @@ Do not edit this file directly! This makes it very difficult for me to continue to maintain the translation. Pull requests in which this file is modified cannot be accepted. In the file howTo.md you can find more details about translations. ---> - +--> Address Table of Contents General @@ -430,7 +429,8 @@ In the file howTo.md you can find more details about translations. Describes a test case. In a test case you can describe how a circuit should behave. It can then be automatically checked whether the behavior of the circuit actually corresponds to this description. If this is not the case, an - error message is shown. + error message is shown. + The help text of the test case editor describes in detail how such a test case can be created. Asynchronous Timing Allows configuration of the timing of an asynchronous sequential circuit such as a Muller-pipeline. The circuit must be started in single gate step mode and must be able to reach a stable state @@ -1954,4 +1954,78 @@ In the file howTo.md you can find more details about translations. Error during optimization! Initial complexity: Best so far: + search + The common data connection. + RAM, async. + As long as we is set, it is stored. Corresponds to a very simple RAM, where the + address and data lines are directly connected to the decoders of the memory cells. + The address at which reading or writing takes place. + The data to be stored. + Write enable. As long as this input is set to 1, the value applied to D is + stored at the address applied to A whenever A or D is changed. + Output of the stored data. + Register + Counter + Bit count + No break detected after {0} cycles at break point ''{1}''. + Possibly the number of timeout cycles in the break component should be increased. + Exact {0} values necessary, not {1} + Nothing connected to input ''{0}'' at component ''{1}''. Open inputs are not allowed. + Logic seems to oscillate. + To analyse you can run the circuit in single gate step mode. + Expected {0} but found {1} values in line {2}! + Unexpected token ({0}) in line {1}. + ROMs defined in the settings are not supported! + Error loading the program memory. + All memories into which data are to be loaded require the same bit width. + If programs are to be loaded into several RAMs, all RAMs must have + different names. The lexical order then determines the order of the RAMs. + HDL not known: {0} + Error when substituting components for the analysis. + Global variables can only be written in code components. + Virtual signal {0} declared twice in line {1}! + No header found! + No output values found! + Not enough values in one line! + Too many values in one line! + ASCII + Bin + Decimal + Default + Hex + Octal + Number of fractional binary digits + If selected the output is low if the component is active. + GHDL + IVerilog + IVerilog Options + Options that are used for all processing steps by IVerilog. + IVerilog + ATMISP + Simple + DIL-Chip + Layout + RAM + EEPROM + Allows the lack of inputs in the circuit which are + defined in the test case. This can be useful if there are several possible solutions which may + depend on different inputs. + CSV + A CSV file containing the complete truth table. + A CSV file containing only the prime implicants. + (Too many entries!) + Message from the external fitter + Execution of external fitter + Comma Separated Values, CSV + Create Behavior Fixing Test Case + Creates a behavioral fixture from the circuit. + A behavioral fixture is a test case that fixes the current behavior. + Create Fixture + Creates a new fixture in the test case. + Complete + Creates the test case component + Error in the creation of the test case. + No movement + Transitions + Transitions+States diff --git a/src/test/java/de/neemann/digital/lang/TestSyntax.java b/src/test/java/de/neemann/digital/lang/TestSyntax.java index b0e4a6eba..c627464e2 100644 --- a/src/test/java/de/neemann/digital/lang/TestSyntax.java +++ b/src/test/java/de/neemann/digital/lang/TestSyntax.java @@ -33,8 +33,8 @@ public class TestSyntax extends TestCase { for (String key : en.getKeys()) { final String en_msg = en.get(key); final String de_msg = de.get(key); - int paramCount = getParamCount(en_msg); - assertEquals(key, paramCount, getParamCount(de_msg)); + int paramCount = getParamCount(key, en_msg); + assertEquals(key, paramCount, getParamCount(key, de_msg)); checkSingleQuoteRules(en_msg, key, paramCount); checkSingleQuoteRules(de_msg, key, paramCount); @@ -42,7 +42,7 @@ public class TestSyntax extends TestCase { final String m = r.get(key); if (m != null) { checkSingleQuoteRules(m, key, paramCount); - assertEquals("Param count does not match: " + key + " " + m, paramCount, getParamCount(m)); + assertEquals("Param count does not match: " + key + " " + m, paramCount, getParamCount(key, m)); } } } @@ -50,14 +50,14 @@ public class TestSyntax extends TestCase { } - private int getParamCount(String msg) { + private int getParamCount(String key, String msg) { HashSet numSet = new HashSet<>(); int pos = 0; while (true) { pos = msg.indexOf("{", pos); if (pos < 0) { for (int i = 0; i < numSet.size(); i++) - assertTrue(numSet.contains(i)); + assertTrue(key + ": param " + i + " is missing in " + msg, numSet.contains(i)); return numSet.size(); }