diff --git a/src/main/java/de/neemann/digital/hdl/vhdl2/VHDLTestBenchCreator.java b/src/main/java/de/neemann/digital/hdl/vhdl2/VHDLTestBenchCreator.java
index 000378749..91e38d1c1 100644
--- a/src/main/java/de/neemann/digital/hdl/vhdl2/VHDLTestBenchCreator.java
+++ b/src/main/java/de/neemann/digital/hdl/vhdl2/VHDLTestBenchCreator.java
@@ -115,6 +115,17 @@ public class VHDLTestBenchCreator {
             out.print("signal ").print(p.getName()).print(" : ").print(VHDLCreator.getType(p.getBits())).println(";");
         for (HDLPort p : main.getOutputs())
             out.print("signal ").print(p.getName()).print(" : ").print(VHDLCreator.getType(p.getBits())).println(";");
+
+        out.print("function to_string ( a: std_logic_vector) return string is\n"
+                + "    variable b : string (1 to a'length) := (others => NUL);\n"
+                + "    variable stri : integer := 1; \n"
+                + "begin\n"
+                + "    for i in a'range loop\n"
+                + "        b(stri) := std_logic'image(a((i)))(2);\n"
+                + "    stri := stri+1;\n"
+                + "    end loop;\n"
+                + "    return b;\n"
+                + "end function;\n");
         out.dec().println("begin").inc();
 
         out.println("main_0 : main port map (").inc();
@@ -195,8 +206,8 @@ public class VHDLTestBenchCreator {
     }
 
     private String convertFunc(HDLPort p) {
-        if (p.getBits()>1)
-            return "to_hstring";
+        if (p.getBits() > 1)
+            return "to_string";
         return "std_logic'image";
     }
 
diff --git a/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLSimulatorTest.java b/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLSimulatorTest.java
index eba86287d..55c37c2c1 100644
--- a/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLSimulatorTest.java
+++ b/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLSimulatorTest.java
@@ -140,14 +140,14 @@ public class VHDLSimulatorTest extends TestCase {
     }
 
     private void runGHDL(File vhdlFile, ArrayList<File> testFileWritten) throws IOException, FileScanner.SkipAllException, HDLException {
-        checkWarn(vhdlFile, startProcess(vhdlFile.getParentFile(), GHDL, "-a", "--std=08", "--ieee=synopsys", vhdlFile.getName()));
-        checkWarn(vhdlFile, startProcess(vhdlFile.getParentFile(), GHDL, "-e", "--std=08", "--ieee=synopsys", "main"));
+        checkWarn(vhdlFile, startProcess(vhdlFile.getParentFile(), GHDL, "-a", "--std=02", "--ieee=synopsys", vhdlFile.getName()));
+        checkWarn(vhdlFile, startProcess(vhdlFile.getParentFile(), GHDL, "-e", "--std=02", "--ieee=synopsys", "main"));
         for (File testbench : testFileWritten) {
             String name = testbench.getName();
-            checkWarn(testbench, startProcess(vhdlFile.getParentFile(), GHDL, "-a", "--std=08", "--ieee=synopsys", name));
+            checkWarn(testbench, startProcess(vhdlFile.getParentFile(), GHDL, "-a", "--std=02", "--ieee=synopsys", name));
             String module = name.substring(0, name.length() - 5);
-            checkWarn(testbench, startProcess(vhdlFile.getParentFile(), GHDL, "-e", "--std=08", "--ieee=synopsys", module));
-            String result = startProcess(vhdlFile.getParentFile(), GHDL, "-r", "--std=08", "--ieee=synopsys", module, "--vcd=" + module + ".vcd");
+            checkWarn(testbench, startProcess(vhdlFile.getParentFile(), GHDL, "-e", "--std=02", "--ieee=synopsys", module));
+            String result = startProcess(vhdlFile.getParentFile(), GHDL, "-r", "--std=02", "--ieee=synopsys", module, "--vcd=" + module + ".vcd");
             if (result.contains("(assertion error)"))
                 throw new HDLException("test bench " + name + " failed:\n" + result);
             checkWarn(testbench, result);