From a6579f5d7ee2488dd5e5c05bd72e9cd93fbf30e3 Mon Sep 17 00:00:00 2001 From: hneemann Date: Thu, 24 Aug 2017 13:41:42 +0200 Subject: [PATCH] Ff the clock frequency is set to the board frequency, the prescaler is omitted. --- .../neemann/digital/hdl/model/HDLModel.java | 20 +++--- .../digital/hdl/vhdl/TestInSimulator.java | 2 +- .../digital/hdl/vhdl/lib/ClockTest.java | 58 +++++++++++++++++ src/test/resources/dig/hdl/Clock3.dig | 65 +++++++++++++++++++ 4 files changed, 135 insertions(+), 10 deletions(-) create mode 100644 src/test/resources/dig/hdl/Clock3.dig diff --git a/src/main/java/de/neemann/digital/hdl/model/HDLModel.java b/src/main/java/de/neemann/digital/hdl/model/HDLModel.java index ded20c9a0..ec3c5c2da 100644 --- a/src/main/java/de/neemann/digital/hdl/model/HDLModel.java +++ b/src/main/java/de/neemann/digital/hdl/model/HDLModel.java @@ -258,18 +258,20 @@ public class HDLModel implements HDLInterface, Iterable { public void integrateClocks(int period) throws HDLException { for (HDLClock c : clocks) { int freq = c.getFrequency(); - int counter = 1000000000 / (period * freq * 2); + int counter = (int) (1000000000L / (2L * period * freq)); - Port cOut = new Port("out", Port.Direction.out).setBits(1); - Port cIn = new Port("in", Port.Direction.in).setBits(1); + if (counter >= 2) { + Port cOut = new Port("out", Port.Direction.out).setBits(1); + Port cIn = new Port("in", Port.Direction.in).setBits(1); - Signal oldSig = c.getClockPort().getSignal(); - Signal newSig = createSignal(); - oldSig.replaceWith(newSig); - newSig.addPort(cOut); - oldSig.addPort(cIn); + Signal oldSig = c.getClockPort().getSignal(); + Signal newSig = createSignal(); + oldSig.replaceWith(newSig); + newSig.addPort(cOut); + oldSig.addPort(cIn); - nodeList.add(new HDLClockNode(counter, new Ports().add(cIn).add(cOut))); + nodeList.add(new HDLClockNode(counter, new Ports().add(cIn).add(cOut))); + } } } } diff --git a/src/test/java/de/neemann/digital/hdl/vhdl/TestInSimulator.java b/src/test/java/de/neemann/digital/hdl/vhdl/TestInSimulator.java index bb3a5df0a..defbd3a7f 100644 --- a/src/test/java/de/neemann/digital/hdl/vhdl/TestInSimulator.java +++ b/src/test/java/de/neemann/digital/hdl/vhdl/TestInSimulator.java @@ -48,7 +48,7 @@ public class TestInSimulator extends TestCase { File examples = new File(Resources.getRoot(), "/dig/hdl"); try { int tested = new FileScanner(this::check).scan(examples); - assertEquals(24, tested); + assertEquals(25, tested); } catch (FileScanner.SkipAllException e) { // if ghdl is not installed its also ok } diff --git a/src/test/java/de/neemann/digital/hdl/vhdl/lib/ClockTest.java b/src/test/java/de/neemann/digital/hdl/vhdl/lib/ClockTest.java index e1d20e9f5..ff0338f52 100644 --- a/src/test/java/de/neemann/digital/hdl/vhdl/lib/ClockTest.java +++ b/src/test/java/de/neemann/digital/hdl/vhdl/lib/ClockTest.java @@ -228,4 +228,62 @@ public class ClockTest extends TestCase { "end DIG_simpleClockDivider_arch;\n", vhdl); } + + // If frequency is high, the clock divider is omitted. + public void testClock3() throws PinException, NodeException, ElementNotFoundException, IOException, HDLException { + ToBreakRunner br = new ToBreakRunner("dig/hdl/Clock3.dig"); + String vhdl = new VHDLExporter(br.getLibrary()) { + @Override + protected void fixClocks(HDLModel model) throws HDLException { + model.integrateClocks(10); + } + }.export(br.getCircuit()).toString(); + + assertEquals("-- auto generated by Digital\n" + + "\n" + + "LIBRARY ieee;\n" + + "USE ieee.std_logic_1164.all;\n" + + "USE ieee.numeric_std.all;\n" + + "\n" + + "entity main is\n" + + " port (\n" + + " PORT_OV: out std_logic;\n" + + " PORT_C: in std_logic );\n" + + "end main;\n" + + "\n" + + "architecture main_arch of main is\n" + + "\n" + + " component NOT_GATE\n" + + " port (\n" + + " PORT_out: out std_logic;\n" + + " PORT_in: in std_logic );\n" + + " end component;\n" + + "\n" + + "begin\n" + + " gate0 : NOT_GATE\n" + + " port map (\n" + + " PORT_out => PORT_OV,\n" + + " PORT_in => PORT_C );\n" + + "end main_arch;\n" + + "\n" + + "-- library components\n" + + "\n" + + "-- NOT_GATE\n" + + "\n" + + "LIBRARY ieee;\n" + + "USE ieee.std_logic_1164.all;\n" + + "\n" + + "entity NOT_GATE is\n" + + " port (\n" + + " PORT_out: out std_logic;\n" + + " PORT_in: in std_logic );\n" + + "end NOT_GATE;\n" + + "\n" + + "architecture NOT_GATE_arch of NOT_GATE is\n" + + "begin\n" + + " PORT_out <= NOT( PORT_in );\n" + + "end NOT_GATE_arch;\n", vhdl); + } + + } diff --git a/src/test/resources/dig/hdl/Clock3.dig b/src/test/resources/dig/hdl/Clock3.dig new file mode 100644 index 000000000..14986f4c3 --- /dev/null +++ b/src/test/resources/dig/hdl/Clock3.dig @@ -0,0 +1,65 @@ + + + 1 + + + + Out + + + Label + OV + + + pinNumber + U18 + + + + + + Clock + + + Label + C + + + pinNumber + W5 + + + Frequency + 100000000 + + + + + + Not + + + + + Text + + + Description + Board: BASYS3 + + + + + + + + + + + + + + + + + \ No newline at end of file