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fixed a warning in counter VHDL template

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hneemann 2017-11-15 20:18:09 +01:00
parent c611dfb0cf
commit b685d42ee5
1 changed files with 1 additions and 1 deletions
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src/main/resources/vhdl/DIG_Counter.vhdl
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@ -14,7 +14,7 @@ end DIG_Counter;
architecture DIG_Counter_arch of DIG_Counter is
signal count : {{data}} := {{zero}};
begin
process (PORT_C, PORT_clr)
process (PORT_C, PORT_clr, PORT_en)
begin
if PORT_clr='1' then
count <= {{zero}};