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renamed some example files

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This commit is contained in:
hneemann 2018-06-18 19:56:37 +02:00
parent 43db280ed6
commit b767d375dd
3 changed files with 2 additions and 2 deletions
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2
src/main/dig/processor/HDLExample.dig
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@ -439,7 +439,7 @@ end loop
<pos x="600" y="340"/>
</visualElement>
<visualElement>
<elementName>GPI_VHDL.dig</elementName>
<elementName>GPI-HDL.dig</elementName>
<elementAttributes/>
<pos x="800" y="300"/>
</visualElement>

0
src/main/dig/processor/IO/GPI_VHDL.dig → src/main/dig/processor/IO/GPI-HDL.dig
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2
src/main/dig/processor/ProcessorMux.dig
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@ -695,7 +695,7 @@ Single-Cycle CPU.}}</string>
<pos x="1260" y="160"/>
</visualElement>
<visualElement>
<elementName>PC_VHDL.dig</elementName>
<elementName>PC-HDL.dig</elementName>
<elementAttributes/>
<pos x="400" y="140"/>
</visualElement>