diff --git a/README.md b/README.md index 8c5c4f214..6468db2dc 100644 --- a/README.md +++ b/README.md @@ -76,13 +76,15 @@ All other tests, including the HDL tests, were executed without errors. ## Documentation ## -The [documentation](https://github.com/hneemann/Digital/releases/latest) is available in English, German, Spanish and Portuguese. +The [documentation](https://github.com/hneemann/Digital/releases/latest) is available in English, +German, Spanish, Portuguese and simplified Chinese. It is still very incomplete but it contains a chapter "First Steps" which explains the basic usage of Digital. The documentation also contains a list of available 74xx chips and a list of available keyboard shortcuts. ## Translations ## -So far Digital is available in English, German, Spanish and Portuguese. If someone wants to add a +So far Digital is available in English, German, Spanish, Portuguese and simplified Chinese. +If someone wants to add a new translation, please let me [know](mailto:digital-simulator@web.de). I can provide you with a special file for translation. This file is much easier to translate than the [files](https://github.com/hneemann/Digital/blob/master/src/main/resources/lang) @@ -269,6 +271,7 @@ Many thanks to the following persons for their help: has provided the Portuguese translation. * Ángel Millán from the Instituto de Educación Secundaria Ies Virgen de Villadiego in Peñaflor (Sevilla), Spain has provided the Spanish translation. +* XinJun Ma ([@itviewer](https://github.com/itviewer)) has provided the Chinese translation. ## Additional Screenshots diff --git a/src/main/resources/lang/lang.xml b/src/main/resources/lang/lang.xml index c74025dd1..7a23ff167 100644 --- a/src/main/resources/lang/lang.xml +++ b/src/main/resources/lang/lang.xml @@ -23,4 +23,5 @@ modified keys. Deutsch Español Português + 简体中文 diff --git a/src/main/resources/lang/lang_zh.xml b/src/main/resources/lang/lang_zh.xml new file mode 100644 index 000000000..513a98545 --- /dev/null +++ b/src/main/resources/lang/lang_zh.xml @@ -0,0 +1,1674 @@ + + + 地址 + 目录 + 一般使用 + 修订版本 + 日期 + 以下内容为可用的仿真器设置 + 最大值 + 属性 + 打开电路 + 包含电路： + 在新窗口中打开电路 + 帮助 + 显示该组件的简介 + 十六进制 + 十进制 + Ascii码 + 高阻 + 八进制 + 二进制 + 基础设置 + 高级设置 + 忽略修改 + 编辑 + 继续编辑 + 载入 + 重新载入 + 重新载入最后使用的十六进制文件 + 保存 + 另存为十六进制文件 + 创建 + 在新窗口中创建电路 + 分离编辑 + 以非模态方式打开对话框 + 浏览器打开 + 在浏览器中打开帮助文本 + 清空 + 所有值将被置为0！ + 转换 + 所有可能的转换被添加为测试用例。 + 新名称 + 始终保存 + 覆盖 + 应用 + 编辑所选 ROM/EEPROM 中的内容 + 移除所选 ROM 中存储的数据。 + 创建模板 + 创建SVG模板，之后可以使用 Inkscape 编辑 + 导入 + 导入 SVG 文件。如果需要创建 SVG 文件，最好的方式时首先创建 SVG 模板，然后进行编辑。 + 警告 + 取消 + Digital + 表达式 + 输入 + 输出 + 属性 + 逻辑运算输入 {0} + 逻辑运算结果 + 与门 + 二进制与门，仅当所有输入为 1 时输出为 1。 + 其输入和输出也可以使用多位总线，此时将执行按位与运算。 + 与非门 + 与和非的组合。仅当所有输入为 1 时，输出为 0。其输入也可以使用多位总线，此时将先执行按位与运算，然后执行逻辑非运算。 + 或门 + 二进制或门，如果其中一个输入为 1 则输出 1。 + 其输入和输出也可以使用多位总线，此时将执行按位或运算。 + 或非门 + 或门和非门的组合。 + 如果其中一个输入为 1 则输出为 0，如果所有输入为 0，输出为 1。 + 其输入也可以使用多位总线，此时将先执行按位或运算，然后执行逻辑非运算。 + 异或门 + 如果两个输入被使用，当两个输入相等时输出为 0，否则为 1。 + 如果多于两个输入，其行为类似于级联的异或门(A 异或 B 异或 C = (A 异或 B) 异或 C)。 + 其输入也可以使用多位总线，此时将执行按位异或运算。 + 异或非门 + 异或门和非门的组合。 + 非门 + 翻转输入，1 变为 0,0变为 1。 + 其输入和输出也可以使用多位总线，此时将执行按位非运算。 + 非门的输入 + 翻转后的输入值 + 查找表 + LUT + 从一张存储表中获取输出，该组件可以模拟任何组合电路。 + 输入 {0}，和其他输入共同定义将要返回的所存储内容地址。 + 根据指定的输入组合，返回对应的存储值。 + 延迟 + 延迟信号传输。Digital 中的所有组件具有相同的传输延迟单位，该组件用于实现必要的传输延迟。 + 将要延迟的输入信号 + 经过延迟的输入信号(默认一个延迟单位) + 输出 + 用于在电路中显示输出信号。也用于连接子电路。 + 当用于生成 CPLD 或 FPGA 代码时，用于为其赋值管脚编号。 + 用于连接输出 + LED + 用于可视化输出信号，仅接受 1 位值，当输入为 1时灯被点亮。 + LED 输入，仅接受 1 位值，当输入为 1时灯被点亮。 + RGB-LED + RGB LED，其颜色通过3个输入信号控制，每个输入表示一个颜色通道。 + 红色通道 + 绿色通道 + 蓝色通道 + 输入 + 可以通过鼠标交互操作输入信号。也用于连接子电路。 + 当用于生成 CPLD 或 FPGA 代码时，用于为其赋值管脚编号。 + 给出连接到该输入的值 + DIP开关 + 简单的DIP开关，可以输出高或低电平 + 开关的输出值 + 时钟输入 + 时钟信号，可以通过实时时钟进行控制。 + 如果频率大于50赫兹，导线的颜色将不会更新。如果没有使用实时时钟，可以通过鼠标单击控制时钟信号。 + 当生成 CPLD 或 FPGA 代码时，用于为其赋值管脚编号。 + 根据设置的时钟频率在0和1间切换 + 按钮 + 一个简单按键，当释放时回到其初始的状态 + 按键输出信号 + 带有LED的按钮 + 一个简单按键，当释放时回到其初始的状态。 + 按键有一个LED，可以通过输入信号进行开关。 + 按键输出信号 + 控制LED的输入信号 + Text + 显示一段文本，其对电路仿真没有影响，可以通过其属性对话框修改文本内容。 + 矩形 + 显示一个矩形，其对电路仿真没有影响。 + 如果使用 - 作为标题，将不会显示标题。 + 探测器 + 测量值可以通过数据图或测量表显示，该组件可用于观察子电路中的值。 + 需要测量的值 + 灯泡 + 灯泡具有两个连接点，当电流经过时灯泡变亮。 + 不关心电流的方向。当输入为不同的值时点亮，行为类似异或门。 + 连接点 + 连接点 + 发光二极管 + LED 区分阴极和阳极，当阳极连接到高电平且阴极连接到低电平时，LED点亮。 + 阳极 + 阴极 + 7段数码管 + 每段都有自己的控制输入 + 该输入控制顶部，水平线 + 该输入控制顶部，右侧，垂直线 + 该输入控制底部，右侧，垂直线 + 该输入控制底部，水平线 + 该输入控制底部，左侧，垂直线 + 该输入控制顶部，左侧，垂直线 + 该输入控制中间，水平线 + 该输入控制小数点 + 共阴极，如果要点亮 LED，该输入需为低电平 + 共阳极，如果要点亮 LED，该输入需为高电平 + 7段数码管(十六进制输入) + 4位十六进制输入7段数码管 + 将被显示的输入值 + 该输入控制小数点 + 16段数码管 + 通过16位输入控制各段，第二个输入控制小数点 + 16位驱动总线 + 该输入控制小数点 + LED矩阵 + LED矩阵，在独立窗口中显示。 + 通过一个数据字段控制一列LED的开关，另外一个输入为当前列的地址。 + 当前列对应的数据位字，自底向上 + 当前列地址 + 数据图 + 在电路面板显示数据绘图，可以绘制完整的时钟周期或单个门改变，该组件不影响仿真。 + 旋转编码器 + 带旋转编码器的旋钮，用于检测旋转运动。 + 信号A + 信号B + 键盘 + 可以用于输入文本的键盘。 + 该组件缓存输入，然后读取输入作为输出。 + 时钟，上升沿时从缓冲中移除旧的字符 + 如果为高电平，则输出 D 有效，输出一个字符。同时使能时钟输入。 + 最后输入的字符或0(如果没有有效字符)，输出为16位Java字符值 + 该输出信号表示字符有效，用于触发中断。 + 终端 + 可以想向终端写入ASCII字符，该终端打开新的窗口并显示输出。 + 时钟，在上升沿将输入信号的值写入终端 + 将要写入终端的数据 + 高电平使能 + VGA显示器 + 分析输入视频信号并显示对应图形。 + 因为仿真不能实时运行，除了视频信号，还需要像素时钟。 + 红色组件 + 绿色组件 + 蓝色组件 + 水平同步信号 + 垂直同步信号 + 像素时钟 + MIDI + 使用 MIDI 系统播放记录 + 记录 + 音量 + 为1相当于按下按键，为0相当于释放按键。 + 使能 + 如果为高电平，使用 N 值改变程序(仪器) + 时钟 + 单极性步进电机 + 具有两个限位开关的单极步进电机。支持全步驱动，半步驱动和细分(微步)驱动。 + 限位开关0，当电机角度为 0° 时变为高电平 + 限位开关1，当电机角度为 180° 时变为高电平 + 相数 0 + 相数 1 + 相数 2 + 相数 3 + 双极性步进电机 + 具有两个限位开关的双极步进电机。支持全步驱动，半步驱动和细分(微步)驱动。 + 限位开关0，当电机角度为 0° 时变为高电平 + 限位开关1，当电机角度为 180° 时变为高电平 + 线圈 A，正极 + 线圈 A，负极 + 线圈 B，正极 + 线圈 B，负极 + 地 + 用于接地，输出始终为 0 + 输出始终为 0 + 电源 + 用于连接电源，输出始终为 1 + 输出始终为 1 + 常量 + 常量，值在属性对话框设置 + 返回常量设置值 + 隧道 + 不是有导线实现组件连接。所有具有相同名称的隧道网络被认为连接一起。 + 仅在当前电路有效，不能用于不同电路。没有名称的隧道组件被忽略。 + 连接点 + 分裂器/合并器 + 分裂信号或创建总线。 + 输入位 {0} + 输入位 {0} + 输出位 {0} + 输出位 {0} + 双向分裂器 + 可用于数据总线特别是存储器模块的构建 + When set, the value at the common data terminal D is output to the bit + outputs D[i], if not, the bits D[i] are output to the common output D. + The common data connection. + 数据位 {0} + 上拉电阻 + 弱高电平 + 如果一个网络为高阻态，该电阻将网络上拉到高电平，其它时候该组件无效。 + 下拉电阻 + 弱低电平 + 如果一个网络为高阻态，该电阻将网络下拉到低电平，其它时候该组件无效。 + 驱动器 + 用于将信号连接到其它导线。 + 如果 sel 输入为低电平，输出为高阻状态，如果 sel 为高电平，输出等于输入。 + 输入 + 输出 + 控制位 + 驱动器(低电平有效) + 用于将信号连接到其它导线。 + 如果 sel 输入为高电平，输出为高阻状态，如果 sel 为低电平，输出等于输入。 + 输入 + 控制位 + 输出 + 双向管脚 + 该组件仅在生成 VHDL 或 Verilog 时有效，用于创建双向端口。该组件只能在顶级电路使用。 + 待输出数据 + 使能输出 + 待读取数据 + 实际管脚连接点，只有一个输出可以连接到该端口 + 复用器 + 根据 sel 端口选择哪个输入可以通过 + 输入端口 {0} + 输出 + 选择端口 + 多路分配器 + 根据 sel 将输入值给到某个输出端口 + 选择端口 + 输入端口 + 输出端口 {0} + 解码器 + 仅有一个选中的输出端口为高电平，其它输出为低电平. + 输出端口 {0} + 选择端口 + 位选择器 + 在数据总线中选择某一位 + 输入总线 + 选择端口 + 输出端口 + 优先级编码器 + Priority + 当输入只有一个为高电平时，其对应的值被输出。 + 当多个输入为高电平时，输出对应最大的值。 + 输入信号对应的值 + 如果该端口为高电平，则至少有一个输入为高电平 + 输入信号 {0} + SR 触发器 + SR + 用于存储 1 位数据。通过置位和复位来设置存储的数据。 + 如果输入同时为高电平，输出全为低电平。如果输入同时为低电平，输出状态随机。 + 置位 + 复位 + 返回存储的值 + 返回翻转后的存储值 + SR 触发器(时钟控制) + SR + 用于存储 1 位数据。通过置位和复位来设置存储的数据。 + 如果输入在时钟上升沿同时为低电平，输出状态随机。 + 置位 + 时钟输入，在上升沿状态转换 + 复位 + 返回存储的值 + 返回翻转后的存储值 + JK 触发器 + JK + 可以存储(J=K=0), 置位(J=1, K=0), 复位(J=0, K=1)或翻转(J=K=1)存储的内容。 + 状态转换仅在时钟上升沿发生。 + 置位 + 时钟输入，在上升沿状态转换 + 复位 + 返回存储的值 + 返回翻转后的存储值 + D 触发器 + D + 管脚 D 的值在时钟上升沿被存储。可以设置位宽以允许存储多位数据。 + 输入 + 时钟 + 返回存储的值 + 返回翻转后的存储值 + T 触发器 + T + 存储一位，在时钟上升沿切换状态。 + 使能状态切换 + 时钟输入 + 返回存储的值 + 返回翻转后的存储值 + JK 触发器(异步) + JK-AS + D 触发器(异步) + D-AS + 单稳态触发器 + Mono + 寄存器 + Reg + ROM + RAM + EEPROM + P 沟道场效应晶体管 + N 沟道浮动门场效应晶体管 + 测试用例 + 用于定义测试用例，可用于自动检测电路的行为是否符合该定义。 + 异步时序 + 允许设置异步时序电路如Muller流水线的时序。 + 电源连接器 + 复位器 + 复位输出 + Break + 如果检测到上升沿则停止仿真 + External + 通过执行外部程序计算逻辑值。用于通过 VHDL 或 Verilog 定义组件行为。 + 实际的仿真行为由外部仿真器完成。目前支持 VHDL 仿真器 ghdl 和 verilog 仿真器 Icarus Verilog。 + 二极管 + 错误 + 组件 {1} 的管脚 {0} 不是输入或输出 + 需要唯一的时钟组件，所有的触发器必须使用该唯一时钟信号。 + 电路包含没有标签的输入端口 + 电路包含没有标签的输出端口 + No break detected after {0} cycles at break point ''{1}''. + Possibly the number of timout cycles in the break component should be increased. + 不支持表达式 {0} + 不支持操作 {0} + 创建查找表时遇到错误 + 在一条导线上存在多于一个输出信号导致短路。 + 不能将上拉和下拉电阻连接到同一网络 + 不能分析结点 {0} + 包含 [var] 和 [not var] + 管脚 {0} 在组件 {1} 中重复 + 未发现组件 {0} + Exact {0} valoas necessary, not {1} + 触发器必须连接到时钟信号 + 文件格式无效 + 逻辑值已经初始化 + 隧道组件 {0} 未连接！ + 多于一个时钟信号 + 时钟组件未使用！ + 需要 {0} 位，但只有 {1} + 找不到管脚 {0} 的网络 + 找不到时钟 + 地址位数 + 地址线位数 + 数据位数 + 数据线位数 + 颜色 + 组件的颜色 + 背景色 + 当嵌入其它电路时的电路背景色 + 超时周期 + 如果设置的周期数完成而没有中断信号则会报错。 + 数据 + 存储在该组件中的值 + 默认 + 电路仿真开始时的默认值。 + 默认值 + 电路仿真启动时的默认值，"Z" 表示高阻状态。 + 允许三态输入 + 如果勾选，则输入信号允许高阻状态，其控制输入组件的默认值是否可以设为 "Z" + 非零输出 + 简介 + 关于该组件和其使用的简短描述 + 频率/赫兹 + 实时时钟频率 + 使用 IEEE 91-1984 外观 + 使用 IEEE 91-1984 形状代替矩形 + 输入端口数 + 输入端口个数，所有的输入端口都必须被连接。 + 标签 + 该组件的名称 + 大小 + 形状大小 + 语言 + 图形界面的语言，需要重启才能生效 + 网络名称 + 所有具有相同名称的网络连在一起。 + 输入分割 + 数字格式 + 显示数字的格式 + ascii + bin + decimal + signed decimal + default + hex + octal + 模式 + 方向 + 设置方向 + 左 + 右 + 最大显示步数 + 存储值的最大数，如果达到最大数，旧的值将被忽略。 + 旋转 + 组件在电路中的旋转角度 + 镜像 + 镜像组件 + 使用实时时钟 + 如果选中，当电路开始模拟时将使用实时时钟 + 仿真启动时显示测量图 + 当仿真开始时，包含测量值的图形将被显示。 + 在测量图中显示 + 在测量图中显示值 + 在仿真开始时显示测量值 + 当仿真开始时，包含测量值的表将被显示。 + 行数 + 显示的行数 + 每行字符数 + 每行字符数 + 作为测量值 + 如果选中，该值将作为测量值在测量图和数据表中显示。此时，必须指定标签作为值的标识。 + 测试数据 + 宽度(像素) + 使用像素描述的屏幕宽度 + 高度(像素) + 使用像素描述的屏幕高度 + 可编程存储器 + 设置 ROM 为可编程存储器，这样就可以通过外部 IDE 访问。 + 程序计数器 + 已编程 + 如果选中，二极管(熔丝)为已烧写，浮动门场效应晶体管为已充电。 + 可以通过快捷键 ‘p’ 修改设置。 + 格式 + 表达式格式 + 共极性 + 如果设置，将会仿真共阴极或共阳极 + 共 + 共极性 + 阴极 + 阳极 + 避免闪烁 + ATF15xx Fitter + 包含Microchip(ATMEL)fit15xx.exe 文件的路径 + 管脚编号 + 为空表示该信号不会被分配给某个管脚 + 行数 + 行数 + 列地址位数 + 单个列的地址，3位表示8列。 + 电路被锁定 + 电路被锁定 + 管脚编号 + 管脚的编号，用于表示电路的 DIL 封装和生成 CPLD 代码时分配管脚。 + 如果具有多位，所有的管脚编号可以表示为逗号分割列表。 + 管脚数 + 管脚数，0表示自动确定管脚数 + 应用启动时显示组件树 + 如果选中，应用启动时会在左侧显示组件树 + 翻转输入 + 选择需要翻转的输入信号 + 菜单字体大小(百分比) + 菜单字体大小，相对于默认大小的百分比 + 允许输入 + 如果设置，将使能输入端口 T + 单向 + Active Low + If selected the output is low if the component is active. + 库 + 包含预定义的子电路，还可以在当前路径下添加自定义电路。 + 显示栅格 + 在主窗口中显示栅格 + 导线提示 + 如果选中，当鼠标划过时导线会高亮 + 映射到键盘 + 按钮被映射的键盘。使用 UP, DOWN, LEFT 或者 RIGHT 作为标签以使用方向键。 + Java 库 + 使用java实现的额外组件jar文件。 + 在总线上显示导线数。 + 注意：值仅在仿真启动后更新。 + 输入位宽 + 输出位宽必须大于输入位宽 + 输出位宽 + 输出位宽必须大于输入位宽 + 字体大小 + 设置文本字体大小 + 时长 + 延迟时间，单位为常见门的传输延迟。 + 翻转输出 + 如果选中，输出将被翻转。 + 脉冲宽度 + 用时钟周期表示的脉冲宽度 + 间距 + 设置输入和输出端口间距 + ROM 内容 + 所有使用的 ROM 中的内容 + 应用 + 定义使用哪个应用 + 通用 + GHDL + IVerilog + 输入 + 输出 + 程序代码 + 被外部应用执行的程序代码 + 选项 + GHDL + GHDL 选项 + 用于处理 GHDL 的选项 + IVerilog + Icarus verilog 安装路径 + 最大值 + 如果为 0，则使用可能的最大值 + 输出为高电平 + 默认输出 + 使用 MacOS 鼠标单击 + 使用 CTRL+左键 代替右键单击。 + 在主面板中不显示工具提示 + 如果选中，将不会在主面板中显示组件的工具提示。 + 显示自动重命名隧道组件对话框 + 如果选中，当一个隧道组件被重命名后，将会显示为同名隧道组件自动重命名的对话框。 + ATMISP + 可执行文件ATMISP.exe的路径。设置后，ATMISP 软件可以被自动启动！ + 自定义形状 + 导入 SVG 文件 + 在启动时预加载程序到存储器 + 当仿真一个使用 RAM 作为程序存储器的处理器时，因为 RAM 内容被初始化为零，因此很难启动处理器。 + 该设置允许在处理器启动时加载数据到程序存储器。 + 程序文件 + 在仿真开始时被自动加载进存储器的程序文件 + 宽 + 以栅格为单位的宽度 + 高 + 以栅格为单位的高度 + 内置文本 + 将文本放在矩形内部 + 底部文本 + 将文本放在矩形底部 + 右侧文本 + 将文本放在矩形右侧 + 宽形 + 使用较宽的形状显示门 + 形状 + 当电路作为子电路时的形状。 + “Simple” 模式：输入管脚显示在一个简单矩形左侧，输出管脚显示在一个简单矩形右侧。 + “Layout” 模式：管脚的位置由实际电路中输入、输出组件的位置和方向决定。此时，管脚可以位于顶部或底部。 + “DIL-Chip”模式：使用双列直插封装外形显示电路，输入、输出组件的管脚编号决定管脚的位置。 + 默认 + Simple + DIL-Chip + Layout + 自定义 + 文本对齐 + 文本对齐方式 + 左下角 + 居中偏下 + 右下角 + 居中偏右 + 右上角 + 居中偏上 + 左上角 + 居中偏左 + 正中 + 启用 + 启用或禁用该组件 + 工具链配置 + 用于配置集成工具链，如启动外部工具，对 FPGA 进行编程 + 通用参数 + 通用化电路的代码 + 通用电路 + 创建一个通用电路 + 启动时显示使用指南 + 开启使用指南 + SVG 导出设置 + 隐藏测试用例 + 不导出测试用例 + 不填充形状 + 多边形不会被填充 + 输入和输出表示为小圆圈。 + 忽略管脚标注 + 符号中蓝色和红色的管脚标注会被忽略。 + 高对比度 + 导线和管脚的文本显示为黑色。 + 单色 + 仅使用灰色。 + 细线 + 如果选中，绘制的线会比较细 + 对齐到栅格 + 如果选中，组件将会和栅格对齐。 + 管脚间距 + 用于 layout 外观，设置和前一个管脚的距离。 + 插入导线 + 从剪切板插入 + 组件 ''{1}'' 中的 ''{0}'' 值被修改 + 修改组件 ''{0}'' 属性 + 删除导线 + 移动或旋转组件 ''{0}'' + 移动导线 + 删除选中 + 插入组件 ''{0}'' + 删除组件 ''{0}'' + 插入导线 + 移动选中组件 + 撤销: {0} + 恢复: {0} + 修改电路属性 + 排序测量值 + 修改所选组件属性 + 分割单个导线为两个 + 逻辑 + 运算器 + 触发器 + 输入输出 + 存储器 + 复用器 + 导线 + 开关 + 显示 + 机械 + 外设 + 其他 + 更多 + 窗口 + 关于 + 分析 + 分析当前电路 + 剪切 + 复制 + 自定义 + 库 + 删除组件 + 删除选中的组件 + 编辑 + 设置当前电路 + 该电路设置影响当前打开电路的行为，例如当电路作为子电路被其他电路使用时的形状， + 这些设置和电路文件保存在一起。 + 设置 + 全局设置，包括仿真器、界面语言、符号、外部工具等。 + 停止仿真 + 停止仿真并允许编辑电路。 + 组件 + 导出 + 导出 PNG(大) + 导出 PNG(小) + 导出 SVG + 导出 GIF 动画 + 运行至中断 + 运行电路直至中断(BRK)组件检测到断点。 + 文件 + 帮助 + 更新 + 更新组件菜单。 + 适合窗口 + 单门仿真 + 使用单步模式运行电路 + 新建 + 新建一个空电路 + 新建子电路 + 打开新窗口并创建一个子电路，然后可以在当前电路中使用该子电路 + 打开 + 打开最近使用 + 在新窗口打开最近使用 + 在新窗口中打开 + 在新窗口中打开电路 + 排序输入信号 + 排序输入信号(作为子电路使用时) + 排序测量值信号 + 排序在图形和表格视图中的测量值信号 + 排序输出信号 + 排序输出信号(作为子电路使用时) + 粘贴 + 旋转 + 仿真 + 启动仿真 + 启动仿真电路 + 保存 + 另存为 + 保存数据 + 保存数据为 CSV 文件 + 电路速度测试 + 通过计算最大时钟频率进行运算速度测试 + 单门步进 + 运行单个门 + 运行至中断 + 执行所有的单门步骤直至中断组件检测到上升沿。 + 如果没有中断组件，则执行剩余所有单门步骤。 + 综合 + 为真值表生成最简布尔表达式 + {0} 变量 + 创建 + 电路 + 根据真值表创建对应电路 + 基于 JK 触发器的电路 + 使用 JK 触发器电路表示真值表 + 基于查找表的电路 + 使用查找表电路表示真值表 + 基于与非门的电路 + 基于2输入与非门的电路 + 仅使用2输入与非门创建电路 + 仅使用与非门电路表示真值表 + 基于或非门的电路 + 基于2输入或非门的电路 + 仅使用2输入或非门创建电路 + 仅使用或非门电路表示真值表 + 基于2输入门的电路 + 仅使用2输入门创建电路 + 基于3输入门的电路 + 仅使用最多3输入的门创建电路 + 器件 + 为器件创建 JEDEC 文件 + 导出 LaTeX + 导出测试用例 + 创建用于测试用例的描述 + 测试用例仅在电路为纯组合电路时可用 + 导出十六进制文件 + 可用将十六进制文件载入 ROM 或查找表 + 新建 + 组合电路 + 时序电路 + 双向时序电路 + 重新排序或删除输入变量 + 重新排序或删除输出列 + 添加输出列 + 在表中添加新的结果列 + 添加输入变量 + 在表中添加新的输入变量 + 将 X 设为 0 + 将 Don't Cares 设为 0 + 将 X 设为 1 + 将 Don't Cares 设为 1 + 创建 J/K 表达式 + 将值全部设为 X + 将值全部设为 "don't care" + 将值全部设为 0 + 将值全部设为 0 + 将值全部设为 1 + 将值全部设为 1 + 翻转所有位 + 将 "1" 变为 "0"，"0" 变为 "1"，Don't cares保持不变。 + 显示结果对话框 + 如果结果对话框被手动关闭，则重新显示。 + 删除 + 删除终端内容 + 视图 + 放大 + 缩小 + 表达式 + 从表达式创建电路 + 运行测试用例(当前电路) + 运行当前电路中的所有测试用例 + 设置默认输入信号 + 将当前实际输入值设为默认输入值 + 重置二级管和浮动栅场效应晶体管状态 + 将所有二极管(熔丝)和浮动栅场效应晶体管设为 "非编程" 状态，实际的配置将会丢失。 + 组件信息 + 显示可用组件列表 + 帮助对话框 + 显示描述当前电路的帮助对话框 + 在新窗口粘贴 + 在新窗口粘贴剪切板内容 + 组件树视图 + 在左侧以树视图显示可用组件 + 针对 74xx 电路的功能 + 添加输入输出信号前缀 + 移除输入输出信号前缀 + 移除输入输出信号标签的第一个字符 + 管脚向导 + 为输入和输出信号添加管脚编号向导 + 移除管脚编号 + 移除电路中所有管脚编号 + 撤销 + 还原上次修改 + 重做 + 再次应用上一次还原的修改 + 显示图 + 以图方式显示数据 + 显示表格 + 以表格方式显示值数据 + 添加电源 + 为电路添加电源 + 导出 VHDL + 导出电路为 VHDL + 导出 Verilog + -导出电路为 Verilog + 卡诺图 + 以卡诺图表示当前表格 + 使用文档 + 打开 {0} + 显示测量值表格 + 在新窗口中显示带有测量值的表格 + 显示测量图 + 在新窗口中显示测量图 + 导出为 ZIP 文件 + 导出电路为 ZIP 压缩文件，该压缩文件包含所有电路功能需要的必要文件 + 标签化输入输出信号 + 为所有没有标签的输入输出信号自动添加标签 + 使用指南 + 打开新手使用指南 + 电路统计 + 显示所有已使用组件的列表 + 数量 + 组件 + 输入 + 位 + 地址位 + 打开 PDF 文件时遇到错误！ + <h1>Digital</h1>一个简单的数字电路仿真器 + 作者： H. Neemann 2016-2020 + + 所用图标来自 <a href="http://tango.freedesktop.org">Tango Desktop Project</a> + + 在 <a href="https://github.com/hneemann/[[name]]">GitHub</a> 查看该项目，并<a href="https://github.com/hneemann/[[name]]/releases/latest">下载</a>最新的发行版 + + 可以在这里提交<a href="https://github.com/hneemann/[[name]]/issues/new?body=version:%20[[version]]&labels=bug">问题</a>或<a href="https://github.com/hneemann/[[name]]/issues/new?labels=enhancement">建议</a> + {0} 结点 + 分析电路时遇到错误 + 时钟状态改变时遇到错误 + 颜色 + 新建电路时遇到错误 + 化简电路时遇到错误 + 创建硬件配置时遇到错误 + 编辑属性时遇到错误 + 导入电路 {0} 时遇到错误！ + 更新组件库遇到错误！ + 读取文件时遇到错误 + 未知命令 {0} + 写入文件时遇到错误 + 最大频率为 {0} kHz + 形状 {0} 丢失 + 管脚分配 + 管脚 {0}: {1} + 当前更改需要重启生效！ + 输入表达式： + 运行测试时遇到错误： + 测试结果 + {0} 通过 + {0} 失败 + (To many entries!) + 所有测试用例已执行，但没有显示所有结果。然而，对测试结果的评估是正确的！ + E: {0} / F: {1} + 创建帮助时遇到错误！ + 剪贴板包含不可导入数据！ + 请选择空文件夹！ + Message from the external fitter + Execution of external fitter + 实际电路 + 文件不可导入！可能存在同名文件？ + 文件名不唯一！工作目录和子目录下的所有文件必须具有唯一的文件名。 + 存在同名文件： + and {0} more. + 文件尚未导入 + 文件 {0} 已存在！是否覆盖当前文件？ + 已禁止编辑电路。你可以在 "{0} -> {1} -> {2}" 移除锁定 + 测试运行速度遇到错误！ + 管脚 {0} + 编号向导 + 选择管脚 {0}: + 写入帧：{0} + 写入 GIF 文件错误！ + 完成 + GIF 文件结束并关闭 + 导出 GIF + 由于 + 待翻转输入 + 未设置 + 不能确定管脚名称 + 发生在文件 {0}。 + 受影响组件： {0} + 信号 {0} + 管脚 {0} 未指定管脚编号！ + 仅当电路没有错误时才可导出！ + 无有效 KV 图！ + 数据不会被更新 + 修改当前值 + 包含无效数据字段！ + 创建 CHN 文件。 + 当前表非常大，导出需要些时间。确认导出？ + 必须先创建和分析电路，不能使用独立的真值表生成硬件描述。 + 没有数据 + 不能关闭外部进程！ + 测试结果： + 测试 + 启动应用以测试输入代码是否正确。 + 不能自动创建输入和输出端口，请检测设置！ + 未发现可执行文件 "{0}" + 输入文本！ + 启动 ATMISP + 启动外部程序 ATMISP。 + 启动 ATMISP 遇到错误！ + ATMISP 在继续运行！当关闭当前对话框，ATMISP 被终止。 + 运行所有测试(当前目录) + 对当前目录下的所有电路进行测试 + {0} 测试行通过 + 测试文件 + 真值表 + 剪贴板 + 复制文本到剪贴板。 + 确定 + 0° + 180° + 270° + 90° + 删除选中内容 + 下移该项 + 上移该项 + 所有可能方案 + 测试数据 {0} + 数据 + 确认退出 + 测量 + 保存变更？ + 内容已更改 + 表 + 导出 + 选择 + 输入 {0} + 卡诺图 + 帮助 + 居中 ROM 内容 + 表达式 + 测试向量 + 有限状态机 + no movement + Transitions + Transitions+States + 设置 {0} + 有限状态机 + 打开有限状态机编辑对话框 + 创建 + 状态转换表 + 创建计数器 + {0} 状态 + 有限状态机编辑器使用帮助 + 状态码 + 表示该状态的数字 + 初始状态 + 如果设置，则该状态为初始状态 + 输出 + 条件 + 布尔表达式 + 半径 + 图中圆的半径 + 载入文件遇到错误！ + 存储文件遇到错误！ + 转换 + 状态 + 新状态 + 不能创建状态转换表 + 有限状态就编辑器帮助 + 测量图 + 使用指南 + 在接下来的指南中，我们将完成第一个简单的电路： + 首先，在电路中添加一个输入组件，我们可以通过 组件▸输入输出 菜单找到该组件。 + 现在向电路中添加第二个输入组件。 + 最好将第二个输入组件放置在第一个组件的下面。我们可以通过按住鼠标右键来移动电路，单击组件来移动相应组件。 + 接下来，添加一个异或门。可以通过 组件▸逻辑 菜单找到该组件。将该组件放置到输入组件的右侧，保持适当距离。 + 最后要添加的组件为输出组件。 + 将其放置在异或门的右侧，保持适当距离。 + 为完成电路，必须绘制连接导线。 + 点击第一个输入组件的红色点，然后点击异或门的一个蓝色点来连接到异或门的输入。 + 连接第二个输入组件的红色点到异或门的第二个蓝色点，连接异或门的红色点到输出组件的蓝色点。 + 当绘制导线时，单击可以固定导线，右击取消绘制。 + 你的第一个电路此时已可正常工作。 + 要仿真电路，点击工具栏中的 “启动仿真” 按钮，如果移动鼠标到工具栏，相应的提示会显示。 + 此时仿真已开启，单击输入组件可以切换输入值。 + 点击工具栏中 “停止仿真” 按钮来定制仿真。 + 继续完成，需要给输入和输出添加标签。 + 在输入组件上右击打开对话框，在 MacOS 上使用 control+单击，这时可以给输入组件命名。 + 为所有输入和输出添加标签 + 输入和输出名称必须唯一 + 跳过使用指南 + 能够存储(J=K=0), 置位(J=1, K=0), 复位(J=0, K=1)或翻转(J=K=1)存储的内容。 + 状态仅能够在时钟上升沿发生改变。另有两个额外的输入可以立即改变状态而不需要时钟信号。 + 置位 + 时钟输入 + 复位 + 返回存储的值 + 翻转后的存储值 + 异步置位，输入高电平将置位触发器 + 异步复位，输入高电平将复位触发器 + 管脚 D 的值在时钟上升沿被存储。可以设置位宽以允许存储多位数据。 + 另有两个额外的输入可以立即改变状态而不需要时钟信号。 + 输入 + 时钟，上升沿触发 + 输出 + 翻转后的输出 + 异步置位，输入高电平将置位触发器 + 异步复位，输入高电平将复位触发器 + 单稳态触发器(monoflop)，在时钟上升沿置位。 + 在经过一个可配置的延迟后，自动复位。该单稳态触发器可重复触发。电路中必须存在唯一的一个时钟组件， + 时钟组件作为测量时间延迟的基准。 + 复位输入，高电平有效 + 时钟输入 + 输出 + 翻转后的输出 + 没有可用输入 + 未找到适用于组件 {0} 的形状 + Nothing connected to input ''{0}'' at component ''{1}''. Open inputs are not allowed. + 所有连接的输出必须具有相同位宽 + 如果允许多个输出信号连接，所有输出必须为三态输出。 + 导线 {0} 未连接到任何输出，状态未定义。 + 至少需要一个结果！ + 输出 {0} 未定义 + 管脚 {0} 没有标签 + 管脚 {0} 重复！ + 管脚 {0} 不是输入！ + 管脚 {0} 不是输出！ + No = found! + 太多输入！ + 太多输出！ + 管脚不存在 + 发现没有定义标签的管脚！ + 需要为时钟信号定义标签。 + 组件 {1} 没有管脚 {0} + 未发现管脚 {0} + 自定义形状未定义管脚 {0} + 未知管脚 {0} + Logic seems to oscillate. + To analyse you can run the circuit in single gate step mode. + 远程端口被占用！是否有其它实例正在运行？ + 输入端口数和选择位数不匹配 + 分裂器 {0} 包含语法错误 + 分裂器位数不匹配 + 所有输入位必须定义！ + 输入位重复定义！ + 分裂器仅允许 64 位！ + 需要两个输入！ + 太多变量，最多允许 {0} 个，但发现 {1} 个。 + {0} 中包含太多变量，最多允许 {1} 个，但发现 {2} 个。 + CUPL 中不允许变量 {0}！ + 变量 {0} 未定义 + 意外的 Token {0} + 缺少右括号 + 第 {1} 行中的 {0} 不是数字！ + Expected {0} but found {1} values in line {2}! + Unexpected token ({0}) in line {1}. + 变量 {0} 不存在 + 测试向量未定义输入信号！ + 测试向量未定义输出信号！ + 未发现测试数据。 + 执行远程命令遇到错误 + 可以设置数据位宽度，和D触发器不同，该寄存器具有使能输入。 + 输入 + 时钟输入，上升沿触发 + 使能输入，高电平有效 + 返回存储内容 + 非易失存储器。可以通过属性对话框编辑存储内容。 + 地址位 + 输出使能 + 如果输入为高电平，输出使能，如果输入为低电平，输出为高阻态。 + RAM(独立端口) + RAM + 拥有独立的数据输入存储端口和数据输出读取端口的RAM。 + 输入和输出共用地址位 + 时钟输入 + 输入数据 + 输出数据 + 输出使能，高电平有效，当为低电平时，输出呈高阻态 + 输入使能，高电平有效 + Block-RAM(独立端口) + 该 RAM 输出仅在时钟上升沿更新，用于 FPGA 的块内存。 + 输入和输出共用地址位 + 时钟输入 + 输入数据 + 输出数据 + 输入使能，高电平有效 + EEPROM(独立端口) + 拥有独立的数据输入存储端口和数据输出读取端口的EEPROM。 + 输入和输出共用地址位 + 时钟输入 + 输入数据 + 输出数据 + 输出使能，高电平有效 + 输入使能，高电平有效 + RAM(双向端口) + RAM + 拥有一个既可用作数据输入，又可用作数据输出端口的RAM。 + 输入和输出共用地址位 + 时钟输入 + 双向数据端口 + 输出使能，高电平有效 + 输入使能，高电平有效 + RAM(片选) + RAM + 拥有一个既可用作数据输入，又可用作数据输出端口的RAM。 + 如果片选输入(CS)为低电平，组件被禁止。用于通过使用较小容量的RAM和地址解码器构造较大容量的RAM。 + 输入和输出共用地址位 + 输入使能，高电平有效 + 双向数据端口 + 片选使能，输入为高电平时，RAM可用，否则输出为高阻态。 + 输出使能，高电平有效 + EEPROM + 拥有一个既可用作数据输入，又可用作数据输出端口的EEPROM。 + 如果片选输入(CS)为低电平，组件被禁止。 + 输入和输出共用地址位 + 输入使能，高电平有效 + 双向数据端口 + 片选使能，输入为高电平时，EEPROM可用，否则输出为高阻态。 + 输出使能，高电平有效 + RAM + 一个端口可以读写，另一个端口只读的RAM。 + 第二个端口可用于图形逻辑访问。此时，处理器写数据到RAM，图形逻辑同时读取数据。 + 输出端口 1 + 输出端口 2 + 用于端口 1 读取和写入数据的地址位 + 用于端口 2 读取和写入数据的地址位 + 时钟输入 + 输入数据 + 输出使能，高电平有效，用于输出端口 1 + 输入使能，高电平有效 + Register File + Register + 计数器 + Counter + 计数器(可预设) + 关闭 + 设置开关的初始状态 + 值 + 常量的值 + 宽度 + 当电路作为子电路时，电路符号的宽度 + 高度 + 当电路作为子电路时，电路符号的高度 + 模型启动时重新载入 + 每次模型启动时重新载入十六进制文件 + 翻转选择管脚位置 + 将选择管脚移到对面的位置 + 使用 LaTeX 格式表示文本 + 使用 LaTeX 格式表示文本 + 数据模式命名管脚标签 + 即使不包含索引，仍然使用数学模式命名管脚标签 + 缩小输入和输出管脚 + 使用等号按键 + Use the equal key instead of the plus key. + This is always useful if the plus character is not a primary key, but the second assignment of the + equals character, e.g. for an American or French keyboard layout. + RAM + EEPROM + 根据电路创建 CUPL 源文件 + 根据电路创建 BLIF 文件，然后启动 Atmel fitte 创建 JEDEC 文件。 + 编程二极管(熔丝) + 存储器 + 显示存储器内容 + 为所有选中的输入和输出添加前缀，用于简化复制 74xx 电路。 + 执行单步时遇到错误 + Error at fast run + 导入 SVG 文件时遇到错误 + 创建 SVG 模板时遇到错误 + 不能创建统计 + 读取工具链配置 {0} 时遇发生错误 + 命令 "{0}" 已启动，处理可能需要些时间！ + 命令 "{0}" 已完成！ + 重命名网络 + 还有 {0} 个网络名为 ''{1}'' 的隧道组件，是否重命名所有组件为 ''{2}''？ + 确定忽略 "{0}" 字段中的修改？ + Break after {0} half cycles at break point ''{1}''. + 全时钟测量 + 单门测量 + 包含 ROM + <html> + <h3>Motivation</h3> + When a circuit containing a ROM component is embedded multiple times, the contents of the ROM + is normally used for each instance of that circuit. Under certain circumstances, + however, it may be desirable for such a circuit to be embedded multiple times, + but different ROM contents are used for each instance.<br/> + This problem occurs e.g. if a 74xx ROM is used multiple times but with different + memory contents.<br/> + <h3>Function</h3> + At this location, therefore, contents can be defined for all ROM's in the circuit. + When the simulation model is generated, every ROM is initialized with the contents stored + directly in the respective ROM. Then it is checked whether an alternative content is + defined here. If this is the case, the content defined here is loaded into the corresponding ROM. + <h3>Usage</h3> + It should be noted that each ROM requires a unique name used to identify the ROM. + To do this, use the asterisk ('*') in the label of the ROM. The asterisk is then replaced by the complete + path constructed from the names of the embedded circuits. + If a circuit contains only one ROM component, it is sufficient to use only the asterisk as a label for it. + All embedded circuits must be named so that a unique name can be formed for each ROM component. + </html> + <html> + <h1>新版本 {0} 可用</h1> + <p>发现新的仿真器</p> + <p>在这里 <a href="https://github.com/hneemann/[[name]]/releases/latest">发行说明</a> + 你可以查看有哪些功能变更。</p> + <p>也可以直接 <a href="https://github.com/hneemann/[[name]]/releases/latest">下载</a> 最新版本</p> + </html> + To define an expression you can use all most common notations: + + And: "&", "&&", "*", "∧" + Or: "|", "||", "+", "∨", "#" + XOr: "^", "⊻" + Not: "!", "~", "¬" + + As usual AND precedes OR and XOr. + + Multiple expressions can be separated by "," or ";". + If you want to name the expressions you can use the + let-command: "let U=A+B, let V=A*B" + <html> + <head><style>pre { background-color: #E0E0E0;}</style></head> + <body> +<p>The first line has to contain the names of inputs and outputs. +The following lines contain the expected values. +A 'X' represents a don't care, and a 'Z' represents a high Z value. +If a 'C' is used, at first all other values are set, after that a clock cycle is performed and than the +values are compared. So it's easier to test sequential logic. +A line which starts with a number sign ('#') is a comment.</p> + +<p>So a test for a 2-bit counter could look like this:</p> + +<pre> +C Q1 Q0 +0 0 0 +C 0 1 +C 1 0 +C 1 1 +C 0 0 +</pre> + +<p>The tests are executed by Run->Run Tests.</p> +<p> +To make it easier to create a lot of test vectors there is the 'repeat([n])' statement: +If a line begins with 'repeat([n])', [n] test lines are generated. The +Variable 'n' can be used to generate the test data. With 'repeat(16)' +16 lines are created, where n goes from 0 to 15. If there are multiple bit inputs, +and these are to be set together to a binary value, this can be done with the +'bits([bits], [value])' statement. This is used to create [bits] bits of the value [value].</p> + +<p>The following is an example that tests a 4-bit adder:</p> + +<pre> + C_i-1 A_3 A_2 A_1 A_0 B_3 B_2 B_1 B_0 C_i S_3 S_2 S_1 S_0 +repeat(256) 0 bits(4,n>>4) bits(4,n) bits(5,(n>>4)+(n&15)) +repeat(256) 1 bits(4,n>>4) bits(4,n) bits(5,(n>>4)+(n&15)+1) +</pre> + +<p>The input signals are the carry-in (C_i-1) and the eight input bits A_3-A_0 and B_3-B_0. +The 4 input bits are generated with the 'bits' instruction. The result (C_i, S_3-S_0) is also generated +by a 'bits' instruction. +This happens once with C_i-1 = 0 and in the next line with C_i-1 = 1. +In this way, 512 test rows are generated which cover all possible input configurations.</p> +<p>If multiple rows are to be repeated, or if nested loops are required, the loop +statement can be used. The above example could also be implemented as follows:</p> + +<pre> + C_i-1 A_3 A_2 A_1 A_0 B_3 B_2 B_1 B_0 C_i S_3 S_2 S_1 S_0 +loop(a,16) + loop(b,16) + 0 bits(4,a) bits(4,b) bits(5,a+b) + 1 bits(4,a) bits(4,b) bits(5,a+b+1) + end loop +end loop +</pre> + +<p>It may be helpful to generate random numbers in test cases. +These can be created with the function 'random([n])'. The generated number is greater +than or equal to zero and less than [n]. Considering a 16-bit multiplier as an example, +a full test can not be performed since it would have 2^32 input combinations. +A regression test that multiplies 100000 random numbers might look like this:</p> + +<pre> + A B Y +loop(i,100000) + let a = random(1&lt;&lt;16); + let b = random(1&lt;&lt;16); + (a) (b) (a*b) +end loop +</pre> + +<p>An input that allows high impedance as a value can also be used as a test output. +In this case, the signal name can be used with a trailing "_out" to read back and check the current value. +For this, the corresponding input must be set to high impedance ('Z').</p> + +<pre>OE CLK D D_out +0 0 0 0 +0 C 1 1 +1 0 z 1 +0 C 0 0 +1 0 z 0 +</pre> + +<p>The circuit for this test has only one input 'D', but which can be high impedance state. +Therefore, the signal 'D_out' is also available to check the value in this case.</p> + +</body></html> + 定义输出值。简单的如 "A=1, B=0"，多位输出，如 "A=101"。 + 未定义的输出状态默认为 0。在状态转换中，为指定的输出保持不变。 + 有限状态机 {0} 不确定 + 状态码 {0} 重复 + 找不到初始状态 + 找不到状态 ''{0}'' + 输出 ''{0}'' 分配错误 + 条件 ''{0}'' 错误 + <html><head></head> +<body> + <h3>Mouse Operation</h3> + <dl> + <dt>Create a state:</dt> + <dd>Right mouse click on a free area.</dd> + <dt>Creating a transition:</dt> + <dd>Right mouse button down on the start state and dragging to the destination state.</dd> + <dt>Delete a state or a transition:</dt> + <dd>Move the mouse over the object and press the [Del] button.</dd> + <dt>Moving a state or transition:</dt> + <dd>Left mouse button down and dragging.</dd> + <dt>Editing a state or a transition:</dt> + <dd>Right mouse click on the state or the transition.</dd> + </dl> + <h3>Layout Help Function</h3> + <dl> + <dt>no movement:</dt> + <dd>The layout help function is disabled.</dd> + <dt>Transitions:</dt> + <dd>The layout help function moves the transition arrows to avoid overlaps.</dd> + <dt>Transitions+States</dt> + <dd>The layout help function moves both states and transitions to help create a well-balanced layout.</dd> + </dl> + <h3>Interpretation of Transitions</h3> + To simplify the generation of a deterministic automata, unconditional transitions are treated in a special way: + an unconditional transition is only executed if no other transition satisfies the transition condition. + So there can be an unconditional transition and conditional transitions that start in the same state. + An unconditional transition thus determines to which state the state machine is shifted if no other transition + condition is met. + If there is no unconditional transition from a state, the state machine will stay in this state if no other + transition condition is met. +</body></html> + <html><body> + <h3>What can be seen in the graph?</h3> + Unlike a real logic analyzer, the X-axis of the measurement graph does not show the time. + Instead a counter is displayed which counts the changes of state in the circuit. + Whenever there is a change in the circuit, the counter is incremented and the new state is displayed.<br/> + You can also think of it as a classic logic analyzer, which does not save any data for optimization + if nothing has changed in the circuit. + However, this also means that it is not possible to read from the graph whether a lot or little time has + passed between two changes in the circuit.<br/> + This behavior is caused by the nature of the simulation: The simulation of the circuit does not know the + concept of time. A change is made to the circuit, and the change in the circuit state is calculated, until + the circuit has stabilized again. Then the next change is made, the effect of which is also is calculated + and so on. These changes are counted and the counter value is displayed on the X-axis of the graph.<br/> + Among other things, this also means that a circuit cannot be overclocked, since the effects of the falling + edge of the clock are not calculated until the circuit has stabilized after the previous rising edge. + </body></html> + 显存 + Gr-RAM + 用于显示位图图形。 + 每个像素都由一个存储器地址表示。存储的值使用固定的调色板定义像素的颜色。实现了两个屏幕缓冲区以支持页翻转。 + 输入B选择显示哪个缓冲区。总存储器大小为 dx * dy * 2。 + 所使用的调色板的结构如下：索引0-9对应于白色，黑色，红色，绿色，蓝色，黄色，青色，品红色，橙色和粉红色。 + 索引32-63映射灰度值，索引64-127表示64个颜色值，其中每个颜色通道有两位。这样产生了一个简单的调色板，该调色板只能用7位寻址。 + 如果支持16位索引，从0x8000开始，则可以使用每个颜色通道5位的高色模式，从而启用32768种颜色。 + 输入和输出共用地址位 + 输入使能，高电平有效 + 时钟输入 + 输出使能，高电平有效 + 选择需要显示的屏幕缓冲区 + 双向数据端口 + RAM(多端口) + 1个写端口，两个读端口的存储器，用于实现处理器寄存器。 + 输出端口 a + 输出端口 b + 输出到端口 a 的寄存器 + 输出到端口 b 的寄存器 + 写寄存器 + 写使能，高电平有效 + 时钟 + 输入数据 + 简单的计数器。时钟上升沿增加计数，通过 clr 输入重置为 0。可通过属性对话框设置计数器位数。 + 时钟输入 + 同步复位，高电平有效 + 溢出位 + 计数输出 + 使能位，高电平有效 + 可预置位的计数器，可以指定最大值和计数方向。 + Counter + 计数输出 + 溢出位，当使能时，如果计数到达最大或递减到 0，则输出 1。 + 时钟输入 + 同步复位 + 使能位，高电平有效 + 计数方向，0 表示递增 + 输入使能，当为 1时 ，输入数据在下一个时钟信号存入计数器 + 数据输入 + 加法器 + Add + 计算输入 a 和输入 b 的和，如果设置进位，则结果加 1。 + 第一个输入 + 第二个输入 + 加法运算结果 + 进位输入，如果为高电平，则结果加 1。 + 输出进位 + 减法器 + Sub + 将二进制输入 a 和输入 b相减，如果进位输入为高电平，则结果减 1。 + 进位输入，如果为高电平，则结果减 1。 + 输入 a + 输入 b + 减法运算结果 + 如果出现溢出，则输出为 1。 + 乘法器 + Mul + 将整数输入 a 和 b 相乘 + 输入 a + 输入 b + 乘法运算结果 + 除法器 + Div + 将整数 a 除以 整数 b。 如果除数为零，则除以1。 在有符号除法中，余数始终为正。 + 被除数 + 除数 + 商 + 余数 + 桶式移位器 + shift + 根据移位输入将数据移位 + 输入数据 + 移位宽度 + 移位后的输出 + 比较器 + 比较二进制输入 a 和 b + 输入 a + 输入 b + 如果 a 等于 b，输出 1 + 如果 a 大于 b，输出 1 + 如果 a 小于 b，输出 1 + 补码器 + Neg + 输入 + 补码输出 + 补码运算 + 符号扩展器 + SignEx + 增加符号数的位宽同时保持值不变 + 输入值，位宽必须小于输出 + 扩展后的输入 + 位计数器 + Bit count + 返回输入值中位为 1 的位数 + 输入 + 包含 1 的位数 + 启动命令 {0} 时遇到错误 + 解析代码时遇到错误 + 未检测到视频模式 ({0}) + 避免输出0。用于设置延迟电路。仅当允许高阻态输出时可用。 + 假设 4位，2位，2位作为输入，可表示为 "4,2,2"。 + 还可以使用 * 号，如 16 位表示为 "1*16"([Bits]*[Number])。还可以直接指定使用的位而不用关心顺序，如 "4-7,0-3"。 + 输入位必须明确且完整的指定。 + 输出分割 + 假设 4位，2位，2位作为输出，可表示为 "4,2,2"。 + 还可以使用 * 号，如 16 位表示为 "1*16"([Bits]*[Number])。还可以直接指定使用的位而不用关心顺序，如 "4-7,0-3"。 + 输出位可以使用多次，如 "0-7,1-6,4-7"。 + 选择位 + 选择位位数 + 补码运算 + 使用补码 + 补码输入 + 输入数据为补码格式 + 桶式移位器模式 + 逻辑 + 环绕 + 算术 + 显示单步 + 在图形中显示所有单步 + 以单步模式显示测量图 + 当仿真启动时，以单步模式显示测量图。 + 测试用例描述，详细的语法可以在测试数据编辑器帮助对话框查看。 + 将该寄存器作为程序计数器。寄存器的值返回给外部汇编器，用来表示当前调试代码行。 + 闭合寄存器 + 输入输入为低电平，继电器闭合 + 极数 + 可用极数 + 不可能将频率增加得太多以至于使闪烁消失。 + 使用此选项，您可以通过保持LED点亮直到公共阴极再次下降来稳定显示，从而模拟高于临界闪烁融合频率的频率。 + 单向晶体管仅将信号从源极传播到漏极。仿真时，比双向晶体管快很多。 + 由于没有从漏极到源极的反馈，因此在这种模式下，晶体管导通时无法使连接的导线短路。此模式对于模拟某些CMOS电路是必需的。 + 外部进程的输入端口。格式为逗号分割的信号名称，对于每个信号，可通过冒号指定位数。如8位加法器的输入可表示为 "a:8,b:8,c_in"。 + 外部进程的输出端口。格式为逗号分割的信号名称，对于每个信号，可通过冒号指定位数。如8位加法器的输出可表示为 "s:8,c_out"。 + 可执行文件ghdl路径。仅当需要使用 ghdl 仿真 vhdl 组件时设置。 + MIDI通道 + 选择需要使用的 MIDI通道 + MIDI 设备 + 选择需要使用的 MIDI 设备 + 允许改变程序 + 增加一个新的输入端口(PC)，如果该输入为高电平，输入端口 N 的值用于改变程序(设备) + 开关行为输入化 + 开关行为类似输入，开对应 0，关对应 1。 + 二极管(上拉) + 用于将导线上拉至VDD，必须将下拉电阻连接到二极管输出。 + 如果输入为高电平，输出则为高电平，其它情况输出为高阻。 + 如果输入为高电平，输出则为高电平，其它情况输出为高阻。 + 二极管(下拉) + 用于将导线下拉至地，必须将上拉电阻连接到二极管输出。 + 如果输入为低电平，输出则为低电平，其它情况输出为高阻。 + 如果输入为低电平，输出则为低电平，其它情况输出为高阻。 + 开关 + 连接点 + 简单的开关，没有门延迟 + 双掷开关 + 双掷开关，没有门延迟 + Fuse + 用于构建一次性可编程存储器 + 连接点 + 连接点 + 继电器 + 继电器是一种可以通过线圈控制的开关，如果电流流过线圈，则开关会闭合或断开。不关心电流方向。 + 控制输入 + 控制输入 + 双掷继电器 + 继电器是一种可以通过线圈控制的开关，如果电流流过线圈，则开关会闭合或断开。不关心电流方向。 + 控制输入 + 控制输入 + P 沟道场效应晶体管 + 栅极 + 源极 + 漏极 + N 沟道场效应晶体管 + N 沟道场效应晶体管 + 栅极 + 源极 + 漏极 + P 沟道浮动门场效应晶体管 + P 沟道浮动门场效应，如果浮栅中存储有电荷，即使栅极为低电平时晶体管也不导通 + 栅极 + 源极 + 漏极 + N 沟道浮动门场效应晶体管，如果浮栅中存储有电荷，即使栅极为高电平时晶体管也不导通 + 栅极 + 源极 + 漏极 + 传输门 + 由两个晶体管构建的传输门 + 输入 A + 输入 B + 控制输入 + 翻转的控制输入 + 用于确保电源和地被连接 + 必须连接到电源 + 必须连接到地 + 在电路初始化期间，该组件的输出保持高电平。电路稳定后，输出变为低电平。 如果输出反相，则其行为相反。 + 如果电路中使用到该组件，则 运行至中断 按钮可用。仅在禁用实时时钟时才能使用此功能！ + 一个理想的二极管：正向偏置二极管两端没有压降。 + 禁止将上拉电阻和下拉电阻连接到同一条导线 + 无法打开浏览器 + 无法创建文件夹 "{0}" + 不可仅连接输入信号到开关 + The file {0} exists multiple times below {1}. + 找不到文件 {0} + 执行 "{0}" 时遇到错误 + 进程 "{0}" 无返回内容！ + 进程返回值非零 {0}: {1} + Error starting the external fitter! + 找不到最简等式！ + 正在计算，请稍等！ + 变量 {0} 重复！ + 文件需要保存！ + 电路 {0} 导入自身！ + 化简结果不正确，变量的名称或不唯一！ + 循环中出现太多迭代！ + 二极管输出需要上拉电阻！ + 二极管输出需要下拉电阻！ + 电路中找不到测试信号 {0}！ + 仅允许 {1} 位数据，但给出 {0} 位！ + 禁止多于 1 位的触发器！ + 传输门的两个控制输入必须反相！ + 信号 {0} 使用多次！ + 解析测试数据遇到错误。 + 不能分析组件 {0} 的模型。 + 电源布线错误 {0} + 管脚编号 {0} 不是整数 + 导出 VHDL 时遇到错误 + 找不到 {0} 的 VHDL 代码！ + 找不到 {0} 的 Verilog 代码！ + 创建测试文件遇到错误！ + 不允许的类型 {0}！ + 缺失名称，是否为所有管脚设置标签？ + 多个输出连接在一起。({0}, {1}, {2}) + 未命名网络 + 太多变量！ + 无效表达式！ + Function {0} not found in line {1}! + Number of arguments in function {0} in line {1} not correct (found {2}, expected {3})! + Invalid value {0} in function {1}! + {0} 不是一个路径元素 + 载入库时遇到错误 + JAR 文件不包含 manifest！ + manifest 文件不包含主类！ + 找不到类 {0}！ + 不能创建类 {0} 的实例！ + 输入位必须多于输出位！ + 禁止设置物理管脚为常量！ + 字符串 {0} 不是有效数字 (pos {1})！ + 不允许名称 "{0}" + TT2文件禁止出现空格！ + 表中包含太多列！ + 创建压缩 zip 时遇到错误。 + 仅允许存在一个高频时钟组件。 + 电路包含环，无法分析当前电路。 + 如果使用单稳态触发器，必须有且也只有一个时钟组件！ + 不能创建组件类型 {0}！ + ROM's defined in the settings are not supported! + 名称 "{0}" 不唯一！ + 无法向外部进程写入值！ + 无法从外部进程读取值！ + 无法创建外部进程！ + 从外部进程读取数据超时！ {0} + 接收数据不足！ + 接收到的文本包含无效字符：{0}! {1} + 进程异常终止！ {0} + 无法结束进程！ + 无法启动进程：{0} + 应用退出状态非零 {0}：{1} + 仅 VHDL 代码可导出！ + 仅 Verilog 代码可导出！ + 如果一个外部组件被使用多次，代码必须相同！影响: {0} + 无法写入 stdOut：{0} + VHDL 仿真器 ghdl 未安装，安装 ghdl (http://ghdl.free.fr/) 并重新尝试。 + Verilog 仿真器 Icarus 未安装，安装 iverilog (http://iverilog.icarus.com/) 并重新尝试。 + 分析电路 {0} 时遇到错误 + 每个 ROM 必须有唯一的标签才能导出！ + 每个 LUT 必须有唯一的标签才能导出！ + 计数器至少需要两位。 + 禁止在异步模式使用时钟组件。 + 导出 Verilog 时遇到错误。 + 未发现程序存储器！ + Error loading the program memory. + 读取 SVG 文件时遇到错误。 + SVG 文件包含电路中不存在的管脚。 + All memories into which data are to be loaded require the same bit width. + If programs are to be loaded into several RAMs, all RAMs must have + different names. The lexical order then determines the order of the RAMs. + MIDI 系统不可用。 + MIDI 通道 {0} 不可用。 + MIDI 设备 {0} 不可用。 + MIDI 设备不可用 + 执行测试 "{0}" 时遇到错误！ + HDL not known: {0} + 未命名的输入或者输出端口！ + 信号名称 "{0}" 无效或多次使用！ + Error when substituting components for the analysis. + Error in the evaluation of the generic code of the circuit. Code + {1} + at Component: {0} + diff --git a/src/main/resources/lang/lang_zh_ref.xml b/src/main/resources/lang/lang_zh_ref.xml new file mode 100644 index 000000000..38b67fff4 --- /dev/null +++ b/src/main/resources/lang/lang_zh_ref.xml @@ -0,0 +1,1938 @@ + + + Address + Table of Contents + General + Revision + Date + The following describes the available settings of the simulator. + maximum + Attributes + Open Circuit + Included circuit: + Opens the circuit in a new window. + Help + Shows a short description of this element. + Hex + Decimal + Ascii + HighZ + Octal + Binary + Basic + Advanced + Discard Changes + Edit + Continue editing + Load + Reload + Reload last hex file + Save + Save as HEX file. + Create + Create a circuit in a separate window + Edit detached + Opens the dialog as a non modal dialog + Browser + Opens help text in the browser. Allows to print the text. + Clear + All values are set to zero! + Transitions + All possible transitions are added as test cases. Is used to create test cases to test the simulator itself. + New Name + Save anyway + Overwrite + Apply + Edits the content of the selected ROM/EEPROM + Removes the stored data for the selected ROM. The content which is stored in the ROM directly is used instead. + Template + Creates an SVG template which can then be edited with Inkscape. + Import + Import an SVG file. To create a suitable SVG file, it is easiest to first create + a SVG template and then edit it. + Warning + Cancel + Digital + Expression + Inputs + Outputs + Attributes + The {0}. input value for the logic operation. + Returns the result of the logic operation. + And + Binary AND gate. Returns high only if all inputs are also set high. + It is also possible to use buses with several bits as inputs and output. In this case, a bitwise AND is executed. + This means that the lowest bits of all inputs are connected with AND and is output as the lowest bit at the output. + The same happens with bit 1, bit 2 and so on. + NAnd + A combination of AND and NOT. + Returns 0 only if all inputs are set to 1. If one of the inputs is set to 0 the output is set to 1. + It is also possible to use buses with several bits per input. In this case, the operation is applied to each + bit of the inputs. + Or + Binary OR gate. Returns a 1 if one of the inputs is set to 1. + If all inputs are set to 0 the output is also set to 0. + It is also possible to use buses with several bits as inputs and output. In this case, a bitwise OR is executed. + This means that the lowest bits of all inputs are connected with OR and is output as the lowest bit at the output. + The same happens with bit 1, bit 2 and so on. + NOr + A combination of OR and NOT. + Returns a 0 if one of the inputs is set to 1. If all inputs are set to 0 the output is also set to 1. + It is also possible to use buses with several bits per input. In this case, the operation is applied to each + bit of the inputs. + XOr + If two inputs are used, the output is 0 if both input bits are equal. + Otherwise the output in set to 1. + If more than two inputs are used, it behaves like cascaded XOR gates ( A XOR B XOR C = (A XOR B) XOR C ). + It is also possible to use buses with several bits per input. In this case, the operation is applied to each + bit of the inputs. + XNOr + A combination of XOR and NOT. The inputs are combined with the XOR operation. + The result of this operation than is inverted. + It is also possible to use buses with several bits per input. In this case, the operation is applied to each + bit of the inputs. + Not + Inverts the input value. A 1 becomes a 0 and a 0 becomes 1. + It is also possible to use a bus with several bits per input. In this case, the operation is applied to each + bit of the inputs. + The input of the NOT gate. + The inverted input value. + Lookup Table + LUT + Gets the output value from a stored table. + So this gate can emulate every combinatorial gate. + Input {0}. This input in combination with all other inputs defines the + address of the stored value to be returned. + Returns the stored value at the address set via the inputs. + Delay + Delays the signal by on propagation delay time. + Delays a signal for an adjustable number of gate delays. + All other components in Digital have a gate delay of on propagation delay time. + This component can be used to realize any necessary propagation delay. + Input of the signal to be delayed. + The input signal delayed by one gate delay time. + Output + Can be used to display an output signal in a circuit. + This element is also used to connect a circuit to an embedding circuit. + In this case the connection is bidirectional. + Is also used to assign an pin number, if code for a CPLD or FPGA is generated. + This value is used for the output connection. + LED + A LED can be used to visualize an output value. Accepts a single bit. + Lights up if the input is set to 1. + LED Input. LED lights up if the input is set to 1. + RGB-LED + An RGB LED whose color can be controlled via three inputs. + At each of the three inputs, a color channel is connected. + The red color channel. + The green color channel. + The blue color channel. + Input + Can be used to interactively manipulate an input signal in a circuit with the + mouse. This element is also used to connect a circuit to an embedding circuit. + In this case the connection is bidirectional. + Is also used to assign an pin number, if code for a CPLD or FPGA is generated. + Gives the value which is connected to this input. + DIP Switch + Simple DIP switch that can output either high or low. + The output value of the switch. + Clock Input + A clock signal. Its possible to control it by a real-time clock. + Depending on the complexity of the circuit, the clock frequency achieved may be less than the selected value. + If the frequency is greater than 50Hz, the graphic representation of the circuit will no longer be updated at + every clock cycle so that the wire colors will no longer be updated. + If the real-time clock is not activated, the clock can be controlled by mouse clicks. + Is also used to assign an pin number, if code for a CPLD or FPGA is generated. + Switches between 0 and 1 with the selected clock frequency. + Button + A simple push button which goes back to its original state when it is released. + The output signal of the button. + Button with LED + A simple push button which goes back to its original state when it is released. + The push button has an LED which can be switched via an input signal. + The output signal of the button. + Input for controlling the LED. + Text + Shows a text in the circuit. + Does not affect the simulation. + The text can be changed in the attribute dialog. + Rectangle + Shows a rectangle in the circuit. + Does not affect the simulation. If a minus sign is used as the heading, the heading is omitted. + Probe + A measurement value which can be shown in the data graph or measurement table. + This component can be used to easily observe values from embedded circuits. + Does not affect the simulation. + The measurement value. + Light Bulb + Light bulb with two connections. If a current flows, the bulb lights up! + The direction of the current does not matter. The lamp lights when the inputs have different values. + The bulb behaves similar to an XOr gate. + Connection + Connection + LED with two connections. + LED with connections for the cathode and the anode. The LED lights up, + if the anode is connected to high and the cathode is connected to low. + The anode connection of the LED. + The cathode connection of the LED. + Seven-Segment Display + Seven Segment Display, every segment has its own control input. + This input controls the upper, horizontal line. + This input controls the upper, right, vertical line. + This input controls the lower, right, vertical line. + This input controls the lower horizontal line. + This input controls the lower, left, vertical line. + This input controls the upper, left, vertical line. + This input controls the middle, horizontal line. + This input controls the decimal point. + Common cathode. To turn on the LEDs, this input needs to be low. + Common anode. To turn on the LEDs, this input needs to be high. + Seven-Segment-Hex Display + Seven Segment Display with a 4 bit hex input + The value at this input is visualized at the display. + This input controls the decimal point. + 16-Segment Display + The LED input has 16 bits which control the segments. The second input controls the decimal point. + 16-bit bus for driving the LEDs. + This input controls the decimal point. + LED-Matrix + A matrix of LEDs. The LEDs are shown in a separate window. + The LEDs of a column of the display are controlled by a data word. At another input, the current column is + selected. So a multiplexed display is realized. + The LEDs are able to light up indefinitely in the simulation to prevent the display from flickering. + The row state of the LEDs of a column. + Each bit in this data word represents the state of a row of the current column. + The number of the current column whose state is currently visible at the other input. + Data Graph + Shows a data plot inside of the circuit panel. + You can plot complete clock cycles or single gate changes. + Does not affect the simulation. + Rotary Encoder + Rotary knob with rotary encoder. Used to detect rotational movements. + encoder signal A + encoder signal B + Keyboard + A keyboard that can be used to enter text. + This component buffers the input, which can then be read out. + A separate window is opened for the text input. + Clock. A rising edge removes the oldest character from the buffer. + If high the output D is active and one character is output. + It also enables the clock input. + The last typed character, or zero if no character is available. + Output is the 16 bit Java char value. + This output indicates that characters are available. + It can be used to trigger an interrupt. + Terminal + You can write ASCII characters to this terminal. + The terminal opens its own window to visualize the output. + Clock. A rising edge writes the value at the input to the terminal window. + The data to write to the terminal + A high at this input enables the clock input. + VGA Monitor + Analyzes the incoming video signals and displays the corresponding graphic. + Since the simulation cannot run in real time, the pixel clock is required in addition to the video signals. + The red color component + The green color component + The blue color component + The horizontal synchronization signal + The vertical synchronization signal + The pixel clock + MIDI + Uses the MIDI system to play notes. + Note + Volume + If set, this translates to pressing a keyboard key (key down event), + if not set, this translates to releasing the key (key up event). + Enables the component + If high, the value at N is used to change the program (instrument). + Clock + Stepper Motor, unipolar + Unipolar stepper motor with two limit position switches. + Full step drive, half step drive and wave drive are supported. + Limit position switch 0, becomes 1 when the motor angle is 0°. + Limit position switch 1, becomes 1 when the motor angle is 180°. + Phase 0 + Phase 1 + Phase 2 + Phase 3 + Stepper Motor, bipolar + Bipolar stepper motor with two limit position switches. + Full step drive, half step drive and wave drive are supported. + Limit position switch 0, becomes 1 when the motor angle is 0°. + Limit position switch 1, becomes 1 when the motor angle is 180°. + Coil A, positive + Coil A, negative + Coil B, positive + Coil B, negative + Ground + A connection to ground. Output is always zero. + Output always returns 0. + Supply voltage + A connection to the supply voltage. Output is always one. + This output always returns 1. + Constant value + A component which returns a given value as a simple constant value. The value can be set in the attribute dialog. + Returns the given value as a constant. + Tunnel + Connects components without a wire. All tunnel elements, which have the same net name, + are connected together. Works only locally, so it is not possible to connect different circuits. + Unnamed tunnels are ignored silently. + The connection to the tunnel. + Splitter/Merger + Splits or creates a wire bundle or a data bus with more than one bit. + With a bus it is e.g. possible to generate 16-bit connections without having to route 16 individual wires. + All 16 connections can be merged into one wire. + The splitter has a direction, meaning it can only transmit signals in one direction. + The input bits {0}. + The input bit {0}. + The output bits {0}. + The output bit {0}. + Bidirectional Splitter + Can be used for data buses and simplifies especially the construction of + memory modules in a DIL package, as the implementation of the data bus is simplified. + When set, the value at the common data terminal D is output to the bit + outputs D[i], if not, the bits D[i] are output to the common output D. + The common data connection. + The data bit {0} of the bus splitter. + Pull-Up Resistor + A "weak high". + If a net is in a HighZ state, this resistor pulls the net to high. + In any other case this component has no effect. + Pull-Down Resistor + A "weak low". + If the net is in a HighZ state, this resistor pulls the net to ground. + In any other case this component has no effect. + Driver + A driver can be used to connect a signal value to another wire. + The driver is controlled by the sel input. + If the sel input is low, the output is in high z state. + If the sel input is high, the output is set to the input value. + The input value of the driver. + If the sel input is 1 the input is given to this output. + If the sel input is 0, this output is in high z state. + Pin to control the driver. + If its value is 1 the input is set to the output. + If the value is 0, the output is in high z state. + Driver, inverted select + A driver can be used to connect a data word to another line. + The driver is controlled by the sel input. + If the sel input is high, the output is in high z state. + If the sel input is low, the output is set to the input value. + The input value of the driver. + Pin to control the driver. + If its value is 0 the input is given to the output. + If the value is 1, the output is in high z state. + If the sel input is 0 the input is given to this output. + If the sel input is 1, this output is in high z state. + Pin Control + Control logic for a bi-directional pin. + This component is necessary only in the context of VHDL or Verilog generation, in order to create a + bi-directional HDL port! + If you don't want to use a bi-directional IO-port on an FPGA, don't use this component! + The PinControl component cannot be used in an embedded circuit! It is only allowed at the top level circuit! + The data to be output. + Activates the output. + The data to be read. + The connector for the actual pin. Only a single output should be connected + here. + Multiplexer + A component which uses the value of the sel pin to decide which input value is + set to the output. + The {0}. data input of the multiplexer. + The value of the selected input. + This input is used to select the data input which is output. + Demultiplexer + A component that can output the input value to one of the outputs. + The other outputs are set to the default value. + This pin selects the output to use. + The value of this input is given to the selected data output. + Data output {0}. + Decoder + One selectable output pin is 1, all other outputs are set to 0. + Output {0}. This output is 1 if selected by the sel input. + This input selects the enabled output. + The selected output is set to 1. All other outputs are set to 0. + Bit Selector + Selects a single bit from a data bus. + The input bus + This input selects the bit + The selected bit. + Priority Encoder + Priority + If one of the inputs is set, its number is output. + If several inputs are set at the same time, the highest number is output. + Number of the set input. + If this output is set, at least one of the inputs is set. + The {0}. input of the priority encoder. + RS-Flip-flop + RS + A component to store a single bit. + Provides the functions "set" and "reset" to set or reset the stored bit. + If both inputs are switched to one, both outputs also output a one. + If both inputs switch back to zero at the same time, the final state is random. + The set input. + The reset input. + Returns the stored value. + Returns the inverted stored value. + RS-Flip-flop, clocked + RS + A component to store a single bit. + Provides the functions "set" and "reset" to set or reset the stored bit. + If both inputs (S, R) are set at the rising edge of the clock, the final state is random. + The set input. + The clock input. A rising edge initiates a state transition. + The reset input. + Returns the stored value. + Returns the inverted stored value. + JK-Flip-flop + JK + Has the possibility to store (J=K=0), set (J=1, K=0), reset (J=0, K=1) or toggle (J=K=1) the stored value. + A change of state takes place only at a rising edge at the clock input C. + The set input of the flip-flop. + The clock input. A rising edge initiates a state change. + The reset input of the flip-flop. + Returns the stored value. + Returns the inverted stored value. + D-Flip-flop + D + A component used to store a value. + The value on pin D is stored on a rising edge of the clock pin C. + The bit width can be selected, which allows to store multiple bits. + Input of the bit to be stored. + Clock pin to store a value. + The value on input D is stored on a rising edge of this pin. + Returns the stored value. + Returns the inverted stored value. + T-Flip-Flop + T + Stores a single bit. Toggles the state on a rising edge at input C. + Enables the toggle function. + Clock input. A rising edge toggles the output, if input T is set to 1. + Returns the stored value. + Returns the inverted stored value. + JK-Flip-flop, asynchronous + JK-AS + D-Flip-flop, asynchronous + D-AS + Monoflop + Mono + Register + Reg + ROM + RAM + EEPROM + P-Channel FET + N-Channel floating gate FET + Test case + Describes a test case. + In a test case you can describe how a circuit should behave. It can then be automatically checked whether the + behavior of the circuit actually corresponds to this description. If this is not the case, an + error message is shown. + Asynchronous Timing + Allows configuration of the timing of an asynchronous sequential circuit such as a + Muller-pipeline. The circuit must be started in single gate step mode and must be able to reach a stable state + at startup. The sequential circuit can then be started interactively or with a reset gate. + It is not allowed to use a regular clock component in this mode. + Power + Reset + Reset Output. + Break + Stops the fast simulation clocking if a rising edge is detected. + External + Component to execute an external process to calculate the logic function. + Is used to specify the behaviour of a component by VHDL or Verilog. + The actual simulation of the behavior must be done with an external simulator. + At present only the VHDL simulator ghdl and the verilog simulator Icarus Verilog are supported. + Diode + Error + Pin {0} in component {1} is not a input or output + A single clock component is necessary. All flip-flops must use this clock signal. + The circuit has no labeled inputs + The circuit has no labeled outputs + No break detected after {0} cycles at break point ''{1}''. + Possibly the number of timout cycles in the break component should be increased. + Expression {0} not supported + Operation {0} not supported + Error creating the lookup table. + More than one output is active on a wire, causing a short circuit. + It is not allowed to connect a pull-up and pull-down resistor to the same net. + Cannot analyse Node {0} + Contains [var] and [not var] + Pin {0} in component {1} exists twice + Component {0} not found + Exact {0} valoas necessary, not {1} + Flip-flop needs to be connected to the clock. + Invalid file format + Logic is already initialized + A tunnel {0} is not connected! + There is more than one clock + The clock component is not used! + There are {0} bits needed, but {1} bits found + Net of pin {0} not found + No clock found in logic + Address Bits + Number of address bits used. + Data Bits + Number of data bits used. + Color + The Color of the element. + Background color + Background color of the circuit when it is embedded in another circuit. Is not used for DIL packages. + Timeout cycles + If this amount of cycles is reached without a break signal, an error is created. + Data + The values stored in this element. + Default + This value is set if the circuit is started. + At the demultiplexer, this value is set for the non-selected outputs. + Default + This value is set if the circuit is started. A "Z" means high-z state. + Is three-state input + If set the input is allowed to be in high-z state. At the input component this is + also allowed if high-z ("Z") is set as the default value. + No zero output. + Description + A short description of this element and its usage. + Frequency/Hz + The real time frequency used for the real time clock + Use IEEE 91-1984 shapes + Use IEEE 91-1984 shapes instead of rectangular shapes + Number of Inputs + The Number of Inputs used. Every input needs to be connected. + Label + The name of this element. + Size + The size of the shape in the circuit. + Language + Language of the GUI. Will only take effect after a restart. + Net name + All nets with identical name are connected together. + Input Splitting + Number Format + The format used to show the numbers. + ascii + bin + decimal + signed decimal + default + hex + octal + Mode + Direction + Set direction. + left + right + Max number of steps to show + The maximal number of values stored. + If the maximum number is reached, the oldest values are discarded. + Rotation + The orientation of the Element in the circuit. + Mirror + Mirrors the component in the circuit. + Start real time clock + If enabled the runtime clock is started when the circuit is started + Show measurement graph at simulation start + When the simulation is started, a graph with the measured values is shown. + Show in Measurement Graph + Shows the value in the measurement graph. + Show measurement values at simulation start + When the simulation is started, a table with the measured values is shown. + Lines + The number of lines to show. + Characters per line + The number of characters shown in a single line. + Use as measurement value + Is set the value is a measurement value and appears in the graph and data table. + In addition, a label must be specified that can serve as identification of the value. + Test data + Width in pixels + The screen width in pixels. + Height in pixels + The screen height in pixels. + Program Memory + Makes this ROM to program memory. So it can be accessed by an external IDE. + Program Counter + Programmed + If set a diode is "blown" or "programmed". + At a floating gate FET the floating gate is charged. + You can change this setting with the key 'p'. + Format + Screen format of expressions. + Common Connection + If selected, a common cathode or anode input is also simulated. + Common + Kind of common connection. + Cathode + Anode + Avoid Flicker + ATF15xx Fitter + Path to the fitter for the ATF15xx. + Enter the directory which contains the fit15xx.exe files provided by Microchip (former ATMEL). + Pin number + An empty field means this signal is not assigned to a pin. + Rows + Specifies the number of rows by specifying the number of bits of the row word. + Address bits of columns + Addresses the individual columns. Three bits means eight columns. + Modification locked + The circuit is locked. It is possible to configure diodes and FGF-FETs. + Pin number + Number of this pin. Used for the representation of a circuit as a DIL package and + the pin assignment when programming a CPLD. + If there are several bits, all pin numbers can be specified as a comma-separated list. + Number of DIL pins + Number of pins. A zero means that the number of pins is determined automatically. + Component tree view is visible at startup. + If set, the component tree view is enabled at startup. + inverted Inputs + You can select the inputs that are to be inverted. + Menus Font Size [%] + Size of the fonts used in the menu in percent of the default size. + Enable Input + If set an enable input (T) is available. + Unidirectional + Active Low + If selected the output is low if the component is active. + Library + Folder which contains the library with predefined sub circuits. + Contains, for example, the components of the 74xx series. You also can add your own circuits by storing + them at this location. + It must be ensured that the names of all files in this folder and all subfolders are unique. + Show Grid + Shows a grid in the main window. + Wire tool tips + If set, lines are highlighted when the mouse hovers over them. + Map to keyboard + Button is mapped to the keyboard. + To use the cursor keys use UP, DOWN, LEFT or RIGHT as label. + Java library + A jar file containing additional components implemented in java. + Shows the number of wires on a bus. + CAUTION: The value is only updated when the simulation starts. + Input Bit Width + The number of output bits must be greater than the number of input bits. + Output Bit Width + The number of output bits must be greater than the number of input bits. + Font Size + Sets the font size to use for this text. + Duration + Delay time in units of the common gate propagation delay. + inverted output + If selected the output is inverted. + Pulse Width + The puls width is measured in clock cycles. + Spreading + Configures the spread of the inputs and outputs in the circuit. + Content of ROM's + Content of all used ROM's + Application + Defines which application to use. + Generic + GHDL + IVerilog + Inputs + Outputs + Programcode + The programm code to be executed by the external application. + Options + GHDL + GHDL Options + Options that are used for all processing steps by GHDL. + IVerilog + Path to the Icarus verilog installation folder. Only necessary if you want to use + iverilog to simulate + components defined with verilog. + Maximum Value + If a zero is entered, the maximum possible value is used (all bits are one). + Output is High + The default output value of the DIP switch when the simulation starts. + Use MacOS mouse clicks. + Uses CTRL-click instead of right-click. + No tool tips for components on the main panel. + If set, no tool tips for the components on the main panel are displayed. + Especially in a presentation, these tool tips can be very annoying. + Show dialog for automatic renaming of tunnels. + If set, a dialog for automatically renaming all tunnels of the same name is displayed after a + tunnel has been renamed. + ATMISP + Path to the executable file ATMISP.exe. If set, the ATMISP software can be started automatically! + Custom Shape + Import of a SVG-file + Preload program memory at startup. + When simulating a processor that uses a RAM device as the program memory, + it is difficult to start this processor because the RAM contents are always initialized with zeros at the start + of the simulation. This setting allows loading data into the program memory at startup. + The program memory in the simulation must be marked as such. + Program file + File which should be loaded into the program memory at the start of the + simulation. + Width + Width in grid units + Height + Height in grid units + Text Inside + Place text inside the rectangle. + Text at the bottom + Place text at the bottom of the rectangle. + Text on the right + Place text to the right of the rectangle. + Wide Shape + Uses a wider shape to visualize the gate. + Shape + The shape to be used for the representation of the circuit in an embedding circuit. + In the "Simple" mode, the inputs are displayed on the left and the outputs on the right side of a simple rectangle. + With "Layout", the position of the inputs and outputs and their orientation in the circuit determines + the position of the pins. Here are also pins at the top or bottom possible. + When selecting "DIL-Chip", a DIL housing is used to display the circuit. The pin numbers of the inputs and outputs + determine the position of the pins in this case. + Default + Simple + DIL-Chip + Layout + User defined + Orientation + Position of the coordinate relative to the text. + left bottom + center bottom + right bottom + right center + right top + center top + left top + left center + center center + Enabled + Enables or disables this component. + Toolchain Configuration + Used to configurate an integration of a toolchain. + Allows the start of external tools, e.g. to program an FPGA or similar. + Generic Parameterization + Statements used to generify a circuit. + Circuit is generic + Allows to create a generic circuit. + Show Tutorial at Startup + Enables the tutorial. + SVG Export Settings + Hide Test Cases + The test cases are not exported. + Shapes not filled + Polygons are not filled. + Inputs and outputs are represented as small circles. + Leave out Pin Marker + The blue and red pin markers on the symbols are omitted. + High Contrast + The wires and the text of the pins are displayed in black. + Monochrome + Only gray colors are used. + Thin Lines + If set, the lines are drawn slightly thinner. + Snap To Grid + If set, the component is aligned with the grid. + Pin Separator + Used by the layout shape type. Sets the distance to the previous pin. + Inserted wire. + Insert from clipboard. + Value ''{0}'' in component ''{1}'' modified. + Attributes of component ''{0}'' modified. + Wire deleted. + Component ''{0}'' moved or rotated. + Wire moved. + Selection deleted. + Component ''{0}'' inserted. + Component ''{0}'' deleted. + Wire inserted. + Selection moved. + Undo: {0} + Redo: {0} + Modified circuit attributes. + Ordered measurements. + Modified attributes of selected components. + Splits a single wire into two wires. + Logic + Arithmetic + Flip-Flops + IO + Memory + Plexers + Wires + Switches + Displays + Mechanical + Peripherals + Misc. + more + Windows + About + Analysis + Analyses the actual circuit + Cut + Copy + Custom + Library + Delete components + Delete selected single component or group of components. + Edit + Circuit specific settings + The circuit specific settings affect the behavior of the + currently open circuit. + Thus, e.g. the shape that represents the circuit when it is embedded in other circuits. + These settings are stored together with the circuit. + Settings + The global settings of the simulator specify, among other + things, the language, the symbol form to be used or the paths of external tools. + Stop Simulation + Stops the simulation and allows to edits the circuit. + Components + Export + Export PNG large + Export PNG small + Export SVG + Export Animated GIF + Run to Break + Runs the circuit until a break is detected by a BRK component. + File + Help + Update + Updates the components menu. + Fit to window + Single gate stepping + Runs the circuit in single gate step mode + New + Creates a new, empty circuit. + New embedded Circuit + Opens a new window to create a new embedded circuit, which than can be used in this circuit. + Open + Open Recent + Open Recent in New Window + Open in New Window + Opens a circuit in a new window + Order Inputs + Order the inputs for the usage as a embedded circuit + Order measurement values + Orders the measurement values in the graphical and table view + Order Outputs + Order the outputs for the usage as a embedded circuit. + Paste + Rotate + Simulation + Start of Simulation + Starts the simulation of the circuit. + Save + Save As + Save Data + Save data as CSV file + Speed Test + Performs a speed test by calculating the max. clock frequency. + Gate Step + Calculates a single gate step + Run To Break in Single Gate Mode + Executes all single gate steps until a rising edge is detected on a break component. + If there is no break component, the remaining single gate steps are executed. + Synthesise + Generates the minimal bool expressions described by a truth table. + {0} variables + Create + Circuit + Creates a circuit which reproduces the truth table. + Circuit with JK flip-flops + Creates a circuit which reproduces the truth table. Uses JK flip-flops. + Circuit with LUTs + Creates a circuit which reproduces the truth table. Uses lookup tables to create the expressions. + Circuit with NAnd gates + Circuit with NAnd gates with two inputs + Use only NAnd gates with two inputs. + Creates a circuit which reproduces the truth table only with NAnd gates. + Circuit with NOr gates + Circuit with NOr gates with two inputs + Use only NOr gates with two inputs. + Creates a circuit which reproduces the truth table only with NOr gates. + Circuit with two input gates + create circuit, use only gates with two inputs + Circuit with three input gates + create circuit, use only gates with a maximum of three inputs + Device + Creates a JEDEC file for the device + Export LaTeX + Export Test Case + Creates a test case description that can be used in a test + case. + The test case is only functional if the circuit is + purely combinatorial! + Export HEX + You can load the HEX file to a ROM or a LUT. + New + Combinatorial + Sequential + Sequential bidirectional + Reorder/Delete Input Variables + Reorder/Delete Output Columns + Add Output Column + Adds a new result column to the table. + Add Input Variable + Adds a new input variable to the table. + Set X to 0 + Sets the Don't Cares to 0. + Set X to 1 + Sets the Don't Cares to 1. + Create J/K Expressions + Set all to X + Set all values to "don't care". + Set all to 0 + Set all values to zero. + Set all to 1 + Set all values to one. + Invert all bits + A "1" becomes a "0" and vice versa. Don't cares remain unchanged. + Show results dialog + Shows the results dialog again if it was closed manually. + Delete + Delete the terminals content. + View + Zoom In + Zoom Out + Expression + Create a circuit from an expression. + Run Tests + Runs all test cases in the circuit + Set Inputs + Use actual input values as new default values. + Reset all diodes and FGFETs + Resets all diodes (fuses) and FGFETs to the "not programed" state. The actual fuse configuration is lost! + Components + Shows a list of all available components. + Help Dialog + Shows the help dialog describing the actual circuit. + Paste in new window + The content of the clip board is pasted in a new window. + Component Tree View + Shows a tree view of available components at the left side. + Special 74xx Funtions + Add IO-Prefix + Remove IO-Prefix + The first character from the inputs and outputs labels are removed. + Is used to simplify the doubling of circuits within a 74xx circuit. + Pin Wizard + Wizard to apply pin numbers to the inputs and outputs. + Remove Pin Numbers + Remove all pin numbers in the circuit + Undo + Revert last modification + Redo + Apply last reverted modification again. + Show graph + Show the data as a Graph. + Show table + Shows values as a table. + Add power supply + Adds a power supply to the circuit. + Export to VHDL + Exports the circuit to VHDL + Export to Verilog + Exports the circuit to Verilog + K-Map + Shows a K-map representation of the Table! + Documentation + Open {0} + Show measurement value table + Show table with the measured values in a separate window. + Show measurement graph + Shows a graph with the measured values in a separate window. + Export to ZIP file + Exports the circuit as a ZIP file. + The ZIP file thus contains all the files that are necessary for the operation of the circuit. + Label Inputs and Outputs + Set a label to all inputs and outputs without a label. + Start Tutorial + Starts the beginner tutorial. + Circuit Statistics + Shows a list of used components. + Number + Component + Inputs + Bits + Addr. Bits + Error opening a PDF file! + <h1>Digital</h1>A simple simulator for digital circuits. + Written by H. Neemann in 2016-2020. + + The icons are taken from the <a href="http://tango.freedesktop.org">Tango Desktop Project</a>. + + Visit the project at <a href="https://github.com/hneemann/[[name]]">GitHub</a>. + At Github you can also <a href="https://github.com/hneemann/[[name]]/releases/latest">download</a> + the latest release. + + There you also can file an <a href="https://github.com/hneemann/[[name]]/issues/new?body=version:%20[[version]]&labels=bug">issue</a> + or suggest + an <a href="https://github.com/hneemann/[[name]]/issues/new?labels=enhancement">enhancement</a>. + {0} nodes + Error analysing the circuit + Error during a clock state change + Color + Error creating the circuit + Error during simplification + Error during creation of hardware configuration. + Error editing a attribute value + Error importing the circuit {0}! + Error updating the component library!! + Error reading a file + Command {0} unknown! + Error writing a file + The maximum frequency is {0} kHz + Shape {0} is missing + Pin assignment + Pin {0}: {1} + A restart is required for the changes to take effect! + Enter an expression: + Error running the tests: + Test result + {0} passed + {0} failed + (To many entries!) + All test cases are executed, but not all results are shown. + The evaluation of the test result is nevertheless correct! + E: {0} / F: {1} + Error creating the help! + The clipboard contains no importable data! + Select an empty folder! + Message from the external fitter + Execution of external fitter + Actual Circuit + The selected file name is not importable from the actual project! + The file name is not unique! + All files in the working directory and all subdirectories must have unique file names. This also applies to the + library folder. If your work directory has a 7400.dig file, you can not use this file or the 7400.dig file from + the library. + If there is a 7400.dig file in your working directory, you can not use this file or the 7400.dig file from the + library, because this file name can no longer be uniquely assigned. + There are several files with identical file names, which can not be + uniquely assigned! Affected are: + and {0} more. + The file has not yet been imported. + The file {0} already exists! Do you want to overwrite the file? + The editing of the circuit is disabled. You can remove the lock at + "{0} -> {1} -> {2}". + However, copying of components and the configuration of diodes and FG-FETs with the [P] key is also possible in the locked mode. + Error during speed test! + Pin {0} + Numbering Wizard + Select pin {0}: + Written frames: {0} + Error writing to GIF file! + Ready + The GIF file is finalized and closed. + GIF Export + caused by + Inputs to invert + none + Could not determine the names of the pins. + Occurred in file {0}. + Affected are: {0}. + Signal {0} + No pin numbers assigned to the pins {0}! + Free pins are automatically assigned. The circuit can therefore not be used on real hardware in most cases! + You can only export a circuit without errors! + No KV map available! + Data will not be updated anymore! + Modify this Value + One of the fields contains a invalid value! + Creation of CHN file. + The table is very large, the export may take a while. + Start export anyway? + To create a hardware description, a circuit must first be created and analyzed. + A standalone truth table can not be used to generate a hardware description. + no data + Could not close external process! + Check Result: + Check + Starts the application to check if the entered code is correct. + If this is not the case, the error message of the external application is displayed. + If possible, the input and output definitions are also adapted to the current code. + Input and output definitions could not be created automatically. + Please check the settings! + Executable file "{0}" not found! + Enter Text! + Start ATMISP + Starts the external program ATMISP. This must have been previously installed. + Error while starting ATMISP! +Is the correct path to the executable ATMISP.exe specified in the settings? + ATMISP is still running! +When this dialog is closed, ATMISP is terminated! +Make sure the flash process is complete before closing this dialog! + Run all Tests + Executes all tests in the current folder. + {0} test rows passed + File Tested + Truth Table + Clipboard + Copies the text to the clipboard. + OK + 0° + 180° + 270° + 90° + Deletes the selected item + Move the item down + Move the item up + All possible solutions + Testdata {0} + Data + Confirm Exit! + Measurements + Save Changes? + State Changed! + Table + Export + Select + Input {0} + Karnaugh Map + Help + Central ROM Content + Expressions + Test vectors + Finite State Machine + no movement + Transitions + Transitions+States + set {0} + Finite State Machine + Opens a Dialog to Edit a Finite State Machine. + Create + State Transition Table + Create Counter + {0} States + Help for operating the FSM editor. + State Number + The number which represents this state. + Initial State + If set, this state is the initial state. + Outputs + Condition + A boolean expression. + Radius + Radius of the circle in the diagram. + Error loading a file! + Error storing a file! + Transition + State + New State + Can not create state transition table. + Help FSM Editor + The measurement graph + Tutorial + In the following a short tutorial leads you to the first, simple circuit: + + First, insert an input into the circuit. You will find the input in the menu Components▸IO. + Now add a second input to the circuit. You can also click on the input + in the toolbar. + + It is best to place the second input slightly below the first input. + You can move the circuit by holding down the right mouse button. + By clicking on components you can move them. + Next, an "Exclusive Or" gate is to be inserted. + You can find this gate in the menu Components▸Logic. + Place this component with some distance to the right of the inputs. + The last component to be inserted is an output. + Place it with some distance to the right of the "Exclusive Or" gate. + In order to complete the circuit, connecting wires must be drawn. + + Click on the red dot at the first input and connect it to an input of the "Exclusive Or" gate, + by clicking on a blue dot of the "Exclusive Or" gate afterwards. + Do NOT drag with mouse button down! + Connect the red dot of the second input to the second blue dot of the + "Exclusive Or" gate and the red dot of the "Exclusive Or" gate to the blue dot of the output. + + While drawing, you can pin the wire by clicking somewhere on the canvas. + Right-click cancels the drawing of the wire (control-click on MacOS). + Your first circuit is now functional. + To start the simulation, you can click on the Play button in the toolbar. + If you move the mouse over the toolbar, tool tips are shown. + The simulation is now active. Switch the inputs by clicking on them. + To stop the simulation, click on the Stop button in the toolbar. + For completeness, the inputs and outputs should be labeled. + + Right-click on an input to open a dialog. On MacOS control-click is used. + Here the input can be given a name. + Label all inputs and outputs. + Inputs and outputs should always be uniquely named. + Skip Tutorial + Has the possibility to store (J=K=0), set (J=1, K=0), reset (J=0, K=1) or toggle (J=K=1) the stored value. + A change of state takes place only at a rising edge at the clock input C. + There are two additional inputs which set or reset the state immediately without a clock signal. + The set input of the flip-flop. + The Clock input. A rising edge initiates a state change. + The reset input of the flip-flop. + Returns the stored value. + Returns the inverted stored value. + asynchronous set. A high value at this input sets the flip-flop. + asynchronous clear. A high value at this input clears the flip-flop. + A component used to store a value. + The value on pin D is stored on a rising edge of the clock pin C. + There are two additional inputs which set or reset the state immediately without a clock signal. + The bit width can be selected, which allows to store multiple bits. + Input of the bit to be stored. + Control pin to store a bit. The bit on input D is stored on a rising edge of this pin. + Returns the stored value. + Returns the inverted stored value. + asynchronous set. If set to one, all stored bits are set to one. + asynchronous clear. If set to one, all stored bits are set to zero. + The monoflop is set at a rising edge at the clock input. + After a configurable delay time, the monoflop will be cleared automatically. + The monoflop is retriggerable. It can only be used if there is exactly one clock component present in the circuit. + This clock component is used as time base to measure the time delay. + Reset Input. A high value clears the monoflop. + The Clock input. A rising edge sets the monoflop. + output + inverted output + No inputs available to set + No shape found for component {0} + Nothing connected to input ''{0}'' at component ''{1}''. Open inputs are not allowed. + Not all connected outputs have the same bit count + If multiple outputs are connected together, all of them have to be three-state outputs. + No output connected to a wire ({0}). The state of the wire is undefined. + Table to small: One result is required! + Output {0} not defined + No label for pin {0} + Pin {0} assigned twice! + Pin {0} is not an input! + Pin {0} is not an output! + No = found! + To many inputs used! + To many outputs used! + Pin not present + Found a pin without a label. + Found a clock without a label. If a clock is embedded also the clock needs a label. + Pin {0} not found at component {1} + Pin {0} not found + The custom shape does not define a pin {0} + Pin {0} unknown + Logic seems to oscillate. + To analyse you can run the circuit in single gate step mode. + The remote port is in use! Is there an other instance running? + Number of inputs does not match selector bit count + Syntax error in splitter definition {0} + Bit count of splitter is not matching + Not all input bits are defined! + Input bits are defined several times! + Only 64 bits allowed in splitter! + Two inputs are required! + To many variables (inputs+flip-flops), allowed are {0} but {1} are found. + To many variables used in {0}, + allowed are {1} variables but {2} are found. + Variable {0} is not allowed in CUPL source! + Variable {0} not defined + Unexpected Token {0} + Missing closed parenthesis + Value {0} in line {1} is not a number! + Expected {0} but found {1} values in line {2}! + Unexpected token ({0}) in line {1}. + Variable {0} not found! + No input signals defined in test vector! + No output signals defined in test vector! + No test data found. + Error during execution of a remote command + A component to store values. The bit width of the data word can be selected. + Unlike a D flip-flop, the register provides an input which enables the clock. + Input pin of the data word to be stored. + Clock input. A rising edge stores the value at the D pin. + Enable pin. Storing a value works only if this pin is set high. + Returns the stored value. + A non-volatile memory component. + The stored data can be edited in the attributes dialog. + This pin defines the address of data word to be output. + The selected data word if the sel input is high. + If the input is high, the output is activated. If it is low, the data output is in high Z state. + RAM, separated Ports + RAM + A RAM module with separate inputs for storing and output for reading the stored data. + The address to read from or write to. + Clock input + The data to be stored in the RAM. + The data output pin + If this input is high the output is activated and the data is visible at the output. + If this input is high and when the clock becomes high, the the data is stored. + Block-RAM, separated ports + A RAM module with separate inputs for storing and output for reading the + stored data. This RAM only updates its output on a rising edge of the clock input. + This allows the usage of Block RAM on an FPGA. + The address to read from or write to. + Clock input + The data to be stored in the RAM. + The data output pin + If this input is high and when the clock becomes high, the the data is stored. + EEPROM, separated Ports + A EEPROM module with separate inputs for storing and output for reading the stored data. + The address to read from or write to. + Clock input + The data to be stored in the EEPROM. + The data output pin + If this input is high the output is activated and the data is visible at the output. + If this input is high and when the clock becomes high, the the data is stored. + RAM, bidirectional Port + RAM + A RAM module with a bidirectional pin for reading and writing the data. + The address to read and write. + Clock + The bidirectional data connection. + If this input is high the output is activated and the data is visible at the output. + If this input is high when the clock becomes high, the the data is stored. + RAM, Chip Select + RAM + A RAM module with a bidirectional connection for reading and writing the data. + If the CS input is low, the component is disabled. + This allows to build a larger RAM from some smaller RAMs and a address decoder. + The write cycle works as follows: By setting CS to high, the component is selected. + A rising edge at WE latches the address, and the following falling edge at WE stores the data. + The address to read and write. + If set to high the data is written to the RAM. + The bidirectional data connection. + If this input is high, this RAM is enabled. Otherwise the output is always in high Z state. + If this input is high, the stored value is output. + EEPROM + A EEPROM module with a bidirectional connection for reading and writing the data. + If the CS input is low, the component is disabled. + The data content is stored like in a ROM. It is thus preserved when the simulation is terminated and restarted. + The write cycle works as follows: By setting CS to high, the component is selected. + A rising edge at WE latches the address, and the following falling edge at WE stores the data. + The address to read and write. + If set to high the data is written to the EEPROM. + The bidirectional data connection. + If this input is high, this EEPROM is enabled. Otherwise the output is always in high Z state. + If this input is high, the stored value is output. + RAM + RAM with one port that allows to write to and read from the RAM, and a second + read only port. + This second port can be used to give some graphic logic access to the memory contents. In this way, a processor + can write to the RAM, and a graphics logic can simultaneously read from the RAM. + Output Port 1 + Output Port 2 + The address at which port 1 is read or written. + The address used to read via port 2. + Clock + The data to be stored in the RAM. + If this input is high the output is activated and the data is visible at the output 1D. + If this input is high and when the clock becomes high, the the data is stored. + Register File + Register + Counter + Counter + Counter with preset + Closed + Sets the initial state of the switch. + Value + The value of the constant. + Width + Width of symbol if this circuit is used as an component in an other circuit. + Height + Height of symbol if this circuit is used as an component in an other circuit. + Reload at model start + Reloads the hex file every time the model is started. + Flip selector position + This option allows you to move te selector pin to the opposite side of the plexer. + Text in LaTeX notation + Text is inserted in LaTeX notation. Inkscape is required for further processing. + Pin-Labels in Math Mode + For pin labels, use math mode even if no indexes are contained. + Small Inputs and Outputs + Use Equals-Key + Use the equal key instead of the plus key. + This is always useful if the plus character is not a primary key, but the second assignment of the + equals character, e.g. for an American or French keyboard layout. + RAM + EEPROM + Creates a CUPL source file containing the define circuit. + Creates a file containing the circuit similar to the Berkeley Logic Interchange Format (BLIF). + After that the Atmel fitter is started to create the JEDEC file. + Program diode + Memory + Shows the content of memory components. + A prefix is added to all selected inputs and outputs. + Is used to simplify the doubling of circuits within a 74xx circuit. + Error calculating a step + Error at fast run + Error while importing the SVG file. + Error creating the SVG template. + Statistics could not be created. + Error while reading the toolchain configuration {0} + Command "{0}" has been started! Processing may take some time! + The command "{0}" has been completed! + Rename Net + There are {0} more tunnels with the net name ''{1}''. + Do you want to rename all {0} to ''{2}''? + Do you really want to discard the changes in the "{0}" field? + Break after {0} half cycles at break point ''{1}''. + Measurements full clock step + Measurements single gate step + Included ROM's + <html> + <h3>Motivation</h3> + When a circuit containing a ROM component is embedded multiple times, the contents of the ROM + is normally used for each instance of that circuit. Under certain circumstances, + however, it may be desirable for such a circuit to be embedded multiple times, + but different ROM contents are used for each instance.<br/> + This problem occurs e.g. if a 74xx ROM is used multiple times but with different + memory contents.<br/> + <h3>Function</h3> + At this location, therefore, contents can be defined for all ROM's in the circuit. + When the simulation model is generated, every ROM is initialized with the contents stored + directly in the respective ROM. Then it is checked whether an alternative content is + defined here. If this is the case, the content defined here is loaded into the corresponding ROM. + <h3>Usage</h3> + It should be noted that each ROM requires a unique name used to identify the ROM. + To do this, use the asterisk ('*') in the label of the ROM. The asterisk is then replaced by the complete + path constructed from the names of the embedded circuits. + If a circuit contains only one ROM component, it is sufficient to use only the asterisk as a label for it. + All embedded circuits must be named so that a unique name can be formed for each ROM component. + </html> + <html> + <h1>New Version {0} Available</h1> + <p>There is a new release of the simulator available.</p> + <p>In the <a href="https://github.com/hneemann/[[name]]/releases/latest">release notes</a> + you can find the changes and improvements.</p> + <p>Here you can <a href="https://github.com/hneemann/[[name]]/releases/latest">download</a> the new release.</p> + </html> + To define an expression you can use all most common notations: + + And: "&", "&&", "*", "∧" + Or: "|", "||", "+", "∨", "#" + XOr: "^", "⊻" + Not: "!", "~", "¬" + + As usual AND precedes OR and XOr. + + Multiple expressions can be separated by "," or ";". + If you want to name the expressions you can use the + let-command: "let U=A+B, let V=A*B" + <html> + <head><style>pre { background-color: #E0E0E0;}</style></head> + <body> +<p>The first line has to contain the names of inputs and outputs. +The following lines contain the expected values. +A 'X' represents a don't care, and a 'Z' represents a high Z value. +If a 'C' is used, at first all other values are set, after that a clock cycle is performed and than the +values are compared. So it's easier to test sequential logic. +A line which starts with a number sign ('#') is a comment.</p> + +<p>So a test for a 2-bit counter could look like this:</p> + +<pre> +C Q1 Q0 +0 0 0 +C 0 1 +C 1 0 +C 1 1 +C 0 0 +</pre> + +<p>The tests are executed by Run->Run Tests.</p> +<p> +To make it easier to create a lot of test vectors there is the 'repeat([n])' statement: +If a line begins with 'repeat([n])', [n] test lines are generated. The +Variable 'n' can be used to generate the test data. With 'repeat(16)' +16 lines are created, where n goes from 0 to 15. If there are multiple bit inputs, +and these are to be set together to a binary value, this can be done with the +'bits([bits], [value])' statement. This is used to create [bits] bits of the value [value].</p> + +<p>The following is an example that tests a 4-bit adder:</p> + +<pre> + C_i-1 A_3 A_2 A_1 A_0 B_3 B_2 B_1 B_0 C_i S_3 S_2 S_1 S_0 +repeat(256) 0 bits(4,n>>4) bits(4,n) bits(5,(n>>4)+(n&15)) +repeat(256) 1 bits(4,n>>4) bits(4,n) bits(5,(n>>4)+(n&15)+1) +</pre> + +<p>The input signals are the carry-in (C_i-1) and the eight input bits A_3-A_0 and B_3-B_0. +The 4 input bits are generated with the 'bits' instruction. The result (C_i, S_3-S_0) is also generated +by a 'bits' instruction. +This happens once with C_i-1 = 0 and in the next line with C_i-1 = 1. +In this way, 512 test rows are generated which cover all possible input configurations.</p> +<p>If multiple rows are to be repeated, or if nested loops are required, the loop +statement can be used. The above example could also be implemented as follows:</p> + +<pre> + C_i-1 A_3 A_2 A_1 A_0 B_3 B_2 B_1 B_0 C_i S_3 S_2 S_1 S_0 +loop(a,16) + loop(b,16) + 0 bits(4,a) bits(4,b) bits(5,a+b) + 1 bits(4,a) bits(4,b) bits(5,a+b+1) + end loop +end loop +</pre> + +<p>It may be helpful to generate random numbers in test cases. +These can be created with the function 'random([n])'. The generated number is greater +than or equal to zero and less than [n]. Considering a 16-bit multiplier as an example, +a full test can not be performed since it would have 2^32 input combinations. +A regression test that multiplies 100000 random numbers might look like this:</p> + +<pre> + A B Y +loop(i,100000) + let a = random(1&lt;&lt;16); + let b = random(1&lt;&lt;16); + (a) (b) (a*b) +end loop +</pre> + +<p>An input that allows high impedance as a value can also be used as a test output. +In this case, the signal name can be used with a trailing "_out" to read back and check the current value. +For this, the corresponding input must be set to high impedance ('Z').</p> + +<pre>OE CLK D D_out +0 0 0 0 +0 C 1 1 +1 0 z 1 +0 C 0 0 +1 0 z 0 +</pre> + +<p>The circuit for this test has only one input 'D', but which can be high impedance state. +Therefore, the signal 'D_out' is also available to check the value in this case.</p> + +</body></html> + Defines the output values. + With simple assignments like "A=1, B=0" outputs can be set. + With instructions like "A=101", multi-bit outputs can be set. + Outputs that are not defined here are set to zero in states. + For transitions, unspecified outputs remain unchanged. + The FSM is not deterministic: {0} + State Number {0} used twice. + There is no initial state (state number zero). + State ''{0}'' not found! + Wrong assignment to output (''{0}'')! + Error in condition ''{0}''! + <html><head></head> +<body> + <h3>Mouse Operation</h3> + <dl> + <dt>Create a state:</dt> + <dd>Right mouse click on a free area.</dd> + <dt>Creating a transition:</dt> + <dd>Right mouse button down on the start state and dragging to the destination state.</dd> + <dt>Delete a state or a transition:</dt> + <dd>Move the mouse over the object and press the [Del] button.</dd> + <dt>Moving a state or transition:</dt> + <dd>Left mouse button down and dragging.</dd> + <dt>Editing a state or a transition:</dt> + <dd>Right mouse click on the state or the transition.</dd> + </dl> + <h3>Layout Help Function</h3> + <dl> + <dt>no movement:</dt> + <dd>The layout help function is disabled.</dd> + <dt>Transitions:</dt> + <dd>The layout help function moves the transition arrows to avoid overlaps.</dd> + <dt>Transitions+States</dt> + <dd>The layout help function moves both states and transitions to help create a well-balanced layout.</dd> + </dl> + <h3>Interpretation of Transitions</h3> + To simplify the generation of a deterministic automata, unconditional transitions are treated in a special way: + an unconditional transition is only executed if no other transition satisfies the transition condition. + So there can be an unconditional transition and conditional transitions that start in the same state. + An unconditional transition thus determines to which state the state machine is shifted if no other transition + condition is met. + If there is no unconditional transition from a state, the state machine will stay in this state if no other + transition condition is met. +</body></html> + <html><body> + <h3>What can be seen in the graph?</h3> + Unlike a real logic analyzer, the X-axis of the measurement graph does not show the time. + Instead a counter is displayed which counts the changes of state in the circuit. + Whenever there is a change in the circuit, the counter is incremented and the new state is displayed.<br/> + You can also think of it as a classic logic analyzer, which does not save any data for optimization + if nothing has changed in the circuit. + However, this also means that it is not possible to read from the graph whether a lot or little time has + passed between two changes in the circuit.<br/> + This behavior is caused by the nature of the simulation: The simulation of the circuit does not know the + concept of time. A change is made to the circuit, and the change in the circuit state is calculated, until + the circuit has stabilized again. Then the next change is made, the effect of which is also is calculated + and so on. These changes are counted and the counter value is displayed on the X-axis of the graph.<br/> + Among other things, this also means that a circuit cannot be overclocked, since the effects of the falling + edge of the clock are not calculated until the circuit has stabilized after the previous rising edge. + </body></html> + Graphic RAM + Gr-RAM + Used to show a bitmap graphic. This element behaves like a RAM. In addition it + shows its content on a graphic screen. Every pixel is represented by a memory address. The value stored defines + the color of the pixel, using a fixed color palette. There are two screen buffers implemented to support page + flipping. The input B selects which buffer is shown. Thus, the total memory size is dx * dy * 2 words. + The palette used is structured as follows: The indices 0-9 correspond to the colors white, black, red, green, + blue, yellow, cyan, magenta, orange and pink. The indices 32-63 map gray values and the indices 64-127 + represent 64 color values each with two bits per color channel. + This results in a simple palette that can be addressed with only 7-bit. + If the architecture supports a 16-bit index, from Index 0x8000, a high-color mode with 5 bits per color channel + can be used, which enables 32768 colors. + The address to read and write. + If this input is high when the clock becomes high, the the data is stored. + Clock + If this input is high the output is activated and the data is visible at the output. + Selects the screen buffer to show. + The bidirectional data connection. + RAM, Dual Port + Memory with one port that allows to write and two ports that allow to read from + the memory simultaneously. Can be used to implement processor registers. + Two registers can be read simultaneously and a third can be written. + Output Port a + Output Port b + The register which is visible at port a. + The register which is visible at port b. + The register into which the data is written. + If this input is high and when the clock becomes high, the the data is stored. + Clock + The data to be stored in the register Rw. + A simple counter component. The clock input increases the counter. + Can be reset back to 0 with the clr input. + The number of bits can be set in the attribute dialog. + The clock input. A rising edge increases the counter. + Synchronous reset of the counter if set to 1. + Overflow output. This pin is set to 1 if the counter is on its maximal value + and the en input is set to 1. + Returns the counted value. + If set to 1 the counter is enabled! + A counter whose value can be set. In addition, a maximum value and a counting direction can be specified. + Counter + Returns the counted value. + Overflow output. It is set to 1 if the 'en' input is set to 1 and if the + counter reaches its maximum value when counting up, or has reached 0 when counting down. + The clock input. A rising edge increases the counter. + Synchronous reset of the counter if set to 1. + If set to 1 the counter is enabled! + Specifies the counting direction. A 0 means upwards. + If set, the value at input 'in' is stored in the counter at the next clock signal. + This data word is stored in the counter when ld is set. + Adder + Add + A component for simple add calculations. + Adds the two integer values from input a and input b (a+b). + The result will be incremented by one if the carry input is set. + First input to add. + Second input to add. + The result of the addition + Carry input, if set the result is incremented by one. + Carry output. If set there was an overflow. + Subtract + Sub + A component for simple subtractions. + Subtracts binary numbers on input a and input b (a-b). + If the carry input is set to 1 the result is decremented by 1. + Carry input, if set the result is decremented by one. + Input a for subtraction. + Input b for subtraction. + Output returns the result of the subtraction. + Output returns 1 if an overflow occurred. + Multiply + Mul + A component for multiplication. + Multiplies the integer numbers on input pin a and input pin b. + Input a for multiplication. + Input b for multiplication. + Output for the result of the multiplication. + Division + Div + A component for division. + Divides the integer applied to input a by the integer applied to input b. + If the divisor is zero, it is divided by one instead. + In signed division, the remainder is always positive. + dividend + divisor + quotient + remainder + Barrel shifter + shift + A component for bit shifting. + Shifts the input value by the number of bits given by the shift input. + Input with bits to be shifted. + Input with shift width. + Output with shifted value. + Comparator + A component for comparing bit values. + Compares the binary numbers on input pin a and input pin b and sets the corresponding outputs. + Input a to compare. + Input b to compare. + Output is 1 if input a equals input b + Output is 1 if input a is greater then input b + Output is 1 if input a is less then input b + Negation + Neg + Input of the data word to be negated in 2th complement + Returns the result of the negation in 2th complement. + Negation in the 2th complement + Sign extender + SignEx + Increases the bit width of a signed value keeping the values sign. + If the input is a single bit, this bit will be output on all output bits. + Input value. + The input bit width must be smaller than the output bit width! + Extended input value. + The input bit width must be smaller than the output bit width! + Bit counter + Bit count + Returns the number of 1-bits in the input value. + The input which 1-bits are counted. + Outputs the number of 1-bits. + Error starting the command {0} + Error while parsing generics code. + Video mode was not detected ({0}) + Avoids zero output. This is especially helpful when setting up relay circuits. + Can only be activated if a high-z output is allowed. + If e.g. four bits, two bits and two further bits are to be used as inputs, + this can be configured with "4,2,2". The number indicates the number of bits. For convenience, the asterisk + can be used: 16 bits can be configured with "[Bits]*[Number]" as "1*16". + It is also possible to specify the bits to be used directly and in any order. + For example, "4-7,0-3" configures bits 4-7 and 0-3. This notation allows any bit arrangement. + The input bits must be specified completely and unambiguously. + Output splitting + If e.g. four bits, two bits and two further bits are to be used as outputs, + this can be configured with "4,2,2". The number indicates the number of bits. For convenience, the asterisk + can be used: 16 bits can be configured with "[Bits]*[Number]" as "1*16". + It is also possible to specify the bits to be used directly and in any order. + For example, "4-7,0-3" configures bits 4-7 and 0-3. This notation allows any bit arrangement. + Output bits can also be output several times: "0-7,1-6,4-7" + Number of Selector Bits + Number of bits used for the selector input. + Signed Operation + If selected the operation is performed with signed (2th complement) values. + shift input has sign + shift input data has two complement format + Mode of barrel shifter + Logical + Rotate + Arithmetic + Show single gate steps + Shows all single step steps in the graphic. + Show measurement graph in single gate step mode at simulation start + When the simulation is started, a graph with the measured values in the + gate step mode is shown. All gate changes are included in the graph. + The description of the test case. + Details of the syntax can be found in the help dialog of the test data editor. + Makes this register a program counter. The value of this register is returned + to the external assembler IDE to mark the current line of code during debugging. + Relay is normally closed. + If set the relay is closed if the input is low. + Pole count + Number of poles available. + It is not possible to increase the frequency so much that the flickering disappears. + With this option you can stabilize the display by keeping the LEDs on until the common cathode goes down again. + This simulates a frequency above the critical flicker fusion frequency. + Unidirectional transistors propagate a signal only from source to drain. They are + much faster to simulate than bidirectional transistors. Since there is no feedback from drain to source, in this + mode, the transistor can not short the connected wires when it is conducting. Thus, this mode is necessary to + simulate certain CMOS circuits. + The inputs of the external process. + It is a comma-separated list of signal names. For each signal name, with a colon separated, a number of bits + can be specified. The inputs of an 8-bit adder could thus be described as "a:8,b:8,c_in". + The outputs of the external process. + It is a comma-separated list of signal names. For each signal name, with a colon separated, a number of bits + can be specified. The outputs of an 8-bit adder could thus be described as "s:8,c_out". + Path to the executable ghdl file. Only necessary if you want to use ghdl to simulate + components defined with vhdl. + MIDI channel + Selects the MIDI channel to use. + MIDI instrument + The MIDI instrument to use. + Allow program change + Adds a new input PC. If this input is set to high, + the value at input N is used to change the program (instrument). + Switch behaves like an input + If the model is analyzed, the switch behaves like an input, where "open" corresponds to '0' and "closed" to '1'. + Diode to VDD + A simplified unidirectional diode, used to pull a wire to VDD. + It is used to implement a wired OR. + So it is necessary to connect a pull down resistor to the diodes output. + In the simulation the diode behaves like an active gate with a trivalent truth table: + Is the input high, also the output is high. In all other cases (input is low or high z) the output is in high z state. + So two anti parallel connected diodes can keep each other in high state, which is not possible with real diodes. + This is an ideal diode: There is no voltage drop across a forward-biased diode. + If the input is high also the output is high. In all other cases the output is in high z state. + If the input is high also the output is high. In all other cases the output is in high z state. + Diode to Ground + A simplified unidirectional diode, used to pull a wire to ground. It is used to implement a wired AND. + So it is necessary to connect a pull up resistor to the diodes output. + Is the input low, also the output is low. In the other cases (input is high or high z) the output is in high z state. + So two anti parallel connected diodes can keep each other in low state, which is not possible with real diodes. + So this is a ideal diode: There is no voltage drop across a forward-biased diode. + If the input is low also the output is low. In all other cases the output is in high z state. + If the input is low also the output is low. In all other cases the output is in high z state. + Switch + One of the connections of the switch. + Simple switch. + There is no gate delay: A signal change is propagated immediately. + Double Throw Switch + Double Throw Switch. + There is no gate delay: A signal change is propagated immediately. + Fuse + A fuse used to build a one time programmable memory. + One of the connections of the fuse. + One of the connections of the fuse. + Relay + A relay is a switch which can be controlled by a coil. + If a current flows through the coil, the switch is closed or opened. + There is no flyback diode so the current direction does not matter. + The switch is actuated if the inputs have different values. + The relay behaves similar to an XOr gate. + On of the inputs to control the relay. + On of the inputs to control the relay. + Double Throw Relay + A relay is a switch which can be controlled by a coil. + If a current flows through the coil, the switch is closed or opened. + There is no flyback diode so the current direction does not matter. + The switch is actuated if the inputs have different values. + The relay behaves similar to an XOr gate. + On of the inputs to control the relay. + On of the inputs to control the relay. + P-Channel Field Effect Transistor. + The bulk is connected to the pos. voltage rail and the transistor is simulated without a body diode. + Gate + Source + Drain + N-Channel FET + N-Channel Field Effect Transistor. + The bulk is connected to ground and the transistor is simulated without a body diode. + Gate + Source + Drain + P-Channel floating gate FET + P-Channel Floating Gate Field Effect Transistor. + The bulk is connected to ground and the transistor is simulated without a body diode. + If there is a charge stored in the floating gate, the fet isn't conducting even if the gate is low. + Gate + Source + Drain + N-Channel Floating Gate Field Effect Transistor. + The bulk is connected to ground and the transistor is simulated without a body diode. + If there is a charge stored in the floating gate, the fet isn't conducting even if the gate is high. + Gate + Source + Drain + Transmission-Gate + A real transmission-gate is build from only two transistors. + Therefore, it is often used to save transistors during implementation on silicon. + input A + input B + control input. + inverted control input + Has no function. Makes sure that VDD and GND are connected. + Can be used in 74xx circuits to generate the pins for the voltage supply, which are tested for correct wiring. + Must be connected to VDD! + Must be connected to GND! + The output of this component is held high during the initialisation of the circuit. + After the circuit has stabilized the output goes to low. + If the output is inverted it behaves the opposite way. + If this component is used in the circuit, the "Run To Break" button between "Start" + and "Stop" is enabled. This button clocks the circuit until a rising edge on the input of this component is + detected. This element can be used for debugging by clocking the circuit to any breakpoint. + Also an assembler command BRK can be implemented. This allows to execute a program up to the next BRK command. + This function can only be used if the real-time clock is deactivated! + Simplified bidirectional diode. It is used to implement a wired AND or a wired OR.. + This is a ideal diode: There is no voltage drop across a forward-biased diode. + It's not allowed to connect a pull up and a pull down resistor to a single wire. + Could not open the browser. + Could not create folder "{0}"! + It is not allowed to connect only inputs to a switch. + The file {0} exists multiple times below {1}. + Could not find the file {0}. + Error during execution of "{0}". + The process "{0}" does not return! + The process returns the non zero value {0}: {1} + Error starting the external fitter! + There are no minimized equations! + Equations are calculated! Please wait a moment! + The variable {0} is used twice! + The file needs to be saved! + The circuit {0} imports itself! + The result of the minimization is not correct! + The names of the variables may not be unique. + To many iterations in a loop. + Diode needs a pull up resistor at its output! + Diode needs a pull down resistor at its output! + Test signal {0} not found in the circuit! + Only {1} bits allowed, but {0} bits found! + Flip-flops with more than one bit are not allowed! + The two control inputs of a transmission gate must be inverted! + Signal {0} is used twice! + Error parsing the test data. + The model component {0} can not be analysed. + Error in wiring of power supply at {0}. + The pin number {0} is not an integer! + Error during export to VHDL. + No VHDL code for {0} available! + No Verilog code for {0} available! + Error creating a test bench! + Values of typ {0} are not allowed! + A name is missing. Have e.g. all pins a label set? + Several outputs are connected to each other. + This type of interconnection is not supported for HDL export. ({0}, {1}, {2}). + unnamed net + To many variables! + Invalid expression! + Function {0} not found in line {1}! + Number of arguments in function {0} in line {1} not correct (found {2}, expected {3})! + Invalid value {0} in function {1}! + The name {0} is not a path element. + Error during loading of a library. + The JAR file contains no manifest! + The manifest does not contain a Main-Class entry! + Could not find the class {0}! + Could not create an instance of the class {0}! + There must be more input bits than output bits! + It is not possible to set physical pins to constant values! + The string {0} is not a valid number (pos {1})! + The name "{0}" is not allowed! + No white space is allowed in the name of the TT2 file! + The table has too many columns! + Error writing the zip file. + Only one clock component with high frequency is allowed. + The circuit contains cycles. It's not possible to analyze such a circuit. + Cycles arise if an output of a gate is fed back to one of the inputs of the same gate. + The use of switches, FETs or relays also causes cycles. + If a monoflop is used, there must be exactly one clock component! + Could not create a component of type {0}! + ROM's defined in the settings are not supported! + The name "{0}" is not unique! + Could not write values to the external process! + Could not read values from the external process! + Could not create the external process! + Timeout reading data from external process! + {0} + Not enough data received! + {0} + The received text contains an invalid character: {0}! + {1} + The process has terminated unexpected! + {0} + Could not terminate the process! + Could not start process: {0} + Application exit status was not 0 but {0}: + {1} + External code can only be exported if it is VHDL! + External code can only be exported if it is Verilog! + If an external component is used multiple times, the code must be identical! Effects: {0} + Could not write to stdOut: + {0} + The VHDL simulator ghdl does not seem to be installed. Install ghdl (http://ghdl.free.fr/) and try again. If there are still problems, check the path to the ghdl executable in the Digital settings. + The Verilog simulator Icarus does not seem to be installed. Install iverilog (http://iverilog.icarus.com/) and try again. If there are still problems, check the path to the iverilog executable in the Digital settings. + Error analysing the circuit: {0} + Every ROM needs a unique label to be exported! + Every LUT needs a unique label to be exported! + The counter needs at least two bits. + Clock elements can not be used in asynchronous mode. + Error during export to Verilog. + No program memory found! The program memory needs to be flagged as such. + Error loading the program memory. + Error while reading the SVG file. + The SVG file contains pins that do not exist in the circuit. + All memories into which data are to be loaded require the same bit width. + If programs are to be loaded into several RAMs, all RAMs must have + different names. The lexical order then determines the order of the RAMs. + The MIDI-System is not available. + The MIDI channel {0} is not available. + The MIDI instrument {0} is not available. + The MIDI instruments are not available. + During the execution of the tests "{0}" an error has occurred! + HDL not known: {0} + There is a unnamed input or output! + The signal name "{0}" is invalid or used multiple times! + Error when substituting components for the analysis. + Error in the evaluation of the generic code of the circuit. Code + {1} + at Component: {0} + diff --git a/src/test/java/de/neemann/digital/docu/DocuTest.java b/src/test/java/de/neemann/digital/docu/DocuTest.java index a1e2a237f..c59b9af27 100644 --- a/src/test/java/de/neemann/digital/docu/DocuTest.java +++ b/src/test/java/de/neemann/digital/docu/DocuTest.java @@ -59,6 +59,8 @@ public class DocuTest extends TestCase { .append(Lang.get("tableOfContent")) .append("\" lang=\"") .append(language) + .append("\" fontFamily=\"") + .append(language.equals("zh") ? "SansSerif,SimSun" : "SansSerif") .append("\" rev=\"") .append(System.getProperty("buildnumber")) .append("\" revt=\"") diff --git a/src/test/java/de/neemann/digital/docu/ScreenShots.java b/src/test/java/de/neemann/digital/docu/ScreenShots.java index 21337104f..de7d20d58 100644 --- a/src/test/java/de/neemann/digital/docu/ScreenShots.java +++ b/src/test/java/de/neemann/digital/docu/ScreenShots.java @@ -91,6 +91,13 @@ public class ScreenShots { .set(Keys.SETTINGS_IEEE_SHAPES, true); firstSteps(); hierarchicalDesign(); + + // Chinese + Lang.setActualRuntimeLanguage(new Language("zh")); + Settings.getInstance().getAttributes() + .set(Keys.SETTINGS_IEEE_SHAPES, true); + firstSteps(); + hierarchicalDesign(); } private static void mainScreenShot() { @@ -316,7 +323,7 @@ public class ScreenShots { .add(new ScreenShot<>(TableDialog.class).useParent()) // k-map .press("F10") - .press("RIGHT", 5) + .press("RIGHT", 4) .press("DOWN", 1) .add(new ScreenShot<>(TableDialog.class).useParent()) .press("ENTER") diff --git a/src/test/resources/docu/elem2fo.xslt b/src/test/resources/docu/elem2fo.xslt index 833a5533e..e6b1a76dd 100644 --- a/src/test/resources/docu/elem2fo.xslt +++ b/src/test/resources/docu/elem2fo.xslt @@ -6,17 +6,17 @@ / - + + margin-top="2cm" margin-bottom="1cm" + margin-left="2.5cm" margin-right="2.5cm"> + margin-left="0cm" margin-right="0cm"/> - + diff --git a/src/test/resources/docu/fop.xconf b/src/test/resources/docu/fop.xconf index b5ac46d6c..4fffd7117 100644 --- a/src/test/resources/docu/fop.xconf +++ b/src/test/resources/docu/fop.xconf @@ -112,6 +112,11 @@ the location of this file. for details of FOP configuration for AFP --> + + + + + diff --git a/src/test/resources/docu/images/zh/scr00.png b/src/test/resources/docu/images/zh/scr00.png new file mode 100644 index 000000000..650d0a382 Binary files /dev/null and b/src/test/resources/docu/images/zh/scr00.png differ diff --git a/src/test/resources/docu/images/zh/scr01.png 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b/src/test/resources/docu/static_zh.xml @@ -0,0 +1,449 @@ + + + + + + Digital 是一个简单的数字电路仿真器。通过导线将各种逻辑门连接起来，可以仿真整个电路的行为。 + 用户可以通过点击按钮或者设置输入值实现交互式仿真。 + + + 通过这种方式，多数数字电路中的基本电路可以被构建和仿真。在 "examples" 文件夹内，用户可以浏览各种示例，如 + 1个16位的单周期哈佛架构处理器。 + + + 仿真器有两种操作模式：编辑和仿真模式。 + 在编辑模式，不允许仿真，只允许修改电路。用户可以添加或连接各种组件。 + 可以通过点按工具栏中的 "启动仿真电路" 按钮开启仿真模式。在开始仿真电路之前，将会先检测电路的一致性。 + 如果有某些错误，将会显示对应的消息提示并且相关的组件或导线将会高亮。如果没有任何错误，将会开启仿真模式。这时， + 你可以和正在运行的仿真进行交互。 + + + + + + 作为第一个示例，将会构建一个由异或门组成的电路。在主窗口，"组件" 菜单允许我们选择各种组件。 + 然后它们会被放置于绘图面板。在任何时候，可以通过 ESC 键取消操作。让我们开始选择一个输入组件，该组件在 + 仿真时可以通过鼠标交互进行控制。 + + + 选择后，输入组件可以被放置在绘图面板。 + 红色的点表示组件和导线之间的连接点，在之后会被连接。同时红色表示输出，意思为该端口定义了一个信号，该信号可以驱动导线。 + + + + 使用同样的方式，添加第二个输入组件，最好将其放置在第一个输入组件下面。 + + + 添加完输入组件，我们选中异或门。该门表示实际的逻辑功能。 + + + + 选中后我们可以将其添加到电路。最好将其放置在合适的位置使得后续的连线尽可能简单。蓝色的点表示门的输入端口。 + + + + 现在，选择一个输出组件，该组件用于显示一个信号状态或者传递信号给一个子电路。 + + + + 输出组件有一个蓝色的点，意思为输入端口，我们可以通过为其赋值以便之后使用。 + + + + 当所有组件放置好后，使用鼠标连接蓝色和红色的点。确保仅有一个红色的点被连接到任何蓝色的点。只有允许三态的输出可以 + 打破该规则，允许连接到多个红色的点。当所有导线被绘制后，整个电路即完成。 + + + + 当仿真启动后，我们可以和电路进行交互。通过点击 “启动仿真电路” 按钮开始仿真。 + 仿真开启后，导线的颜色改变并且输入、输出组件被填充。鲜绿色表示逻辑电平 ‘1’，深绿色表示逻辑电平 ‘0’。 + 在上图中，所有的导线为 ‘0’。 + + + + 通过鼠标点击，可以切换输入组件的值。由于仿真已经运行，输出组件的值根据当前输入的状态而做出对应改变。电路的行为 + 和期望的异或门一样。 + + + + 如果需要修改电路，必须先停止仿真。最简单的方式是通过点击工具栏的 “停止” 按钮。 + 通过在组件上右击（MacOS 使用 control+左击）打开组件属性对话框。通过该对话框，我们定义第一个输入组件的标签为 ‘A’。 + + + + 通过同样的方式，定义剩余组件的输入和输出端口标签。 + "分析" 菜单包含一个同名的菜单项，该功能对当前电路进行分析。不过，需要先给所有的输入和输出端口添加标签才行。 + + + + 仿真电路的真值表在一个新窗口中显示，在表的下面，我们可以找到一个和电路对应的布尔表达式。如果电路可能有多个布尔 + 表达式，一个独立的窗口将会打开并显示所有可能的表达式。 + + + + 真值表对话框有一个 "卡诺图" 菜单项，允许以卡诺图方式显示真值表。 + + + + 在对话框的顶部，通过下拉列表允许选择期望的表达式。通过这种方式，我们可以评估多个等价的布尔表达式。然而，在该示例中， + 仅有一个最小表达式。点击卡诺图，可以实现对真值表的修改。 + + + + + 所有的组件必须通过导线连接起来。不可以通过将两个组件相邻放置实现连接。 + + + 另外，仅可以通过导线的端点连接到组件，如果一个组件的管脚放置在一条导线中间，该组件和导线并不会实现连接。 + 因此，导线必须在其所连接的管脚终止。即使使用隧道组件，也必须使用导线连接管脚和隧道组件。 + + + 如果需要移动组件，包括其连接的导线，则必须先框选该组件，如果不想同时移到其连接的导线，可以通过单击选择组件。 + + + 通过 CTRL-单击，可以选中且移动或删除一个单独的导线段。如果在画导线时按下 D 键，可以绘制斜线。 + 键 S 可以将一条线段分割为两条。 + + + + + 随着电路越来越复杂，电路将变得难以理解。为解决该问题，电路中不同的部分可以存放在不同的文件。该机制使得 + 使用子电路变为可能。 + + + + 作为一个示例，我们考虑4位加法器：首先，我们构建一个简单的半加器，其包含一个异或门和一个与门。 + 位 ‘A’ 和 ‘B’ 相加的结果通过 ‘S’ 和 ‘C’ 输出。该电路存储在文件 "halfAdder.dig"。 + + + + 使用两个半加器可以构建一个全加器。 + 创建一个空文件并保存为 "fullAdder.dig"，将其放在和半加器相同的路径下。这时，可以通过菜单"组件""自定义" + 将半加器添加进电路。 + 半加器的管脚顺序可以在半加器电路中通过菜单 "编辑""排序输入信号" 或者 "编辑""排序输出信号" + 重新排序。全加器实现将位 ‘A’，‘B’，‘Ci’ 相加，结果给到输出 ‘S’ 和 ‘Co’。 + + + + 为了检验全加器正常工作，我们需要添加一个测试用例。在测试用例中存储满足电路功能的真值表，通过这种方式，可以自动 + 测试电路功能是否正确。 + + + + 可以通过测试用例编辑器或工具栏中的测试按钮执行测试。 + 绿色高亮的单元格表示电路的输出和测试用例中的真值表相匹配。 + + + + 现在可以通过全加器进一步构建逐位（行波）进位加法器;。 + 在该示例中，前一个加法器的进位输出作为下一级加法器的进位输入，就像使用纸和笔进行加法一样。 + 为了测试该 4 位加法器的功能，我门添加了一个测试用例。 + + + + 该测试用例执行 100% 测试，这对于相对简单的电路是可能的。在这里，所有的512种输入组合被应用于电路，同时检测其输出是否 + 正确。 + 第一行列出输入和输出信号，下面的内容应用输入值并检测其对应的输出，像真值表一样。 + 在该示例中，需要512行。然而这样输入即繁琐又容易出错，如果能够自动生成所需要的行，则更容易和可靠。 + 为此，变量 "A" 和 "B" 分别被分别从0到15进行遍历。对应的值被赋值给 ‘A[n]’ 和 ‘B[n]’。然后检测电路输出 + 是否为 "A+B"。然后再次检测当设置进位时，即 "A+B+1" 的对应结果。详细的测试语法可以通过帮助对话框查看。 + + + 如果一个电路被嵌入另外一个电路，仅仅子电路的名字被保存在父电路而不是子电路本身。 + 因此，在仿真时，必须可以通过文件系统找到对应的子电路。为了避免复杂的导入路径管理，使用以下导入策略。 + + + 仅仅子电路的文件名而不是完整的文件路径被存储。如果需要打开某个子电路，需要在所有的子文件夹下寻找。 + 该过程仅依赖文件名称而不是完整路径，当在不同路径下有多个同名文件时，将会给出错误信息。 + + + 一个合理的项目结构看起来应当时这样的：根电路放在独立的文件夹下，所有导入的子电路必须放在相同和子文件夹下。 + 所有的电路必须不能重名，即使位于不同的文件夹内。 + + + + + + + 在仿真时，所有的逻辑门均有一个传输延迟。所有的组件具有相同的传输延迟而与其复杂度无关。 + 因此，与门和乘法器具有相同的传输延迟。特例是二极管，开关和分裂器，这些组件没有任何延迟。 + + + 如果需要仿真一个组件如乘法器更长的传输延迟，必须在乘法器的输出右侧添加一个延迟组件。 + + + 如果一个电路被包含进另一个父电路，被包含的电路保持其时序行为。被包含的电路同将其所有组件直接插入父电路行为一致。 + + + + + + 可以通过 "分析" 菜单来分析电路。对于纯组合电路，会生成对应的真值表。可以编辑该真值表，然后从编辑后的真值表生成 + 新的电路。 + + + 分析和生成时序电路也是可能的。此时，会生成状态转换表而不是简单的真值表。 + 每个触发器在状态转换表的输入和输出侧都会显示。在该表中，右侧为下一个状态，其会在下一个时钟信号产生。 + 下一个状态依赖左侧触发器的当前状态。为了能够分析电路，必须为触发器命名。 + + + 右侧的下一个状态通过小写的 ‘n+1’ 表示，对应的当前状态通过附加 ‘n’ 表示。如果状态变量为 ‘A’, ‘An’ 表示当前状态， + ‘An+1’ 表示下一个状态。在一个真值表中，如果信号的名称以此方式命名，则被认为时状态转换表，会生成时序电路而不是组合电路。 + + + 需要注意的是，需要分析的电路仅可包含纯组合电路和内建的 D、JK 触发器。如果一个触发器由用户自己构建，如使用或非门 + 组成，则该电路不被认为触发器，因此不可以分析这种电路。 + + + + + + 在真值表对话框电路生成菜单中，有生成 JEDEC 文件的功能。这是一种描述 PLD 配置图（fuse map）的特殊文件格式。 + 该 JEDEC 文件可以通过特殊的编程器烧写进对应的 PLD 设备。目前，支持 "GAL16v8" 和 "GAL22v10" 或其兼容的设备。 + + + + + + "ATF150x" + + 系列芯片是简单的 CPLDs，其最多有128个宏单元。具有 PLCC 封装。这样，如果一个 IC 在实验中被毁坏，那么其可以被 + 简单的替换。另外，通过 + + "ATDH1150USB" + + 廉价和易用的编程器，可以使用 JTAG 接口编程 + + "ATF150x" + + 芯片。 + 一个合适的评估开发板为 + + ("ATF15XX-DK3-U") + + ，编程所需要的软件 + + "ATMISP" + , + 通过 ATMEL/Microchip 网站提供。 + + + + + 电路可以导出为 VHDL 或 Verilog，导出文件包含电路的完整描述。生成的 VHDL 代码通过了Xilinx Vivado + 和开源 VHDL 仿真器 ghdl 的测试。Verilog 代码通过了仿真器 Icarus Verilog 的测试。 + + + 如果电路包含测试用例，测试数据用于生成对应的 HDL 测试平台（test bench），可用于在 HDL 仿真时检测电路功能的正确性。 + + + 对于一些开发板，会为其生成额外所需的文件。目前，支持 BASYS3 + 和 Mimas 开发板 Mimas + 和 Mimas V2。 + 包含管脚分配的约束文件将会被创建。可以在开发板的数据手册中查找其管脚描述，并为输入和输出组件分配管脚编号。 + + + 对于 BASYS3 板子，如果电路的时钟频率比较低，在生成的 HDL 代码中将包含一个分频器，从而合理的对板载的时钟进行分频。 + 如果电路的时钟频率超过 4.7MHz，则使用 Artix-7 的 MMCM 单元用于生成时钟。 + + + + 为了创建 HDL 需要的约束文件，必须在设置中配置对应的开发板。在字段 “工具链配置” 中，可以设置对应的 XML 文件。 + 在 "examples/hdl" 目录下，可以找到以 ".config" 为后缀的可用配置文件。 + 如果配置文件正确，会在主菜单右侧显示对应的功能菜单。 + + + + + + 尽管 Digital 有些内建的选项可以设置子电路的外观，但在某些时候，需要使用更特殊的形状来显示子电路。如当表示处理器 + 中的 ALU 时，本节解释如何为电路定义一个特殊的形状。 + + + Digital 没有提供一个用例创建特殊形状的编辑器。 + 为了创建电路形状，需要一些特殊步骤：首先，打开需要创建特殊外观形状的电路，然后为该电路创建一个 SVG 模板，在 + 该模板中，电路表示为一个简单矩形，另外还包含电路中所有的管脚，其中输入使用蓝色圆圈表示，输出使用红色圆圈表示。 + 可以通过查看圆圈的 ID 对象属性了解该圆圈属于哪个管脚。ID 格式为 "pin:[name]" 或 "pin+:[name]"。 + 对于后者，当导入 Digital 时，管脚将被包含一个标签。 + + + SVG 文件可以被编辑，如使用最常用的开源编辑器Inkscape。 + 管脚可以自由移动，但在重新导入 Digital 时，其被替换为最近的栅格坐标位置。 + + + 当导入Digital后，所有的信息将被提取和保存在电路文件中，SVG 文件不再需要。 + 最后提示：SVG 是一种非常强大和灵活的文件格式。可用于描述非常复杂的图形。 + Digital 并不能导入所有可能的 SVG 文件。如果一个文件不能被导入，可能会出现异常。 + + + + + 有这样一种情形，一个子电路用于多种变形。如需要一个不同位宽的计数器，分别用于创建一个 4,5,6位宽的电路， + 这样，将来维护时会非常困难。因为我们必须维护多个子电路，然而这些子电路除了一个位宽参数，其它都相同。 + + + 为解决该问题，我们可以创建一个通用参数化的部分电路。 + 为此，电路设置中的 “通用电路” 复选框必须被选中，然后每个组件的属性对话框包含一个额外的字段 “通用参数”。 + 在该字段中，可以输入程序代码用来改变组件的参数。 + 每个参数须有一个名字，可以作为字段"this"的属性被修改。可用参数的名称可以通过组件的帮助对话框查看。 + 如果我们需要改变加法器的位宽，可以通过 "this.Bits=int(1);" 实现，这里的常量 1 始终是 "long" + 类型，但位宽是 "int"，因此必须使用类型转换。 + + + 此时，电路仍然没有被参数化。这种情形是必要的，即当电路实际被使用时给出参数。 + 这可以通过 “args” 字段来实现。如果我们想在外部设置位宽，代码可以这样 "this.Bits=int(args.bitWidth);"。 + 参数的名称-这里为 "bitWidth" 是任意的。当实际使用该电路时，需要设置参数 "bitWidth"：。 + + + 当使用电路时，打开子电路的属性对话框，其也有一个 “通用参数” 字段。这里可以通过输入 "bitWidth:=5;" + 来实现设置位宽。 + + + "examples/generic" 文件夹包含一个格雷码计数器的例子，其位宽可以被配置。 + + + + + 如果学生通过 Digital 来完成测验，能够自动测试学生提交的电路将会非常有帮助。为实现这种测试，可以通过命令行启动 Digital： + + + + java -cp Digital.jar de.neemann.digital.testing.CommandLineTester [file to test] [[optional file with + test cases]] + + + + 如果仅指定一个文件，则该文件中的测试用例将被执行。 + + + 如果指定了第二个文件，则使用第二个文件中的测试用例和第一个文件中的电路进行测试。第二个文件中的电路将被忽略。 + + + 此时，待测电路和测试用例中的电路输入输出信号名称必须相同。 + + + + + 如何移动导线？ + 选择其中一个端点或通过 CTRL+单击选择导线，移动鼠标。 + + + + 如何删除导线？ + + 选择其中一个端点或通过 CTRL+单击选择导线，然后按 "DEL" 键。 + + + + 如何移动组件，包括其所连接的导线？ + 框选整个组件 + + + + 当组件管脚放在导线上时没有连接 + 仅当导线的端点位于管脚时才会连接 + + + 如果管脚的名字比较长，当作为子电路时，管脚名字无法阅读 + 通过菜单 "编辑设置当前电路" 修改组件的宽度 + + + + 修改子电路管脚的顺序 + 菜单 "编辑排序输入信号" 或 + "编辑排序输出信号" + + + + 当开始仿真时，导线颜色变为灰色 + + 鲜绿色表示高电平，深绿色表示低电平，灰色表示高阻。 + + + + 我有一个真值表，如何计算最小布尔表达式？ + + 通过菜单 "分析" 选择 "综合"，然后输入真值表。在窗口底部，你会发现匹配的布尔表达式。 + + + + + 我输入真值表后，显示多个布尔表达式，哪个是正确的？ + + + 化简一个布尔表达式可能出现多个结果，它们描述同样的功能 + + + + 我有一个真值表，如何创建对应的电路？ + 通过菜单 "分析" 选择 "综合"，然后输入真值表。 + 使用菜单 "创建" "电路" 可以创建对应的电路。 + + + + 如何编辑真值表中信号的名称？ + 在表头中右击信号名称 + + + 如何根据表达式创建电路？ + 通过菜单 "分析" "表达式"，输入表达式。 + + + + 如何通过表达式创建真值表？ + 菜单 "分析" "表达式" 输入表达式，创建电路。 + 然后通过菜单 "分析" "分析" 创建真值表。 + + + + 我创建了一个电路，想把它用于很多电路，如何才能不重复的复制到不同的文件夹下？ + + 放在 “lib” 文件夹内 + + + + + + 开启或停止仿真 + 打开测量表对话框 + 运行至中断 + 执行测试用例 + 时钟步进（仅在仿真模式且只有一个时钟组件时可用） + + 单门步进 + 执行所有单门步骤，直至中断或完成 + 分析电路 + 选择所有 + 剪切 + 复制 + 从剪贴板插入 + 复制当前选中而不更改剪贴板 + 旋转组件 + 插入最近一次插入的组件 + 插入隧道组件 + 新建电路 + 打开电路 + 保存电路 + 撤销上次修改 + 重做上次撤销操作 + 对二极管或浮动栅场效应管编程 + 画导线时使用对角线模式 + 画线时翻转方向 + 分割一条导线为两条 + 放弃当前操作 + 删除 + 删除 + + 加1 + + 减1 + + 放大 + 缩小 + 适合窗口 + 显示或隐藏组件树 + + + \ No newline at end of file diff --git a/src/test/resources/docu/static_zh_ref.xml b/src/test/resources/docu/static_zh_ref.xml new file mode 100644 index 000000000..e44d9153e --- /dev/null +++ b/src/test/resources/docu/static_zh_ref.xml @@ -0,0 +1,741 @@ + + + + + + Digital is a simple simulator used to simulate digital circuits. The logic gates are connected + to each other by wires and the behavior of the overall circuit can be simulated. + The user can interact with the simulation by either pressing buttons or setting + values to the inputs of the circuit. + + + In this way, most of the basic circuits used in digital electronics can be built and simulated. + In the folder examples, users can browse for examples that includes a functional + 16-bit single-cycle Harvard processor. + + + The simulator has two modes of operation: Editing and Simulation mode. + In the editing mode, modifications to the circuit can be performed. Users can add or connect components. + In this mode, simulation is disabled. + The simulation mode is activated by pressing the Start button in the tool bar. + While starting the simulation the circuit is checked for consistency. + If there are errors in the circuit an appropriate message is shown and + the affected components or wires are highlighted. If the circuit is error free, the simulation is + enabled. Now you can interact with the running simulation. + In the simulation mode it is not possible to modify the circuit. To do so you have to activate the + editing mode again by stopping the simulation. + + + + + + + + As a first example, a circuit is to be constructed with an Exclusive-Or gate. + From the main window, the Components menu allows you to select the various components. + Then they are placed on the drawing panel. This process can be canceled by pressing the ESC key at any + time. Start by selecting an input component. + This can later be controlled interactively by using the mouse. + + + + + After selection, the first input can be placed on the drawing panel. + The red dot on the input component symbol is a connection point between the component and a wire, + which will be + connected later on. + The red color indicates an output. This means that the port defines a signal value or can drive a + wire. + + + + + + In the same way, a second input is added. It is best to place it directly below the first input. + + + + + After adding the inputs, the Exclusive-Or gate is selected. This gate represents the actual logical + function. + + + + + + This gate can now also be added to the circuit. It is best to place it in a way that the subsequent + wiring is made as simple as possible. The blue dots indicate the input terminals of the gate. + + + + + + Now, select an output which could be used to display a signal state or to later pass signals to + an embedding circuit. + + + + + + This is placed in a way that it can be wired easily. + The output has a blue dot, which indicates an input terminal. + Here you can feed in the value which is then exported. + + + + + + After all components are selected and in place, use the mouse to wire a connection between the blue and + red dots. Make sure that exactly one red dot is connected to any number of blue dots. + Only the usage of three-state outputs makes it possible to deviate from this rule and to interconnect + several red dots. + If all wires have been drawn, the circuit is complete. + + + + + + Interaction with the circuit is possible when simulation is started. + This is done by clicking on the play button located in the toolbar. + After starting the simulation, the color of the wires changes and the + inputs and outputs are now filled. Bright green indicates a logical '1' and dark green a logical '0'. + In the figure above, all wires have a '0' value. + + + + + + By clicking with the mouse, the inputs can be switched. Since the simulation is now active, the + output changes according to the current input states. The circuit behaves like an + Exclusive-Or gate as expected . + + + + + + To further process the circuit, the simulation must first be stopped. The easiest way to do this is + with the Stop button in the tool bar. Clicking on a component with the right mouse button + (control-click on MacOS) opens a dialog which shows the component's properties. The label 'A' can + be defined for the first input via this dialog. + + + + + + In this way, the labels for the remaining inputs and outputs can be defined. The menu item + Analysis + also contains a menu item Analysis. This function performs an analysis of + the current circuit. However, this is only possible if all inputs and outputs are labeled properly. + + + + + + The truth table of the simulated circuit appears in a new window. Below the table you can find the + algebraic expression associated with the circuit. If there are several possible algebraic + expressions, a separate window will open, showing all possible expressions. + + + + + + The table dialog has the menu entry K-Map in its main menu. This allows to display the truth + table in the form of a K-map. + + + + + + At the top of this dialog there is a drop-down list which allows the selection of the desired + expression in the K-map. In this way you can, for example, illustrate how several equivalent + algebraic expressions can result. However, in this example, there is only one minimal expression. + The truth table can also be modified by clicking the K-map. + + + + + All components must be connected via wires. It is not possible to connect two components + by placing them directly next to each other. + + + In addition, there are only connections between an endpoint of a wire and a component. + If a pin of a component is placed in the middle of a wire, no connection is made between the component + and the wire. + Therefore, a wire must actually terminate at each pin which is to be connected. + Even if the tunnel component is used, there must be a wire between the pin and the tunnel element. + + + The component needs to be selected using the rectangular selection tool in order to be moved, + including the connected wires. For moving a component without the connected wires, + select the component using a mouse click. + + + With CTRL-Click a single wire section can be selected to move or delete it. + If the D key is pressed while drawing a wire, a diagonal wire can be drawn. + The key S allows the splitting of a line segment into two segments. + + + + + If a complex circuit is built up, this can quickly become very confusing. To keep track here, + the different parts of a circuit can be stored in different files. This mechanism also makes it + possible to use a subcircuit, which has been created once, several times in a further circuit. + This approach also offers the advantage that the files can be stored independently of each other in a + version control system and changes can be tracked. + + + + + + As an example, consider a 4-bit adder: First, we built a simple half-adder. This consists of an + XOR gate and an AND gate. The sum of the two bits 'A' and 'B' is given to the outputs 'S' and 'C'. + This circuit is stored in the file halfAdder.dig. + + + + + + From two half adders a full adder can now be built. To do this, create a new empty file and save the + empty file as fullAdder.dig in the same folder as the half adder. Then the + half adder can be added to the new circuit via the + Components + + Custom + menu. + The order of the pins at the package of the half-adder can be rearranged in the half adder in the + menu + Edit + + Order inputs + or + Edit + + Order outputs. + The full adder adds the three bits 'A', 'B' and 'Ci' and gives the sum to the outputs 'S' and 'Co'. + + + + + + In order to check the correct function of the full adder, a test case should be added. In the test case, + the truth table is stored, which should fulfill the circuit. In this way it can be automatically + checked whether this is the case. + + + + + + The tests can be executed via the test case editor or the test button in the toolbar. + The table cells highlighted in green indicate that the output of the circuit matches + the truth table given in the test case. + + + + + + Now the full adders can be put together to form a so-called ripple-carry adder. + In this case, the carry output of an addition is forwarded as a carry input to the addition of the + next higher-order bit, just as is usual in pencil-and-paper addition. + This 4-bit adder should be tested for correct function. For this purpose a test case was inserted. + + + + + + This test case performs a 100% test, which is possible only with relatively simple circuits: all + possible 512 input combinations are applied to the circuit, and it is checked whether the output + of the circuit is correct. + The first line lists the input and output signals. Below this, the input values to be applied and + the output values to be checked are specified in a row, as in a truth table. + In this example, however, 512 lines are required. Entering this would be a tedious and error-prone task. + It is easier and more reliable to automatically generate the required lines. + For this purpose, the variables A and B are each traversed + from 0 to 15. The respective values of A and B are then assigned to inputs 'A[n]' and + 'B[n]'. + Then it is checked whether the circuit outputs the value A+B. Then it is checked again with + the carry bit set, in which case A+B+1 must result. + The details of the test syntax are provided by the help dialog. + + + If a circuit is embedded in an other circuit, only the file name of the subcircuit is stored in a + circuit, not the embedded circuit itself. + The corresponding files of + the embedded subcircuits must therefore be found in the file system at runtime of the simulation. + In order to support the various work methods of the users as best as possible and still to avoid a + complex administration of import paths, etc., a somewhat unusual import strategy is implemented. + + + Only the file names of the embedded circuits are stored in a circuits file, not the full path. + If a file needs to be opened, all subfolders are searched for a file of the corresponding name. + If a suitable file is found, it is imported. This process only depends on the file name of the file to + be read, not on its path. Correspondingly, an error message is generated if there are several files of + the same name in different subfolders, since ambiguities then arise. + + + A suitable project structure therefore looks as follows: The root circuit is located in a separate + folder. + All imported circuits must be in the same folder or subfolders. All circuits must have different names, + so it must not happen that there are circuits of the same name in different folders. + + + + + + + During the simulation every logic gate has a propagation delay. Every component found in the library + has the same propagation delay regardless of its complexity. + The AND gate thus has the same propagation delay as the multiplier. + The only exceptions are diodes, switches and splitters which are used to create data buses. + These components have no propagation delay at all. + + + If it's necessary to simulate a gate - e.g. the multiplier - with a longer propagation delay, a delay + gate must be inserted in the circuit right behind the output of the multiplier. + + + If a circuit is included in another parent circuit, the included circuit keeps its timing behaviour. + So if you include a complex circuit which has a large propagation delay because the input signals + has to pass three gates until it reaches the output, this behaviour is conserved while including this + circuit. + There are no additional delays introduced as a result of including a circuit. If not all outputs of a + circuit have + the same propagation delay, then this is also the case if it is included in a parent circuit. + In general, including a circuit into an other circuit does not modify its timing behaviour at all. An + included circuit behaves exactly the same way as if all components had been inserted at the same circuit + level. + + + + + + A circuit can be analyzed via the menu entry Analysis. A truth table is generated for purely + combinatorial circuits. This truth table can be edited as desired. + A new circuit can be generated from this truth table after editing. + + + In addition to purely combinatorial circuits, it is also possible to analyze or generate sequential + circuits. + Instead of a simple truth table a so-called state transition table is created. + Each flip-flop thereby appears on the input side and the output side of the state transition table. + In this table, on the right-hand side, you can find the next state, which will + occur after the next clock signal. This next state depends on the current state of the flip-flops as found + at the left-hand side of the table. + For an analysis to be possible, the flip-flops must be named. + + + The following naming convention applies: The following next state of a bit on the right side of the table + is indicated by a lowercase 'n+1'. The corresponding current state is indicated by an appended 'n'. + If there is a state variable 'A', 'An' indicates the current state and 'An+1' indicates the next state. + If, in the truth table on the left and right side, signals are present, which correspond to this pattern + it is assumed that the table is a state transition table, and a sequential circuit is generated instead of + a combinatorial circuit. + + + It should be noted that the circuit to be analyzed may contain only purely combinatorial elements in + addition to the built-in D and JK flip-flops. If a flip-flop is e.g. made from Nor gates, this + circuit is not recognized as a flip-flop and therefore it is not possible to analyse such a circuit. + + + + + + In the circuit generation menu in the truth table there are also functions to generate so-called + JEDEC files. This is a special file format that describes the fuse map of a PLD. + This JEDEC file can be written into a corresponding PLD using a special programmer. + At the moment, circuits of the type GAL16v8 and GAL22v10 or fuse map compatible + devices are supported. + + + + + The chips in the + + ATF150x + + family are simple CPLDs with up to 128 macrocells. They are available in a + PLCC package, which makes them suitable for laboratory exercises: If an IC is destroyed during + exercises, + it can simply be replaced. In addition, with the + + ATDH1150USB + + an easy to use, low-cost programmer is available. This programmer is able to program the + + ATF150x + + chips in system using a JTAG interface. + A suitable evaluation board + + (ATF15XX-DK3-U) + + is also available. + The software + + ATMISP + + , + which is available on the ATMEL/Microchip website, is required for programming the chips. + + + Unfortunately, the fuse map details are not publicly available so that no suitable fitter for this chip + can be integrated in Digital, as is possible with the GAL16v8 and GAL22v10 chips. + + + Therefore, the fitters fit150[x].exe provided by ATMEL must be used. These programs create a + JEDEC + file from a suitable TT2 file which can then be programmed on the chip. Digital + starts the fitter automatically every time a TT2 file is created. For this purpose, the path to + the + fit150[n].exe + fitters must be specified in the settings. + The created JEDEC file can then be opened and programmed directly with + + ATMISP + + . + + + For legal reasons the fitter fit1502.exe can not be distributed with Digital. However, it can be + found in the folder WinCupl\Fitters after installing + + WinCupl + + . + + WinCupl + + is available on the ATMEL/Microchip website. + On Linux systems, the fitters can also be executed by Digital if wine is installed. + + + + + A circuit can be exported to VHDL or Verilog. A file is generated which contains the complete + description + of the circuit. The generated VHDL code was tested with + Xilinx Vivado + and the open source VHDL simulator ghdl. + The Verilog code is tested with the Verilog simulator Icarus + Verilog. + + + If a circuit contains test cases, the test data is used to generate a HDL test bench. This can be used + to check the correct function of the circuit in a HDL simulation. + + + Additional files which are needed by special boards can be created. At present only the + BASYS3 + board and the Mimas boards + Mimas + and + Mimas V2 + + are supported. + A constraints file is created, which contains the assignment of the pins. The description of the pins + can + be found in the boards data sheet, and must be entered as a pin number for the inputs and outputs. + + + At a BASYS3 board, if the circuit clock frequency is low, a frequency divider is integrated into the HDL + code to divide the board clock accordingly. + If the clock frequency selected in the circuit exceeds 4.7MHz, the MMCM unit of the + Artix-7 is used for clock generation. + This ensures that the FPGA resources provided for the clock distribution are used. + This allows the included example processor to run at 20MHz, and if you can do without the + multiplier, 30HMz is also possible. + + + + If a circuit is to run on a BASYS3 board, a new project can be created in Vivado. + The generated VHDL file and the constraints file must be added to the project. + Once the project has been created, the bitstream can be generated and the Hardware-Manager can be used + to program a BASYS3 board. + + + In order to create the required constraints file in addition to the HDL file, the corresponding board + must be configured in the settings. In the field "Toolchain Configuration" the corresponding XML file + can be selected. + The available configurations can be found in the folder examples/hdl and have the file + extension .config. + If the configuration was successfully integrated, a further menu appears, which makes the board + specific functions accessible. + + + + + + Although Digital has some options that determine the appearance of a circuit when it is embedded in + another, in some cases it may be useful to use a very special shape for a subcircuit. An example is + the representation of the ALU in the processor included in the examples. This chapter explains how to + define such a special shape for a circuit. + + + Digital does not provide an editor for creating a special shape. Instead, a small detour is required + for creating circuit shapes: First, the circuit is opened, which is to be represented by a special shape. + Then an SVG template is created for this circuit. In this template, the circuit is represented by a + simple rectangle. It also contains all the pins of the circuit, represented by blue (inputs) and + red (outputs) circuits. To see which circle belongs to which pin, you can look at the ID of the + circle in the object properties. This ID has the form pin:[name] or pin+:[name]. + In the latter variant, the pin is provided with a label if reimported to digital. + If you do not want such a label, the + can be removed. + + + This SVG file can now be edited. The most suitable is the open source program + Inkscape + which is available for free. + The pins can be moved freely, but are moved to the next grid point during the reimport. + + + If existing SVG files are to be used, it is easiest to open the created template and paste the + existing graphic into the template via Copy&Paste. + + + If the file was saved, it can be imported with Digital. The file is read in and all necessary + information is extracted and stored in the circuit. For further use of the circuit, the SVG + file is no longer required. + + + A final remark: SVG is a very powerful and flexible file format. + It can be used to describe extremely complex graphics. The Digital importer is not able to import all + possible SVG files without errors. If a file can not be imported, or does not appear as expected, + some experimentation may be required before the desired result is achieved. + + + + + It happens that a subcircuit has been created, and this is to be used in different variants. + For example, you can imagine a special counter that is needed for different bit widths. + If one would create a partial circuit for 4, 5 and 6 bits each, the maintenance of the circuit + would be difficult in the future, since one must always work on several subcircuits, which are + identical except for one parameter, the bit width. + + + To prevent this, a generic partial circuit can be created which can be parameterized. + For this purpose, the checkbox "Circuit is generic" must be set in the circuit setting of the circuit. + Then the parameter dialog of each component of the circuit contains the additional field "generic + parameterization". In this field program code can be entered, which can change the parameters of the + component. Each parameter has a name and can be modified as an attribute of the field this. + The names of the parameters can be found in the help dialog of the component. + If you want to change the bit width of an adder, the line this.Bits=int(1); can be used. + Constants - here the one - are always of type long, but the bit width is an int. + Therefore the type conversion to an int is necessary. + + + In this way, however, it is not yet possible to create a circuit that can be parameterized. + It is still necessary to access parameters that are set when the circuit is used. + This is done via the field "args". If you want to set the bit width from outside, you can write: + this.Bits=int(args.bitWidth);. The name of the argument - here bitWidth is arbitrary. + If this partial circuit is used, this argument must be set. + + + If the circuit is used and the parameter dialog of the embedded circuit is opened, it also has a + field "generic parameterization". Here the bit width to be used can be set with the instruction + bitWidth:=5;. + + + In this way, no wires or components can be removed or added. Nevertheless, many circuits can be + realized with a trick. This is achieved by replacing one circuit with another, depending on the + arguments. For this purpose the function setCircuit([Name]) is available. + If it is called in the definition part of a subcircuit, the circuit to be inserted can be replaced + by another circuit. This allows the recursive definition of a circuit. As in other programming + languages, a suitable termination condition must be ensured. + + + The examples/generic folder contains an example of a Gray code counter whose bit width can + be configured. Here a Gray code counter is constructed by recursively adding further bits to an + initial circuit until the required number of bits of the counter is reached. + + + + + If students are to complete exercises with Digital, it can be helpful if the circuits submitted by the + students can be checked in an automatic process. To perform this check, Digital can be started + from the command line. The call is done as follows: + + + + java -cp Digital.jar de.neemann.digital.testing.CommandLineTester [file to test] [[optional file with + test cases]] + + + + If only the file to be tested is specified, the test cases in that file are executed. In this way, the + test cases created by the students themselves can be executed. + + + If a second file name is specified, the test cases are taken from the second file and the first circuit + is checked with these test cases. The second file will therefore usually contain the sample solution + whose test cases are complete and correct. The circuit contained in the second file is ignored. + Only the test cases are taken from it. + + + In order to test a submitted circuit against a sample solution, the signal names of the inputs and + outputs in both circuits must match. + + + + + How to move a wire? + Select one of the end points with the rectangular selection. Then move this point using the mouse. + You can also select a wire with CTRL + mouse button. + + + + How to delete a wire? + Select one of the end points and press DEL or click on the trashcan. + You can also select a wire with CTRL + mouse button. + + + + How to move a component including all the connected wires? + Select the component with the rectangular selection. The selection must include the entire + component. + Then move the component including the wires using the mouse. + + + + There is a component not connected to a wire, even though the pins are on the wire. + A pin is only connected to a wire if the wire has an endpoint at the pin. + + + If the names of the pins in a circuit are long, the names are no longer readable when + the circuit is embedded. What can I do? + + The width of the block can be increased using the menu item + EditEdit circuit attributes + + . + + + + The pins in an embedded circuit have an non-optimal order. How can this be changed? + The sequence can be changed using the menu entry + EditOrder inputs + + or + EditOrder outputs + + . + + + + + When the simulation is started, a wire becomes gray. What does that mean? + The colors light green and dark green are used to represent high and low state. + Gray means the wire is in high Z state. + + + + I have a truth table. How to calculate the minimized boolean equations? + In the menu Analysis select the entry Synthesise. Then enter the truth table. + At the bottom of the window you can find the matching boolean equation. If you enter more than one + dependent variable, a new window opens in which all boolean equations are shown. + + + + I have entered a truth table, but there is more than one boolean equation shown. + Which of them is the correct one? + + Minimizing a boolean equation can result in many equations, describing the same function. + Digital shows all of them and they all create the same truth table. + There may be differences depending on the "don't cares" in the truth table. + + + + I have a truth table. How to create a circuit representing the truth table? + In the menu Analysis select the entry Synthesise. Then enter the truth table. + You can edit the table using the New or Add Columns menus. + In the menu Create you can create a circuit using the Circuit item. + + + + How to edit a signal's name in the truth table? + Right click on the name in the table header to edit the name. + + + I have a boolean equation. How to create a circuit? + In the menu Analysis select the entry Expression. Then enter the expression. + + + + How to create a truth table from a boolean equation? + In the menu Analysis select the entry Expression. Then enter the expression. + Then create a circuit and in the menu Analysis use the entry Analysis to create the truth + table. + + + + How to create a JEDEC file from a given circuit? + In the menu Analysis select the entry Analysis. Then in the menu Create in the + new + window choose the correct device in the sub menu Device. + + + + When creating a JEDEC file: How to assign a pin number to a certain signal? + At the corresponding inputs and outputs you can enter a pin number in the settings dialog of the + pin. + + + + I have created a JEDEC file. How to program it to a GAL16v8 or GAL22v10? + + To program such a chip a special programmer hardware is necessary. + + + I have created a circuit that I want to use in many other circuits. + How can I do this without copying the file over and over again into the appropriate folders? + + The circuit can be saved in the "lib" folder. Then it is available in all other circuits. + + + + + + Starts or stops the simulation. + Opens the measurement table dialog. + Run to Break + Execute test cases + A single clock step (Works only in a running simulation and only if there is a single + clock component). + + Execute a single gate step. + Execute all single gate steps until the circuit has stabilized or, + if a break component is present, until the break. + + Analysis of the circuit + Select all. + Cuts the selected components to the clipboard. + Copys the selected components to the clipboard. + Inserts the components from the clipboard. + Duplicate the current selection without modifying the clipboard. + While inserting this rotates the components. + Inserts the last inserted component again. + Inserts a new tunnel. + New circuit. + Open circuit. + Save the circuit. + Undo last modification. + Redo the last undone modification. + Programs a diode or a FG-FET. + While drawing a wire switches to the diagonal mode. + While drawing a line flips the orientation. + Splits a single wire into two wires. + Abort the current action. + Removes the selected components. + Removes the selected components. + Increases the number of inputs at the component the mouse points to. If it is used with + constants, the value is increased. + + Decreases the number of inputs at the component the mouse points to. If it is used with + constants, the value is decreased. + + Zoom In + Zoom Out + Fit to size + Show or hide the components tree view + + + \ No newline at end of file