diff --git a/src/test/java/de/neemann/digital/hdl/verilog2/VerilogGeneratorTest.java b/src/test/java/de/neemann/digital/hdl/verilog2/VerilogGeneratorTest.java
index a6b9e0ed0..27633d54a 100644
--- a/src/test/java/de/neemann/digital/hdl/verilog2/VerilogGeneratorTest.java
+++ b/src/test/java/de/neemann/digital/hdl/verilog2/VerilogGeneratorTest.java
@@ -136,15 +136,39 @@ public class VerilogGeneratorTest extends TestCase {
+ " assign s0 = inst[8];\n"
+ " assign \\9SD [7:0] = inst[7:0];\n"
+ " assign \\9SD [8] = s0;\n"
- + " assign \\9SD [9] = s0;\n"
- + " assign \\9SD [10] = s0;\n"
- + " assign \\9SD [11] = s0;\n"
- + " assign \\9SD [12] = s0;\n"
- + " assign \\9SD [13] = s0;\n"
- + " assign \\9SD [14] = s0;\n"
- + " assign \\9SD [15] = s0;\n"
- + "endmodule\n", out.toString());
+ + " assign \\9SD [9] = s0;\n"
+ + " assign \\9SD [10] = s0;\n"
+ + " assign \\9SD [11] = s0;\n"
+ + " assign \\9SD [12] = s0;\n"
+ + " assign \\9SD [13] = s0;\n"
+ + " assign \\9SD [14] = s0;\n"
+ + " assign \\9SD [15] = s0;\n"
+ + "endmodule\n", out.toString());
}
+ public void testSkip() throws Exception {
+ ToBreakRunner br = new ToBreakRunner("dig/hdl_skip/skipOuter.dig");
+ CodePrinterStr out = new CodePrinterStr();
+ new VerilogGenerator(br.getLibrary(), out).export(br.getCircuit());
+
+ assertEquals("/*\n" +
+ " * Generated by Digital. Don't modify this file!\n" +
+ " * Any changes will be lost if this file is regenerated.\n" +
+ " */\n" +
+ "\n" +
+ "module skipOuter (\n" +
+ " input A,\n" +
+ " input B,\n" +
+ " output Y\n" +
+ ");\n" +
+ " wire s0;\n" +
+ " skipInner skipInner_i0 (\n" +
+ " .i( B ),\n" +
+ " .o( s0 )\n" +
+ " );\n" +
+ " assign Y = (A & s0);\n" +
+ "endmodule\n", out.toString());
+ }
+
}
\ No newline at end of file
diff --git a/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLGeneratorTest.java b/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLGeneratorTest.java
index e26158484..cebf74a80 100644
--- a/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLGeneratorTest.java
+++ b/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLGeneratorTest.java
@@ -169,8 +169,37 @@ public class VHDLGeneratorTest extends TestCase {
" n9SD(13) <= s0;\n" +
" n9SD(14) <= s0;\n" +
" n9SD(15) <= s0;\n" +
- "end Behavioral;\n",out.toString());
+ "end Behavioral;\n", out.toString());
}
+ public void testSkip() throws Exception {
+ ToBreakRunner br = new ToBreakRunner("dig/hdl_skip/skipOuter.dig");
+ CodePrinterStr out = new CodePrinterStr();
+ new VHDLGenerator(br.getLibrary(), out).export(br.getCircuit());
+
+ assertEquals("-- generated by Digital. Don't modify this file!\n" +
+ "-- Any changes will be lost if this file is regenerated.\n" +
+ "\n" +
+ "LIBRARY ieee;\n" +
+ "USE ieee.std_logic_1164.all;\n" +
+ "USE ieee.numeric_std.all;\n" +
+ "\n" +
+ "entity main is\n" +
+ " port (\n" +
+ " A: in std_logic;\n" +
+ " B: in std_logic;\n" +
+ " Y: out std_logic);\n" +
+ "end main;\n" +
+ "\n" +
+ "architecture Behavioral of main is\n" +
+ " signal s0: std_logic;\n" +
+ "begin\n" +
+ " gate0: entity work.skipInner\n" +
+ " port map (\n" +
+ " i => B,\n" +
+ " o => s0);\n" +
+ " Y <= (A AND s0);\n" +
+ "end Behavioral;\n", out.toString());
+ }
}
\ No newline at end of file
diff --git a/src/test/resources/dig/hdl_skip/skipInner.dig b/src/test/resources/dig/hdl_skip/skipInner.dig
new file mode 100644
index 000000000..310f63d8b
--- /dev/null
+++ b/src/test/resources/dig/hdl_skip/skipInner.dig
@@ -0,0 +1,48 @@
+
+
+ 1
+
+
+ skipHDL
+ true
+
+
+
+
+ Not
+
+
+
+
+ Out
+
+
+ Label
+ o
+
+
+
+
+
+ In
+
+
+ Label
+ i
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/src/test/resources/dig/hdl_skip/skipOuter.dig b/src/test/resources/dig/hdl_skip/skipOuter.dig
new file mode 100644
index 000000000..8579924a7
--- /dev/null
+++ b/src/test/resources/dig/hdl_skip/skipOuter.dig
@@ -0,0 +1,66 @@
+
+
+ 1
+
+
+
+ Out
+
+
+ Label
+ Y
+
+
+
+
+
+ In
+
+
+ Label
+ A
+
+
+
+
+
+ And
+
+
+
+
+ skipInner.dig
+
+
+
+
+ In
+
+
+ Label
+ B
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file