diff --git a/src/main/resources/vhdl2/DIG_BlockRAMDualPortMasked.tem b/src/main/resources/vhdl2/DIG_BlockRAMDualPortMasked.tem
new file mode 100644
index 000000000..47a8a113f
--- /dev/null
+++ b/src/main/resources/vhdl2/DIG_BlockRAMDualPortMasked.tem
@@ -0,0 +1,49 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+<?
+
+   entityName := "BlockRam_D"+elem.Bits+"A"+elem.AddrBits;
+   maskBits   := elem.Bits / 8;
+
+?>
+entity <?=entityName?> is
+  port (
+    D: out std_logic_vector (<?=elem.Bits-1?> downto 0);
+    A: in std_logic_vector (<?=elem.AddrBits-1?> downto 0);
+    Din: in std_logic_vector (<?=elem.Bits-1?> downto 0);
+    str: in <?
+      if (maskBits=1) {
+        print("std_logic;");
+      } else {
+        print("std_logic_vector ("+(maskBits-1)+" downto 0);");
+      } ?>
+    C: in std_logic );
+end <?=entityName?>;
+
+architecture Behavioral of <?=entityName?> is
+    type memoryType is array(0 to <?=(1<<elem.AddrBits)-1?>) of std_logic_vector(<?=elem.Bits-1?> downto 0);
+    signal memory : memoryType;
+    signal rData : std_logic_vector (<?=elem.Bits-1?> downto 0) := (others => '0');
+begin
+  process ( C )
+  begin
+    if rising_edge(C) then
+      rData <= memory(to_integer(unsigned(A)));
+      <? if (maskBits=1) { ?>
+      if str='1' then
+        memory(to_integer(unsigned(A))) <= Din;
+      end if;
+      <? } else {
+          for (i:=0;i<maskBits;i++) {
+      ?>
+      if str(<?=i?>)='1' then
+        memory(to_integer(unsigned(A)))(<?=i*8+7?> downto <?=i*8?>) <= Din(<?=i*8+7?> downto <?=i*8?>);
+      end if;
+      <?
+          }
+        } ?>
+    end if;
+  end process;
+  D <= rData;
+end Behavioral;
diff --git a/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLSimulatorTest.java b/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLSimulatorTest.java
index b19d579a3..50f24c1d1 100644
--- a/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLSimulatorTest.java
+++ b/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLSimulatorTest.java
@@ -47,7 +47,7 @@ public class VHDLSimulatorTest extends TestCase {
         File examples = new File(Resources.getRoot(), "/dig/test/vhdl");
         try {
             int tested = new FileScanner(this::checkVHDLExport).noOutput().scan(examples);
-            assertEquals(33, tested);
+            assertEquals(36, tested);
             assertEquals(tested+2, testBenches);
         } catch (FileScanner.SkipAllException e) {
             // if ghdl is not installed its also ok
diff --git a/src/test/resources/dig/test/RAM/maskedRAM.dig b/src/test/resources/dig/test/vhdl/ram/maskedRAM.dig
similarity index 98%
rename from src/test/resources/dig/test/RAM/maskedRAM.dig
rename to src/test/resources/dig/test/vhdl/ram/maskedRAM.dig
index 9300faf5a..927b4ad7b 100644
--- a/src/test/resources/dig/test/RAM/maskedRAM.dig
+++ b/src/test/resources/dig/test/vhdl/ram/maskedRAM.dig
@@ -78,6 +78,7 @@
             <dataString>C A Din         mask   D
 
 # no write at all, mask is zero
+C 0 0           0b1111 x
 C 0 0xffffffff  0b0000 x
 C 0 0           0b0000 0
 
@@ -97,6 +98,7 @@ C 0 0           0b0000 0xffffffff
 
 # write 16 bit words
 
+C 1 0           0b1111 x
 C 1 0xffff      0b0011 x
 C 1 0           0b0000  0xffff
 
@@ -108,6 +110,7 @@ C 1 0           0b0000 0xffaaaaff
 
 # write 32 bit words
 
+C 2 0           0b1111 x
 C 2 0xffffffff  0b1111 x
 C 2 0           0b0000  0xffffffff
 
diff --git a/src/test/resources/dig/test/RAM/maskedRAM64.dig b/src/test/resources/dig/test/vhdl/ram/maskedRAM64.dig
similarity index 98%
rename from src/test/resources/dig/test/RAM/maskedRAM64.dig
rename to src/test/resources/dig/test/vhdl/ram/maskedRAM64.dig
index 78ab16be8..2a671f267 100644
--- a/src/test/resources/dig/test/RAM/maskedRAM64.dig
+++ b/src/test/resources/dig/test/vhdl/ram/maskedRAM64.dig
@@ -78,6 +78,7 @@
             <dataString>C A Din                 mask   D
 
 # no write at all, mask is zero
+C 0 0                   0b11111111 x
 C 0 0xffffffffffffffff  0b00000000 x
 C 0 0                   0b00000000 0
 
@@ -109,6 +110,8 @@ C 0 0                   0b00000000 0xffffffffffffffff
 
 # write 32 bit words
 
+C 1 0                   0b11111111 x
+
 C 1 0xffffffff          0b00001111 x
 C 1 0                   0b00000000 0xffffffff
 
diff --git a/src/test/resources/dig/test/RAM/maskedRAM8.dig b/src/test/resources/dig/test/vhdl/ram/maskedRAM8.dig
similarity index 98%
rename from src/test/resources/dig/test/RAM/maskedRAM8.dig
rename to src/test/resources/dig/test/vhdl/ram/maskedRAM8.dig
index 21bd7589c..0d4106db4 100644
--- a/src/test/resources/dig/test/RAM/maskedRAM8.dig
+++ b/src/test/resources/dig/test/vhdl/ram/maskedRAM8.dig
@@ -74,6 +74,7 @@
             <dataString>C A Din   mask   D
 
 # no write at all, mask is zero
+C 0 0     1      x
 C 0 0xff  0      x
 C 0 0     0      0
 
@@ -82,6 +83,7 @@ C 0 0     0      0
 C 0 0xff  1      x
 C 1 0xf0  1      x
 
+C 2 0     1      x
 C 2 0     0      0
 0 0 0     0      0
 0 1 0     0      0