From c114f7954b7961be826818419caccff5cf080cf3 Mon Sep 17 00:00:00 2001
From: hneemann <helmut.neemann@arcor.de>
Date: Fri, 1 Mar 2019 19:19:20 +0100
Subject: [PATCH] added Verilog LookUpTable template

---
 src/main/resources/verilog/DIG_LookUpTable.v  | 36 +++++++++++++++++++
 .../hdl/verilog2/VerilogSimulatorTest.java    | 19 +++++++---
 2 files changed, 50 insertions(+), 5 deletions(-)
 create mode 100644 src/main/resources/verilog/DIG_LookUpTable.v

diff --git a/src/main/resources/verilog/DIG_LookUpTable.v b/src/main/resources/verilog/DIG_LookUpTable.v
new file mode 100644
index 000000000..64757066a
--- /dev/null
+++ b/src/main/resources/verilog/DIG_LookUpTable.v
@@ -0,0 +1,36 @@
+<?
+    if (elem.Label="")
+        panic("err_lutNeedsALabelToBeExported");
+
+    lutSize := 1 << elem.Inputs;
+    moduleName = format("LUT_%s", elem.Label);
+    dBitRange := format("[%d:0]", elem.Bits - 1);
+
+?>module <?= moduleName ?> (
+<?- for (i:=0;i<elem.Inputs;i++) {?>
+    input \<?=i?> ,
+<?- }?>
+    output reg <?= dBitRange ?> out
+);
+    reg <?= dBitRange ?> my_lut [0:<?= (lutSize - 1) ?>];
+    wire [<?=elem.Inputs-1?>:0] temp;
+    assign temp = {<?
+        for (i:=elem.Inputs-1;i>=0;i--) {
+            if (i<elem.Inputs-1) {
+                print(" , ");
+            }
+            print("\\"+i);
+        }
+    ?> };
+
+    always @ (*) begin
+       out = my_lut[temp];
+    end
+
+    initial begin<?
+
+    for (i := 0; i < lutSize; i++) { ?>
+        my_lut[<?= i ?>] = <?= format("%d'h%x", elem.Bits, elem.Data[i]) ?>;<?
+    } ?>
+    end
+endmodule
diff --git a/src/test/java/de/neemann/digital/hdl/verilog2/VerilogSimulatorTest.java b/src/test/java/de/neemann/digital/hdl/verilog2/VerilogSimulatorTest.java
index ceec7b8ce..b728f375b 100644
--- a/src/test/java/de/neemann/digital/hdl/verilog2/VerilogSimulatorTest.java
+++ b/src/test/java/de/neemann/digital/hdl/verilog2/VerilogSimulatorTest.java
@@ -19,20 +19,19 @@ import de.neemann.digital.integration.Resources;
 import de.neemann.digital.integration.TestExamples;
 import de.neemann.digital.integration.ToBreakRunner;
 import junit.framework.TestCase;
+import org.slf4j.Logger;
+import org.slf4j.LoggerFactory;
 
 import java.io.File;
 import java.io.IOException;
 import java.nio.file.Files;
+import java.nio.file.Path;
+import java.nio.file.Paths;
 import java.text.DateFormat;
 import java.text.SimpleDateFormat;
 import java.util.ArrayList;
 import java.util.Date;
 
-import java.nio.file.Path;
-import java.nio.file.Paths;
-import org.slf4j.Logger;
-import org.slf4j.LoggerFactory;
-
 public class VerilogSimulatorTest extends TestCase {
     private static final Logger LOGGER = LoggerFactory.getLogger(VerilogSimulatorTest.class);
     private static String IVERILOG = System.getProperty("iverilog", "");
@@ -41,6 +40,16 @@ public class VerilogSimulatorTest extends TestCase {
     private static final boolean foundIVerilog = findIVerilogDir();
     private int testBenches;
 
+    /*
+    public void testDebug() throws Exception {
+        File file = new File(Resources.getRoot(), "dig/test/vhdl/lut.dig");
+
+        ToBreakRunner br = new ToBreakRunner(file);
+        System.out.println(new VerilogGenerator(br.getLibrary(), new CodePrinterStr(true)).export(br.getCircuit()));
+
+        checkVerilogExport(file);
+    }*/
+
     public void testInSimulator() throws Exception {
         File examples = new File(Resources.getRoot(), "/dig/test/vhdl");
         try {