diff --git a/src/main/java/de/neemann/digital/hdl/hgs/Parser.java b/src/main/java/de/neemann/digital/hdl/hgs/Parser.java
index 24f110023..da7e7fc9c 100644
--- a/src/main/java/de/neemann/digital/hdl/hgs/Parser.java
+++ b/src/main/java/de/neemann/digital/hdl/hgs/Parser.java
@@ -173,8 +173,11 @@ public class Parser {
                         throw newUnexpectedToken(refToken);
                 }
             case CODEEND:
-                final String str = tok.readText();
-                return c -> c.print(str);
+                String str = tok.readText();
+                if (nextIs(SUB))
+                    str = Value.trimRight(str);
+                final String strc = str;
+                return c -> c.print(strc);
             case SUB:
                 expect(CODEEND);
                 final String strt = Value.trimLeft(tok.readText());
diff --git a/src/main/java/de/neemann/digital/hdl/vhdl/lib/VHDLTemplate.java b/src/main/java/de/neemann/digital/hdl/vhdl/lib/VHDLTemplate.java
index 3391a89eb..08fbf20a9 100644
--- a/src/main/java/de/neemann/digital/hdl/vhdl/lib/VHDLTemplate.java
+++ b/src/main/java/de/neemann/digital/hdl/vhdl/lib/VHDLTemplate.java
@@ -99,7 +99,7 @@ public class VHDLTemplate implements VHDLEntity {
         try {
             String port = getEntity(node).getPortDecl();
             if (port != null) {
-                out.dec().print(port).inc();
+                out.dec().print(Value.trimRight(port)).println().inc();
             } else {
                 out.println("port (").inc();
                 Separator semic = new Separator(";\n");
diff --git a/src/main/resources/vhdl/DIG_Comparator.tem b/src/main/resources/vhdl/DIG_Comparator.tem
index f1c82b90b..0f8a17145 100644
--- a/src/main/resources/vhdl/DIG_Comparator.tem
+++ b/src/main/resources/vhdl/DIG_Comparator.tem
@@ -1,16 +1,16 @@
 LIBRARY ieee;
 USE ieee.std_logic_1164.all;
-<?
+<?-
   if (elem.Signed) {
       entityName:="COMP_GATE_SIGNED";
-      print("USE ieee.numeric_std.all;");
+      print("\nUSE ieee.numeric_std.all;");
   } else
       entityName:="COMP_GATE_UNSIGNED";
 
 
 ?>
 entity <?=entityName?> is
-  <? vhdl.beginGenericPort();?>
+  <?- vhdl.beginGenericPort();?>
   generic ( Bits : integer );<? vhdl.registerGeneric("Bits");?>
   port (
     PORT_gr: out std_logic;
@@ -18,26 +18,26 @@ entity <?=entityName?> is
     PORT_le: out std_logic;
     PORT_a: in <?= vhdl.genericType(elem.Bits)?>;
     PORT_b: in <?= vhdl.genericType(elem.Bits)?> );
-<? vhdl.endGenericPort();?>
+  <?- vhdl.endGenericPort();?>
 end <?=entityName?>;
 
 architecture <?=entityName?>_arch of <?=entityName?> is
 begin
   process(PORT_a,PORT_b)
   begin
-    <? if (elem.Signed) { ?>
+    <?- if (elem.Signed) { ?>
     if (signed(PORT_a) > signed(PORT_b)) then
-    <? } else { ?>
+    <?- } else { ?>
     if (PORT_a > PORT_b ) then
-    <? } ?>
+    <?- } ?>
       PORT_le <= '0';
       PORT_eq <= '0';
       PORT_gr <= '1';
-    <? if (elem.Signed) { ?>
+    <?- if (elem.Signed) { ?>
     elsif (signed(PORT_a) < signed(PORT_b)) then
-    <? } else { ?>
+    <?- } else { ?>
     elsif (PORT_a < PORT_b) then
-    <? } ?>
+    <?- } ?>
       PORT_le <= '1';
       PORT_eq <= '0';
       PORT_gr <= '0';
diff --git a/src/test/java/de/neemann/digital/hdl/hgs/ParserTest.java b/src/test/java/de/neemann/digital/hdl/hgs/ParserTest.java
index e69880b24..856ed8099 100644
--- a/src/test/java/de/neemann/digital/hdl/hgs/ParserTest.java
+++ b/src/test/java/de/neemann/digital/hdl/hgs/ParserTest.java
@@ -500,6 +500,13 @@ public class ParserTest extends TestCase {
         assertEquals("5 ", exec(" <?-=5?> ").toString());
         assertEquals("5", exec("\n\n  <?-=5;-?>\n\n").toString());
         assertEquals("\n 5 \n", exec("\n <?=5?> \n").toString());
+        assertEquals("5", exec("\n\n  <?- print(5);-?>\n\n").toString());
+
+        assertEquals(" 5", exec("<??> <?=5;-?> ").toString());
+        assertEquals("5 ", exec("<??> <?-=5?> ").toString());
+        assertEquals("5", exec("<??>\n\n  <?-=5;-?>\n\n").toString());
+        assertEquals("\n 5 \n", exec("<??>\n <?=5?> \n").toString());
+        assertEquals("5", exec("<??>\n\n  <?- print(5);-?>\n\n").toString());
     }
 
     // checks the available VHDL templates
diff --git a/src/test/java/de/neemann/digital/hdl/vhdl/lib/VHDLFileTest.java b/src/test/java/de/neemann/digital/hdl/vhdl/lib/VHDLFileTest.java
index 6dc4c7e82..55d2f7667 100644
--- a/src/test/java/de/neemann/digital/hdl/vhdl/lib/VHDLFileTest.java
+++ b/src/test/java/de/neemann/digital/hdl/vhdl/lib/VHDLFileTest.java
@@ -39,14 +39,14 @@ public class VHDLFileTest extends TestCase {
                 "           PORT_C  : in std_logic;\n" +
                 "           PORT_Q  : out std_logic;\n" +
                 "           PORT_notQ : out std_logic );\n" +
-                "    end component;\n" +
+                "  end component;\n" +
                 "  component DIG_D_FF_BUS\n" +
                 "    generic ( Bits: integer ); \n" +
                 "    port ( PORT_D  : in std_logic_vector ((Bits-1) downto 0);\n" +
                 "           PORT_C  : in std_logic;\n" +
                 "           PORT_Q  : out std_logic_vector ((Bits-1) downto 0);\n" +
                 "           PORT_notQ : out std_logic_vector ((Bits-1) downto 0) );\n" +
-                "    end component;\n" +
+                "  end component;\n" +
                 "  signal S0: std_logic;\n" +
                 "  signal S1: std_logic;\n" +
                 "  signal S2: std_logic_vector (2 downto 0);\n" +