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inlining of many-to-one splitter

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hneemann 2018-03-29 12:10:00 +02:00
parent 6cc350e488
commit c8090510ff
3 changed files with 50 additions and 19 deletions
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1
src/main/java/de/neemann/digital/hdl/model2/HDLCircuit.java
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@ -521,6 +521,7 @@ public class HDLCircuit implements Iterable<HDLNode>, HDLModel.BitProvider, Prin
public HDLCircuit applyDefaultOptimizations() throws HDLException {
apply(new ReplaceOneToMany());
apply(new MergeAssignements());
apply(new InlineManyToOne());
apply(new RemoveConstantSignals());
apply(new MergeConstants()); // under certain circumstances there are still constants
apply(new NameConstantSignals());

36
src/main/java/de/neemann/digital/hdl/model2/optimizations/InlineManyToOne.java Normal file
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@ -0,0 +1,36 @@
/*
* Copyright (c) 2018 Helmut Neemann.
* Use of this source code is governed by the GPL v3 license
* that can be found in the LICENSE file.
*/
package de.neemann.digital.hdl.model2.optimizations;
import de.neemann.digital.hdl.model2.*;
import java.util.Iterator;
/**
* Inlines the inputs of the HDLNodeSplitterManyToOne.
*/
public class InlineManyToOne implements Optimization {
@Override
public void optimize(HDLCircuit circuit) {
Iterator<HDLNode> it = circuit.iterator();
while (it.hasNext()) {
HDLNode node = it.next();
if (node instanceof HDLNodeAssignment) {
HDLNodeAssignment assign = (HDLNodeAssignment) node;
final HDLNet net = assign.getTargetNet();
if (net.getInputs().size() == 1) {
HDLNode receiver = net.getInputs().get(0).getParent();
if (receiver instanceof HDLNodeSplitterManyToOne) {
HDLNodeSplitterManyToOne mto = (HDLNodeSplitterManyToOne) receiver;
mto.replaceNetByExpression(net, assign.getExpression());
it.remove();
circuit.removeNet(net);
}
}
}
}
}
}

32
src/test/java/de/neemann/digital/hdl/vhdl2/VHDLGeneratorTest.java
View File

@ -104,13 +104,9 @@ public class VHDLGeneratorTest extends TestCase {
"end main;\n" +
"\n" +
"architecture Behavioral of main is\n" +
" signal s0: std_logic_vector(1 downto 0);\n" +
" signal s1: std_logic_vector(1 downto 0);\n" +
"begin\n" +
" s0 <= (A(1 downto 0) AND B(1 downto 0));\n" +
" s1 <= (A(3 downto 2) OR B(3 downto 2));\n" +
" S(1 downto 0) <= s0;\n" +
" S(3 downto 2) <= s1;\n" +
" S(1 downto 0) <= (A(1 downto 0) AND B(1 downto 0));\n" +
" S(3 downto 2) <= (A(3 downto 2) OR B(3 downto 2));\n" +
"end Behavioral;\n",out.toString());
}
@ -163,20 +159,18 @@ public class VHDLGeneratorTest extends TestCase {
"end main;\n" +
"\n" +
"architecture Behavioral of main is\n" +
" signal s0: std_logic_vector(7 downto 0);\n" +
" signal s1: std_logic;\n" +
" signal s0: std_logic;\n" +
"begin\n" +
" s0 <= inst(7 downto 0);\n" +
" s1 <= inst(8);\n" +
" n9SD(7 downto 0) <= s0;\n" +
" n9SD(8) <= s1;\n" +
" n9SD(9) <= s1;\n" +
" n9SD(10) <= s1;\n" +
" n9SD(11) <= s1;\n" +
" n9SD(12) <= s1;\n" +
" n9SD(13) <= s1;\n" +
" n9SD(14) <= s1;\n" +
" n9SD(15) <= s1;\n" +
" s0 <= inst(8);\n" +
" n9SD(7 downto 0) <= inst(7 downto 0);\n" +
" n9SD(8) <= s0;\n" +
" n9SD(9) <= s0;\n" +
" n9SD(10) <= s0;\n" +
" n9SD(11) <= s0;\n" +
" n9SD(12) <= s0;\n" +
" n9SD(13) <= s0;\n" +
" n9SD(14) <= s0;\n" +
" n9SD(15) <= s0;\n" +
"end Behavioral;\n",out.toString());
}