mirror of
https://github.com/hneemann/Digital.git
synced 2025-09-19 09:54:49 -04:00
added vhdl templates for async flip flops
This commit is contained in:
hneemann
parent
7827f6911c
commit
cdb2eef854
@ -63,6 +63,7 @@ public class Port {
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.replace('.', '_')
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.replace('-', '_')
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.replace("\u00AC", "not")
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.replace("~", "not")
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.replace("=", "eq")
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.replace("<", "le")
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.replace(">", "gr");
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@ -7,7 +7,7 @@ import java.io.IOException;
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/**
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* Used to create separators
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*/
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public final class Separator {
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public class Separator {
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private final String sep;
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private boolean first = true;
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@ -30,6 +30,13 @@ public final class Separator {
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if (first)
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first = false;
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else
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out.print(sep);
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out.print(getSeperator());
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}
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/**
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* @return the separator
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*/
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public String getSeperator() {
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return sep;
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}
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}
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@ -67,7 +67,7 @@ public class VHDLTestBenchCreator {
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else
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testName = filename + "_tb";
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testName=Port.getHDLName(testName);
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testName = Port.getHDLName(testName);
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File f = new File(file.getParentFile(), testName + ".vhdl");
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testFileWritten.add(f);
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@ -163,11 +163,17 @@ public class VHDLTestBenchCreator {
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private final CodePrinter out;
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private final ArrayList<Port> dataOrder;
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private final Separator lineSep;
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private int line = 0;
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private LineListenerVHDL(CodePrinter out, ArrayList<Port> dataOrder) {
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this.out = out;
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this.dataOrder = dataOrder;
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lineSep = new Separator(",\n");
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lineSep = new Separator("") {
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@Override
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public String getSeperator() {
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return ", -- i=" + (line++) + "\n";
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}
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};
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}
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@Override
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31
src/main/resources/vhdl/DIG_D_FF_AS.vhdl
Normal file
31
src/main/resources/vhdl/DIG_D_FF_AS.vhdl
Normal file
@ -0,0 +1,31 @@
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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entity DIG_D_FF_AS is
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port (
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PORT_Q: out {{data}};
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PORT_notQ: out {{data}};
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PORT_Set: in std_logic;
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PORT_D: in {{data}};
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PORT_C: in std_logic;
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PORT_Clr: in std_logic );
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end DIG_D_FF_AS;
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architecture DIG_D_FF_AS_arch of DIG_D_FF_AS is
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signal state : {{data}} := {{zero}};
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begin
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process ( PORT_Set, PORT_Clr, PORT_C )
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begin
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if (PORT_Set='1') then
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state <= NOT({{zero}});
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elsif (PORT_Clr='1') then
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state <= {{zero}};
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elsif rising_edge(PORT_C) then
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state <= PORT_D;
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end if;
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end process;
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PORT_Q <= state;
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PORT_notQ <= NOT( state );
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end DIG_D_FF_AS_arch;
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@ -17,9 +17,7 @@ begin
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process (PORT_C)
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begin
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if rising_edge(PORT_C) then
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if (PORT_J='0' and PORT_K='0') then
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temp <= temp;
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elsif (PORT_J='0' and PORT_K='1') then
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if (PORT_J='0' and PORT_K='1') then
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temp <= '0';
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elsif (PORT_J='1' and PORT_K='0') then
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temp <= '1';
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38
src/main/resources/vhdl/DIG_JK_FF_AS.vhdl
Normal file
38
src/main/resources/vhdl/DIG_JK_FF_AS.vhdl
Normal file
@ -0,0 +1,38 @@
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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entity DIG_JK_FF_AS is
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generic (Default : std_logic);
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port (
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PORT_Q: out std_logic;
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PORT_notQ: out std_logic;
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PORT_Set: in std_logic;
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PORT_J: in std_logic;
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PORT_C: in std_logic;
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PORT_K: in std_logic;
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PORT_Clr: in std_logic );
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end DIG_JK_FF_AS;
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architecture DIG_JK_FF_AS_arch of DIG_JK_FF_AS is
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signal state: std_logic := Default;
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begin
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process (PORT_C, PORT_Clr, PORT_Set)
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begin
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if (PORT_Set='1') then
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state <= '1';
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elsif (PORT_Clr='1') then
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state <= '0';
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elsif rising_edge(PORT_C) then
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if (PORT_J='0' and PORT_K='1') then
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state <= '0';
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elsif (PORT_J='1' and PORT_K='0') then
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state <= '1';
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elsif (PORT_J='1' and PORT_K='1') then
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state <= not (state);
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end if;
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end if;
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end process;
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PORT_Q <= state;
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PORT_notQ <= NOT( state );
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end DIG_JK_FF_AS_arch;
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@ -12,9 +12,9 @@ end DIG_Register;
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architecture DIG_Register_arch of DIG_Register is
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signal state : {{data}} := {{zero}};
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begin
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PORT_Q <= state;
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PORT_Q <= state;
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process(PORT_C)
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process ( PORT_C )
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begin
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if rising_edge(PORT_C) and (PORT_en='1') then
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state <= PORT_D;
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@ -18,7 +18,10 @@ import java.io.File;
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import java.io.IOException;
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import java.io.InputStream;
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import java.nio.file.Files;
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import java.text.DateFormat;
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import java.text.SimpleDateFormat;
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import java.util.ArrayList;
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import java.util.Date;
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/**
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* Test vhdl files in ghdl simulator
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@ -34,8 +37,8 @@ public class TestInSimulator extends TestCase {
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int tested = new FileScanner(this::check).scan(examples);
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// if tested is negative, ghdl was not found and tests are skipped!
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if (tested >= 0) {
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assertEquals(5, tested);
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assertEquals(5, testBenches);
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assertEquals(7, tested);
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assertEquals(7, testBenches);
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}
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}
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@ -55,7 +58,7 @@ public class TestInSimulator extends TestCase {
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private void check(File file) throws PinException, NodeException, ElementNotFoundException, IOException, FileScanner.SkipAllException, HDLException {
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ToBreakRunner br = new ToBreakRunner(file);
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File dir = Files.createTempDirectory("digital_vhdl_test_").toFile();
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File dir = Files.createTempDirectory("digital_vhdl_"+getTime()+"_").toFile();
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File vhdlFile = new File(dir, file.getName().replace('.', '_') + ".vhdl");
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CodePrinter out = new CodePrinter(vhdlFile);
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try (VHDLExporter vhdl = new VHDLExporter(br.getLibrary(), out){
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@ -125,6 +128,11 @@ public class TestInSimulator extends TestCase {
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}
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}
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private String getTime() {
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DateFormat f = new SimpleDateFormat("YY-MM-dd_HH-mm_ss");
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return f.format(new Date());
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}
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private static final class ReaderThread extends Thread {
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private final ByteArrayOutputStream baos;
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private final InputStream in;
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@ -40,8 +40,8 @@ public class TestExamples extends TestCase {
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*/
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public void testTestExamples() throws Exception {
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File examples = new File(Resources.getRoot(), "/dig/test");
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assertEquals(88, new FileScanner(this::check).scan(examples));
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assertEquals(79, testCasesInFiles);
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assertEquals(90, new FileScanner(this::check).scan(examples));
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assertEquals(81, testCasesInFiles);
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}
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144
src/test/resources/dig/test/vhdl/d_async.dig
Normal file
144
src/test/resources/dig/test/vhdl/d_async.dig
Normal file
@ -0,0 +1,144 @@
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<?xml version="1.0" encoding="utf-8"?>
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<circuit>
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<version>1</version>
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<attributes/>
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<visualElements>
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<visualElement>
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<elementName>In</elementName>
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<elementAttributes>
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<entry>
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<string>Label</string>
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<string>CLK</string>
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</entry>
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</elementAttributes>
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<pos x="300" y="240"/>
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</visualElement>
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<visualElement>
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<elementName>In</elementName>
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<elementAttributes>
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<entry>
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<string>Label</string>
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<string>D</string>
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</entry>
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</elementAttributes>
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<pos x="300" y="200"/>
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</visualElement>
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<visualElement>
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<elementName>In</elementName>
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<elementAttributes>
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<entry>
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<string>Label</string>
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<string>S</string>
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</entry>
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</elementAttributes>
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<pos x="300" y="160"/>
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</visualElement>
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<visualElement>
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<elementName>In</elementName>
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<elementAttributes>
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<entry>
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<string>Label</string>
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<string>C</string>
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</entry>
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</elementAttributes>
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<pos x="300" y="280"/>
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</visualElement>
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<visualElement>
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<elementName>Out</elementName>
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<elementAttributes>
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<entry>
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<string>Label</string>
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<string>Q</string>
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</entry>
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</elementAttributes>
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<pos x="440" y="200"/>
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</visualElement>
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<visualElement>
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<elementName>Out</elementName>
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<elementAttributes>
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<entry>
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<string>Label</string>
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<string>~Q</string>
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</entry>
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</elementAttributes>
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<pos x="520" y="220"/>
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</visualElement>
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<visualElement>
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<elementName>Testcase</elementName>
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<elementAttributes>
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<entry>
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<string>Testdata</string>
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<testData>
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<dataString>CLK D S C Q ~Q
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0 0 0 0 0 1
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0 1 0 0 0 1
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C 1 0 0 1 0
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0 0 0 0 1 0
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C 0 0 0 0 1
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0 0 0 1 0 1
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0 0 0 0 0 1
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0 0 1 0 1 0
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0 0 0 0 1 0
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</dataString>
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</testData>
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</entry>
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</elementAttributes>
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<pos x="480" y="260"/>
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</visualElement>
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<visualElement>
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<elementName>D_FF_AS</elementName>
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<elementAttributes/>
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<pos x="360" y="200"/>
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</visualElement>
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</visualElements>
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<wires>
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<wire>
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<p1 x="300" y="240"/>
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<p2 x="360" y="240"/>
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</wire>
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<wire>
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<p1 x="300" y="160"/>
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<p2 x="340" y="160"/>
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</wire>
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<wire>
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<p1 x="340" y="260"/>
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<p2 x="360" y="260"/>
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</wire>
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<wire>
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<p1 x="300" y="200"/>
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<p2 x="320" y="200"/>
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</wire>
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<wire>
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<p1 x="340" y="200"/>
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<p2 x="360" y="200"/>
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</wire>
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<wire>
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<p1 x="420" y="200"/>
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<p2 x="440" y="200"/>
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</wire>
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<wire>
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<p1 x="300" y="280"/>
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<p2 x="340" y="280"/>
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</wire>
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<wire>
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<p1 x="320" y="220"/>
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<p2 x="360" y="220"/>
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</wire>
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<wire>
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<p1 x="420" y="220"/>
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<p2 x="520" y="220"/>
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</wire>
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<wire>
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<p1 x="320" y="200"/>
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<p2 x="320" y="220"/>
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</wire>
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<wire>
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<p1 x="340" y="160"/>
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<p2 x="340" y="200"/>
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</wire>
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<wire>
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<p1 x="340" y="260"/>
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<p2 x="340" y="280"/>
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</wire>
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</wires>
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</circuit>
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171
src/test/resources/dig/test/vhdl/jk_async.dig
Normal file
171
src/test/resources/dig/test/vhdl/jk_async.dig
Normal file
@ -0,0 +1,171 @@
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<?xml version="1.0" encoding="utf-8"?>
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<circuit>
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<version>1</version>
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<attributes/>
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<visualElements>
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<visualElement>
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<elementName>JK_FF_AS</elementName>
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<elementAttributes/>
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<pos x="360" y="200"/>
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</visualElement>
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<visualElement>
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<elementName>In</elementName>
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<elementAttributes>
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<entry>
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<string>Label</string>
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<string>CLK</string>
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</entry>
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</elementAttributes>
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<pos x="300" y="240"/>
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</visualElement>
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<visualElement>
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<elementName>In</elementName>
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<elementAttributes>
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<entry>
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<string>Label</string>
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<string>J</string>
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</entry>
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</elementAttributes>
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<pos x="300" y="200"/>
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</visualElement>
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<visualElement>
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<elementName>In</elementName>
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<elementAttributes>
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<entry>
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<string>Label</string>
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<string>S</string>
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</entry>
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</elementAttributes>
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<pos x="300" y="160"/>
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</visualElement>
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<visualElement>
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<elementName>In</elementName>
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<elementAttributes>
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<entry>
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<string>Label</string>
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<string>K</string>
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</entry>
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</elementAttributes>
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<pos x="300" y="280"/>
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</visualElement>
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<visualElement>
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<elementName>In</elementName>
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<elementAttributes>
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<entry>
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<string>Label</string>
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<string>C</string>
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</entry>
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</elementAttributes>
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<pos x="300" y="320"/>
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</visualElement>
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<visualElement>
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<elementName>Out</elementName>
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<elementAttributes>
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<entry>
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<string>Label</string>
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<string>Q</string>
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</entry>
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</elementAttributes>
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<pos x="440" y="200"/>
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</visualElement>
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<visualElement>
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<elementName>Out</elementName>
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<elementAttributes>
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<entry>
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<string>Label</string>
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<string>~Q</string>
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</entry>
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</elementAttributes>
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<pos x="520" y="220"/>
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</visualElement>
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<visualElement>
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<elementName>Testcase</elementName>
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<elementAttributes>
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<entry>
|
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<string>Testdata</string>
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<testData>
|
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<dataString>CLK J K S C Q ~Q
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0 0 0 0 0 0 1
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C 1 0 0 0 1 0
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0 1 0 0 0 1 0
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0 0 0 0 0 1 0
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0 0 1 0 0 1 0
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C 0 1 0 0 0 1
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0 0 0 0 0 0 1
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C 1 0 0 0 1 0
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0 0 0 1 0 1 0
|
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0 0 0 0 1 0 1
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C 1 1 0 0 1 0
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C 1 1 0 0 0 1
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C 1 1 0 0 1 0
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C 1 1 0 0 0 1
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</dataString>
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</testData>
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</entry>
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</elementAttributes>
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<pos x="480" y="300"/>
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</visualElement>
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</visualElements>
|
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<wires>
|
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<wire>
|
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<p1 x="300" y="240"/>
|
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<p2 x="360" y="240"/>
|
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</wire>
|
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<wire>
|
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<p1 x="300" y="160"/>
|
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<p2 x="340" y="160"/>
|
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</wire>
|
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<wire>
|
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<p1 x="300" y="320"/>
|
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<p2 x="340" y="320"/>
|
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</wire>
|
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<wire>
|
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<p1 x="320" y="260"/>
|
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<p2 x="360" y="260"/>
|
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</wire>
|
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<wire>
|
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<p1 x="300" y="200"/>
|
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<p2 x="320" y="200"/>
|
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</wire>
|
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<wire>
|
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<p1 x="340" y="200"/>
|
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<p2 x="360" y="200"/>
|
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</wire>
|
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<wire>
|
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<p1 x="420" y="200"/>
|
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<p2 x="440" y="200"/>
|
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</wire>
|
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<wire>
|
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<p1 x="300" y="280"/>
|
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<p2 x="320" y="280"/>
|
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</wire>
|
||||
<wire>
|
||||
<p1 x="340" y="280"/>
|
||||
<p2 x="360" y="280"/>
|
||||
</wire>
|
||||
<wire>
|
||||
<p1 x="320" y="220"/>
|
||||
<p2 x="360" y="220"/>
|
||||
</wire>
|
||||
<wire>
|
||||
<p1 x="420" y="220"/>
|
||||
<p2 x="520" y="220"/>
|
||||
</wire>
|
||||
<wire>
|
||||
<p1 x="320" y="200"/>
|
||||
<p2 x="320" y="220"/>
|
||||
</wire>
|
||||
<wire>
|
||||
<p1 x="320" y="260"/>
|
||||
<p2 x="320" y="280"/>
|
||||
</wire>
|
||||
<wire>
|
||||
<p1 x="340" y="160"/>
|
||||
<p2 x="340" y="200"/>
|
||||
</wire>
|
||||
<wire>
|
||||
<p1 x="340" y="280"/>
|
||||
<p2 x="340" y="320"/>
|
||||
</wire>
|
||||
</wires>
|
||||
</circuit>
|
||||
Loading…
x
Reference in New Issue
Block a user