From d03cc1c492be8d4450e6364c7ac0203dc795d0d2 Mon Sep 17 00:00:00 2001
From: hneemann <helmut.neemann@arcor.de>
Date: Sun, 20 Dec 2020 10:19:48 +0100
Subject: [PATCH] minor improvement of verilog identifier renaming, closes #582

---
 .../digital/hdl/verilog2/VerilogRenaming.java   | 17 +++++++++--------
 .../hdl/verilog2/VerilogRenamingTest.java       |  2 ++
 .../digital/hdl/vhdl2/VHDLRenamingTest.java     |  2 ++
 3 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/src/main/java/de/neemann/digital/hdl/verilog2/VerilogRenaming.java b/src/main/java/de/neemann/digital/hdl/verilog2/VerilogRenaming.java
index 3c7a6377d..2cadf5230 100644
--- a/src/main/java/de/neemann/digital/hdl/verilog2/VerilogRenaming.java
+++ b/src/main/java/de/neemann/digital/hdl/verilog2/VerilogRenaming.java
@@ -6,8 +6,8 @@
 package de.neemann.digital.hdl.verilog2;
 
 import de.neemann.digital.hdl.model2.HDLModel;
-import java.util.Arrays;
 
+import java.util.Arrays;
 import java.util.HashSet;
 
 /**
@@ -38,17 +38,16 @@ public class VerilogRenaming implements HDLModel.Renaming {
         if (isKeyword(name) || !isFirstCharValid(name))
             // Escaped identifier, the space is part of the identifier.
             return "\\" + name + " ";
-        else {
+        else
             return cleanName(name);
-        }
     }
 
     private boolean isFirstCharValid(String name) {
         char c = name.charAt(0);
 
         return ((c >= 'a' && c <= 'z')
-                 || (c >= 'A' && c <= 'Z')
-                 || (c == '_'));
+                || (c >= 'A' && c <= 'Z')
+                || (c == '_'));
     }
 
     private boolean isKeyword(String str) {
@@ -62,12 +61,14 @@ public class VerilogRenaming implements HDLModel.Renaming {
         for (int i = 0; i < name.length(); i++) {
             char c = name.charAt(i);
             if ((c >= 'a' && c <= 'z')
-                || (c >= 'A' && c <= 'Z')
-                || (c >= '0' && c <= '9')
-                || (c == '_') || (c == '$'))
+                    || (c >= 'A' && c <= 'Z')
+                    || (c >= '0' && c <= '9')
+                    || (c == '_') || (c == '$'))
                 sb.append(c);
             else {
                 switch (c) {
+                    case '\\':
+                        break;
                     case '/':
                     case '!':
                     case '~':
diff --git a/src/test/java/de/neemann/digital/hdl/verilog2/VerilogRenamingTest.java b/src/test/java/de/neemann/digital/hdl/verilog2/VerilogRenamingTest.java
index 958c6fd1c..4c2269568 100644
--- a/src/test/java/de/neemann/digital/hdl/verilog2/VerilogRenamingTest.java
+++ b/src/test/java/de/neemann/digital/hdl/verilog2/VerilogRenamingTest.java
@@ -25,5 +25,7 @@ public class VerilogRenamingTest extends TestCase {
         assertEquals("\\a<b ", r.checkName("a<b"));
         assertEquals("\\a>b ", r.checkName("a>b"));
         assertEquals("\\a=b ", r.checkName("a=b"));
+        assertEquals("a_b", r.checkName("a\\_b"));
+        assertEquals("\\a^b ", r.checkName("a\\^b"));
     }
 }
\ No newline at end of file
diff --git a/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLRenamingTest.java b/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLRenamingTest.java
index 091047663..75be3a21f 100644
--- a/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLRenamingTest.java
+++ b/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLRenamingTest.java
@@ -25,5 +25,7 @@ public class VHDLRenamingTest extends TestCase {
         assertEquals("aleb", r.checkName("a<b"));
         assertEquals("agrb", r.checkName("a>b"));
         assertEquals("aeqb", r.checkName("a=b"));
+        assertEquals("a_b", r.checkName("a\\_b"));
+        assertEquals("a_b", r.checkName("a\\^b"));
     }
 }
\ No newline at end of file