diff --git a/src/main/resources/verilog/DIG_Neg.v b/src/main/resources/verilog/DIG_Neg.v
new file mode 100644
index 000000000..0ba3f1568
--- /dev/null
+++ b/src/main/resources/verilog/DIG_Neg.v
@@ -0,0 +1,12 @@
+<?
+    generics[0] := "Bits";
+?>
+module DIG_Neg #(
+    parameter Bits = 1
+)
+(
+      input signed [(Bits-1):0] in,
+      output signed [(Bits-1):0] out
+);
+    assign out = -in;
+endmodule
diff --git a/src/main/resources/vhdl/DIG_Neg.tem b/src/main/resources/vhdl/DIG_Neg.tem
new file mode 100644
index 000000000..1f5e0f8f2
--- /dev/null
+++ b/src/main/resources/vhdl/DIG_Neg.tem
@@ -0,0 +1,15 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+entity DIG_Neg is
+  generic ( Bits: integer ); <? vhdl.registerGeneric("Bits");?>
+  port (
+    p_in: in std_logic_vector ((Bits-1) downto 0);
+    p_out: out std_logic_vector ((Bits-1) downto 0) );
+end DIG_Neg;
+
+architecture Behavioral of DIG_Neg is
+begin
+    p_out <= std_logic_vector(-signed(p_in));
+end Behavioral;
\ No newline at end of file
diff --git a/src/test/java/de/neemann/digital/hdl/verilog2/VerilogSimulatorTest.java b/src/test/java/de/neemann/digital/hdl/verilog2/VerilogSimulatorTest.java
index 4e24b457f..a1dcf9cba 100644
--- a/src/test/java/de/neemann/digital/hdl/verilog2/VerilogSimulatorTest.java
+++ b/src/test/java/de/neemann/digital/hdl/verilog2/VerilogSimulatorTest.java
@@ -51,8 +51,8 @@ public class VerilogSimulatorTest extends TestCase {
         File examples = new File(Resources.getRoot(), "/dig/test/vhdl");
         try {
             int tested = new FileScanner(this::checkVerilogExport).noOutput().scan(examples);
-            assertEquals(57, tested);
-            assertEquals(51, testBenches);
+            assertEquals(58, tested);
+            assertEquals(52, testBenches);
         } catch (FileScanner.SkipAllException e) {
             // if iverilog is not installed its also ok
         }
diff --git a/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLSimulatorTest.java b/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLSimulatorTest.java
index b04de66e4..55152be14 100644
--- a/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLSimulatorTest.java
+++ b/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLSimulatorTest.java
@@ -43,8 +43,8 @@ public class VHDLSimulatorTest extends TestCase {
         File examples = new File(Resources.getRoot(), "/dig/test/vhdl");
         try {
             int tested = new FileScanner(this::checkVHDLExport).noOutput().scan(examples);
-            assertEquals(57, tested);
-            assertEquals(51, testBenches);
+            assertEquals(58, tested);
+            assertEquals(52, testBenches);
         } catch (FileScanner.SkipAllException e) {
             // if ghdl is not installed its also ok
         }
diff --git a/src/test/java/de/neemann/digital/integration/TestExamples.java b/src/test/java/de/neemann/digital/integration/TestExamples.java
index 248f05b98..6ad6d2caa 100644
--- a/src/test/java/de/neemann/digital/integration/TestExamples.java
+++ b/src/test/java/de/neemann/digital/integration/TestExamples.java
@@ -44,8 +44,8 @@ public class TestExamples extends TestCase {
      */
     public void testTestExamples() throws Exception {
         File examples = new File(Resources.getRoot(), "/dig/test");
-        assertEquals(192, new FileScanner(this::check).scan(examples));
-        assertEquals(181, testCasesInFiles);
+        assertEquals(193, new FileScanner(this::check).scan(examples));
+        assertEquals(182, testCasesInFiles);
     }
 
     /**
diff --git a/src/test/resources/dig/test/vhdl/neg.dig b/src/test/resources/dig/test/vhdl/neg.dig
new file mode 100644
index 000000000..641daecfd
--- /dev/null
+++ b/src/test/resources/dig/test/vhdl/neg.dig
@@ -0,0 +1,83 @@
+<?xml version="1.0" encoding="utf-8"?>
+<circuit>
+  <version>1</version>
+  <attributes/>
+  <visualElements>
+    <visualElement>
+      <elementName>In</elementName>
+      <elementAttributes>
+        <entry>
+          <string>Label</string>
+          <string>a</string>
+        </entry>
+        <entry>
+          <string>Bits</string>
+          <int>4</int>
+        </entry>
+        <entry>
+          <string>intFormat</string>
+          <intFormat>decSigned</intFormat>
+        </entry>
+      </elementAttributes>
+      <pos x="360" y="200"/>
+    </visualElement>
+    <visualElement>
+      <elementName>Testcase</elementName>
+      <elementAttributes>
+        <entry>
+          <string>Testdata</string>
+          <testData>
+            <dataString>a y
+
+0 0
+1 15
+2 14
+14 2
+15 1
+8  8</dataString>
+          </testData>
+        </entry>
+      </elementAttributes>
+      <pos x="360" y="240"/>
+    </visualElement>
+    <visualElement>
+      <elementName>Neg</elementName>
+      <elementAttributes>
+        <entry>
+          <string>Bits</string>
+          <int>4</int>
+        </entry>
+      </elementAttributes>
+      <pos x="380" y="200"/>
+    </visualElement>
+    <visualElement>
+      <elementName>Out</elementName>
+      <elementAttributes>
+        <entry>
+          <string>Label</string>
+          <string>y</string>
+        </entry>
+        <entry>
+          <string>intFormat</string>
+          <intFormat>decSigned</intFormat>
+        </entry>
+        <entry>
+          <string>Bits</string>
+          <int>4</int>
+        </entry>
+      </elementAttributes>
+      <pos x="460" y="200"/>
+    </visualElement>
+  </visualElements>
+  <wires>
+    <wire>
+      <p1 x="360" y="200"/>
+      <p2 x="380" y="200"/>
+    </wire>
+    <wire>
+      <p1 x="440" y="200"/>
+      <p2 x="460" y="200"/>
+    </wire>
+  </wires>
+  <measurementOrdering/>
+</circuit>
\ No newline at end of file