diff --git a/src/main/dig/hdl/BASYS3.config b/src/main/dig/hdl/BASYS3.config index e0c4eed18..68405b40d 100644 --- a/src/main/dig/hdl/BASYS3.config +++ b/src/main/dig/hdl/BASYS3.config @@ -7,10 +7,15 @@ vivado/<?=shortname?>.xpr + + + xc7a35ticpg236-1L + .vhdl + + LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; @@ -22,7 +27,7 @@ entity clockGenerator is cin: in std_logic ); end clockGenerator; - + architecture Behavioral of clockGenerator is -- Don't use a logic signal as clock source in a real world application! @@ -89,7 +94,7 @@ begin M_IDEAL := D_MIN*VCO_MAX/F_IN; - F_DES := hdl.frequency/1000000.0; + F_DES := model.frequency/1000000.0; bestError:=F_DES; bestErrorM:=M_MAX; @@ -205,11 +210,11 @@ end Behavioral; ]]> - + ]]> - + \n");?> - - + - + + + \n" + " \n" + - " deal with <?=path?>, Bits: <?=hdl.ports[0].bits?> (<?=hdl.ports[0].name?>)\n" + + " deal with <?=path?>, Bits: <?=model.ports[0].bits?> (<?=model.ports[0].name?>)\n" + " \n" + " \n" + " test\n" +