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improved the vhdl test bench creator
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e152fbbef1
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@ -69,11 +69,12 @@ public class VHDLTestBenchCreator {
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if (p > 0)
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filename = filename.substring(0, p);
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VHDLRenaming renaming = new VHDLRenaming();
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for (ElementAttributes tc : testCases) {
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String testName = tc.getLabel();
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if (testName.length() > 0)
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testName = filename + "_" + testName + "_tb";
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else
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if (testName.length() > 0) {
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testName = filename + "_" + renaming.checkName(testName) + "_tb";
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} else
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testName = filename + "_tb";
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File f = new File(file.getParentFile(), testName + ".vhdl");
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@ -179,7 +180,12 @@ public class VHDLTestBenchCreator {
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.print(" AND patterns(").print(loopVar).print(").").print(p.getName()).print(" = ")
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.print(getSimpleValue(p.getBits(), 'Z'))
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.print(")").eol();
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out.inc().print("report \"wrong value for ").print(p.getName()).print(" ").print(loopVar).print("=\" & integer'image(").print(loopVar).println(") severity error;").dec();
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out.inc().print("report \"wrong value for ").print(p.getName()).print(", ").print(loopVar).print("=\" & integer'image(").print(loopVar).println(")")
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.print(" & \", expected \"")
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.print(" & ").print(convertFunc(p)).print("(patterns(").print(loopVar).print(").").print(p.getName()).print(")")
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.print(" & \", found \"")
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.print(" & ").print(convertFunc(p)).print("(").print(p.getName()).print(")")
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.print(" severity error;").dec();
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}
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out.dec().println("end loop;");
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@ -188,6 +194,12 @@ public class VHDLTestBenchCreator {
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out.dec().println("end behav;");
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}
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private String convertFunc(HDLPort p) {
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if (p.getBits()>1)
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return "to_hstring";
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return "std_logic'image";
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}
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private boolean loopVarExists(String loopVar, ArrayList<HDLPort> ports) {
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for (HDLPort p : ports)
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if (p.getName().equalsIgnoreCase(loopVar))
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