fixes handling of whitespaces in verilog identifiers; closes #831

src/main/java/de/neemann/digital/hdl/verilog2/VerilogRenaming.java

@@ -37,11 +37,17 @@ public class VerilogRenaming implements HDLModel.Renaming {
     public String checkName(String name) {
         if (isKeyword(name) || !isFirstCharValid(name))
             // Escaped identifier, the space is part of the identifier.
-            return "\\" + name + " ";
+            return "\\" + replaceWhitespace(name) + " ";
         else
             return cleanName(name);
     }
 
+    private String replaceWhitespace(String name) {
+        return name
+                .replace(' ', '_')
+                .replace('\t', '_');
+    }
+
     private boolean isFirstCharValid(String name) {
         char c = name.charAt(0);
 
@@ -69,6 +75,10 @@ public class VerilogRenaming implements HDLModel.Renaming {
                 switch (c) {
                     case '\\':
                         break;
+                    case '\t':
+                    case ' ':
+                        sb.append("_");
+                        break;
                     case '/':
                     case '!':
                     case '~':

src/test/java/de/neemann/digital/hdl/verilog2/VerilogGeneratorTest.java

@@ -14,7 +14,7 @@ public class VerilogGeneratorTest extends TestCase {
     public void testComb() throws Exception {
         ToBreakRunner br = new ToBreakRunner("dig/hdl/model2/comb.dig");
         CodePrinterStr out = new CodePrinterStr();
-        VerilogGenerator gen = new VerilogGenerator(br.getLibrary(), out).export(br.getCircuit());
+        new VerilogGenerator(br.getLibrary(), out).export(br.getCircuit());
 
         assertEquals("/*\n"
                 + " * Generated by Digital. Don't modify this file!\n"
@@ -77,7 +77,7 @@ public class VerilogGeneratorTest extends TestCase {
     public void testSplitter3() throws Exception {
         ToBreakRunner br = new ToBreakRunner("dig/hdl/model2/splitter3.dig");
         CodePrinterStr out = new CodePrinterStr();
-        VerilogGenerator gen = new VerilogGenerator(br.getLibrary(), out).export(br.getCircuit());
+        new VerilogGenerator(br.getLibrary(), out).export(br.getCircuit());
 
         assertEquals("/*\n"
                 + " * Generated by Digital. Don't modify this file!\n"
@@ -97,7 +97,7 @@ public class VerilogGeneratorTest extends TestCase {
     public void testSplitter2() throws Exception {
         ToBreakRunner br = new ToBreakRunner("dig/hdl/model2/splitter2.dig");
         CodePrinterStr out = new CodePrinterStr();
-        VerilogGenerator gen = new VerilogGenerator(br.getLibrary(), out).export(br.getCircuit());
+        new VerilogGenerator(br.getLibrary(), out).export(br.getCircuit());
 
         assertEquals("/*\n"
                 + " * Generated by Digital. Don't modify this file!\n"
@@ -121,7 +121,7 @@ public class VerilogGeneratorTest extends TestCase {
     public void testSplitter2I() throws Exception {
         ToBreakRunner br = new ToBreakRunner("dig/hdl/splitter2.dig");
         CodePrinterStr out = new CodePrinterStr();
-        VerilogGenerator gen = new VerilogGenerator(br.getLibrary(), out).export(br.getCircuit());
+        new VerilogGenerator(br.getLibrary(), out).export(br.getCircuit());
 
         assertEquals("/*\n"
                 + " * Generated by Digital. Don't modify this file!\n"
@@ -171,4 +171,35 @@ public class VerilogGeneratorTest extends TestCase {
                 "endmodule\n", out.toString());
     }
 
+    public void testNames() throws Exception {
+        ToBreakRunner br = new ToBreakRunner("dig/hdl_names/main.dig");
+        CodePrinterStr out = new CodePrinterStr();
+        new VerilogGenerator(br.getLibrary(), out).export(br.getCircuit());
+
+        assertEquals("/*\n" +
+                " * Generated by Digital. Don't modify this file!\n" +
+                " * Any changes will be lost if this file is regenerated.\n" +
+                " */\n" +
+                "\n" +
+                "module a_b (\n" +
+                "  input A,\n" +
+                "  input B,\n" +
+                "  output Y\n" +
+                ");\n" +
+                "  assign Y = (A & B);\n" +
+                "endmodule\n" +
+                "\n" +
+                "module main (\n" +
+                "  input A,\n" +
+                "  input B,\n" +
+                "  output Y\n" +
+                ");\n" +
+                "  a_b a_b_i0 (\n" +
+                "    .A( A ),\n" +
+                "    .B( B ),\n" +
+                "    .Y( Y )\n" +
+                "  );\n" +
+                "endmodule\n", out.toString());
+    }
+
 }

src/test/java/de/neemann/digital/hdl/vhdl2/VHDLGeneratorTest.java

@@ -14,7 +14,7 @@ public class VHDLGeneratorTest extends TestCase {
     public void testComb() throws Exception {
         ToBreakRunner br = new ToBreakRunner("dig/hdl/model2/comb.dig");
         CodePrinterStr out = new CodePrinterStr();
-        VHDLGenerator gen = new VHDLGenerator(br.getLibrary(), out).export(br.getCircuit());
+        new VHDLGenerator(br.getLibrary(), out).export(br.getCircuit());
 
         assertEquals("-- generated by Digital. Don't modify this file!\n" +
                 "-- Any changes will be lost if this file is regenerated.\n" +
@@ -85,7 +85,7 @@ public class VHDLGeneratorTest extends TestCase {
     public void testSplitter3() throws Exception {
         ToBreakRunner br = new ToBreakRunner("dig/hdl/model2/splitter3.dig");
         CodePrinterStr out = new CodePrinterStr();
-        VHDLGenerator gen = new VHDLGenerator(br.getLibrary(), out).export(br.getCircuit());
+        new VHDLGenerator(br.getLibrary(), out).export(br.getCircuit());
 
         assertEquals("-- generated by Digital. Don't modify this file!\n" +
                 "-- Any changes will be lost if this file is regenerated.\n" +
@@ -111,7 +111,7 @@ public class VHDLGeneratorTest extends TestCase {
     public void testSplitter2() throws Exception {
         ToBreakRunner br = new ToBreakRunner("dig/hdl/model2/splitter2.dig");
         CodePrinterStr out = new CodePrinterStr();
-        VHDLGenerator gen = new VHDLGenerator(br.getLibrary(), out).export(br.getCircuit());
+        new VHDLGenerator(br.getLibrary(), out).export(br.getCircuit());
 
         assertEquals("-- generated by Digital. Don't modify this file!\n" +
                 "-- Any changes will be lost if this file is regenerated.\n" +
@@ -141,7 +141,7 @@ public class VHDLGeneratorTest extends TestCase {
     public void testSplitter2I() throws Exception {
         ToBreakRunner br = new ToBreakRunner("dig/hdl/splitter2.dig");
         CodePrinterStr out = new CodePrinterStr();
-        VHDLGenerator gen = new VHDLGenerator(br.getLibrary(), out).export(br.getCircuit());
+        new VHDLGenerator(br.getLibrary(), out).export(br.getCircuit());
 
         assertEquals("-- generated by Digital. Don't modify this file!\n" +
                 "-- Any changes will be lost if this file is regenerated.\n" +
@@ -202,4 +202,49 @@ public class VHDLGeneratorTest extends TestCase {
                 "end Behavioral;\n", out.toString());
     }
 
+    public void testNames() throws Exception {
+        ToBreakRunner br = new ToBreakRunner("dig/hdl_names/main.dig");
+        CodePrinterStr out = new CodePrinterStr();
+        new VHDLGenerator(br.getLibrary(), out).export(br.getCircuit());
+
+        assertEquals("-- generated by Digital. Don't modify this file!\n" +
+                "-- Any changes will be lost if this file is regenerated.\n" +
+                "\n" +
+                "LIBRARY ieee;\n" +
+                "USE ieee.std_logic_1164.all;\n" +
+                "USE ieee.numeric_std.all;\n" +
+                "\n" +
+                "entity a_b is\n" +
+                "  port (\n" +
+                "    A: in std_logic;\n" +
+                "    B: in std_logic;\n" +
+                "    Y: out std_logic);\n" +
+                "end a_b;\n" +
+                "\n" +
+                "architecture Behavioral of a_b is\n" +
+                "begin\n" +
+                "  Y <= (A AND B);\n" +
+                "end Behavioral;\n" +
+                "\n" +
+                "LIBRARY ieee;\n" +
+                "USE ieee.std_logic_1164.all;\n" +
+                "USE ieee.numeric_std.all;\n" +
+                "\n" +
+                "entity main is\n" +
+                "  port (\n" +
+                "    A: in std_logic;\n" +
+                "    B: in std_logic;\n" +
+                "    Y: out std_logic);\n" +
+                "end main;\n" +
+                "\n" +
+                "architecture Behavioral of main is\n" +
+                "begin\n" +
+                "  gate0: entity work.a_b\n" +
+                "    port map (\n" +
+                "      A => A,\n" +
+                "      B => B,\n" +
+                "      Y => Y);\n" +
+                "end Behavioral;\n", out.toString());
+    }
+
 }

src/test/resources/dig/hdl_names/a b.dig

@@ -0,0 +1,57 @@
+<?xml version="1.0" encoding="utf-8"?>
+<circuit>
+  <version>1</version>
+  <attributes/>
+  <visualElements>
+    <visualElement>
+      <elementName>And</elementName>
+      <elementAttributes/>
+      <pos x="380" y="200"/>
+    </visualElement>
+    <visualElement>
+      <elementName>Out</elementName>
+      <elementAttributes>
+        <entry>
+          <string>Label</string>
+          <string>Y</string>
+        </entry>
+      </elementAttributes>
+      <pos x="460" y="220"/>
+    </visualElement>
+    <visualElement>
+      <elementName>In</elementName>
+      <elementAttributes>
+        <entry>
+          <string>Label</string>
+          <string>A</string>
+        </entry>
+      </elementAttributes>
+      <pos x="360" y="200"/>
+    </visualElement>
+    <visualElement>
+      <elementName>In</elementName>
+      <elementAttributes>
+        <entry>
+          <string>Label</string>
+          <string>B</string>
+        </entry>
+      </elementAttributes>
+      <pos x="360" y="240"/>
+    </visualElement>
+  </visualElements>
+  <wires>
+    <wire>
+      <p1 x="360" y="240"/>
+      <p2 x="380" y="240"/>
+    </wire>
+    <wire>
+      <p1 x="360" y="200"/>
+      <p2 x="380" y="200"/>
+    </wire>
+    <wire>
+      <p1 x="440" y="220"/>
+      <p2 x="460" y="220"/>
+    </wire>
+  </wires>
+  <measurementOrdering/>
+</circuit>

src/test/resources/dig/hdl_names/main.dig

@@ -0,0 +1,57 @@
+<?xml version="1.0" encoding="utf-8"?>
+<circuit>
+  <version>1</version>
+  <attributes/>
+  <visualElements>
+    <visualElement>
+      <elementName>a b.dig</elementName>
+      <elementAttributes/>
+      <pos x="500" y="300"/>
+    </visualElement>
+    <visualElement>
+      <elementName>Out</elementName>
+      <elementAttributes>
+        <entry>
+          <string>Label</string>
+          <string>Y</string>
+        </entry>
+      </elementAttributes>
+      <pos x="580" y="320"/>
+    </visualElement>
+    <visualElement>
+      <elementName>In</elementName>
+      <elementAttributes>
+        <entry>
+          <string>Label</string>
+          <string>A</string>
+        </entry>
+      </elementAttributes>
+      <pos x="480" y="300"/>
+    </visualElement>
+    <visualElement>
+      <elementName>In</elementName>
+      <elementAttributes>
+        <entry>
+          <string>Label</string>
+          <string>B</string>
+        </entry>
+      </elementAttributes>
+      <pos x="480" y="340"/>
+    </visualElement>
+  </visualElements>
+  <wires>
+    <wire>
+      <p1 x="560" y="320"/>
+      <p2 x="580" y="320"/>
+    </wire>
+    <wire>
+      <p1 x="480" y="340"/>
+      <p2 x="500" y="340"/>
+    </wire>
+    <wire>
+      <p1 x="480" y="300"/>
+      <p2 x="500" y="300"/>
+    </wire>
+  </wires>
+  <measurementOrdering/>
+</circuit>