From e95d24c00a8283de5e8fca568038156d03f81dc7 Mon Sep 17 00:00:00 2001 From: hneemann Date: Sun, 19 May 2019 12:56:52 +0200 Subject: [PATCH] updated the documentation. --- src/main/dig/hdl/{BASYS3_Config.xml => BASYS3.config} | 0 .../hdl/{TinyFPGA_BX_Config.xml => TinyFPGA_BX.config} | 0 ...erilogClockExample.xml => VerilogClockExample.config} | 0 .../java/de/neemann/digital/toolchain/BASYS3Test.java | 4 ++-- src/test/resources/docu/static_de.xml | 8 +++++--- src/test/resources/docu/static_en.xml | 9 ++++++--- src/test/resources/docu/static_es.xml | 2 +- src/test/resources/docu/static_es_ref.xml | 2 +- src/test/resources/docu/static_pt.xml | 2 +- src/test/resources/docu/static_pt_ref.xml | 2 +- 10 files changed, 17 insertions(+), 12 deletions(-) rename src/main/dig/hdl/{BASYS3_Config.xml => BASYS3.config} (100%) rename src/main/dig/hdl/{TinyFPGA_BX_Config.xml => TinyFPGA_BX.config} (100%) rename src/main/dig/hdl/{VerilogClockExample.xml => VerilogClockExample.config} (100%) diff --git a/src/main/dig/hdl/BASYS3_Config.xml b/src/main/dig/hdl/BASYS3.config similarity index 100% rename from src/main/dig/hdl/BASYS3_Config.xml rename to src/main/dig/hdl/BASYS3.config diff --git a/src/main/dig/hdl/TinyFPGA_BX_Config.xml b/src/main/dig/hdl/TinyFPGA_BX.config similarity index 100% rename from src/main/dig/hdl/TinyFPGA_BX_Config.xml rename to src/main/dig/hdl/TinyFPGA_BX.config diff --git a/src/main/dig/hdl/VerilogClockExample.xml b/src/main/dig/hdl/VerilogClockExample.config similarity index 100% rename from src/main/dig/hdl/VerilogClockExample.xml rename to src/main/dig/hdl/VerilogClockExample.config diff --git a/src/test/java/de/neemann/digital/toolchain/BASYS3Test.java b/src/test/java/de/neemann/digital/toolchain/BASYS3Test.java index 845f6d2cd..fb538fe58 100644 --- a/src/test/java/de/neemann/digital/toolchain/BASYS3Test.java +++ b/src/test/java/de/neemann/digital/toolchain/BASYS3Test.java @@ -20,11 +20,11 @@ import java.io.IOException; public class BASYS3Test extends TestCase { public void testMMCME2_BASEParams() throws IOException, ParserException, HGSEvalException { - Configuration c = Configuration.load(new File(Resources.getRoot(), "../../main/dig/hdl/BASYS3_Config.xml")); + Configuration c = Configuration.load(new File(Resources.getRoot(), "../../main/dig/hdl/BASYS3.config")); FileToCreate clock = c.getFileById("MMCME2_BASE",null); String content = clock.getContent(); - for (int f = 5000; f < 500000; f+=77) { + for (int f = 4688; f < 500000; f+=77) { Context context = new Context().disableLogging(); context.declareVar("hdl", new ElementAttributes() diff --git a/src/test/resources/docu/static_de.xml b/src/test/resources/docu/static_de.xml index e6d24bab2..2d01ed6d4 100644 --- a/src/test/resources/docu/static_de.xml +++ b/src/test/resources/docu/static_de.xml @@ -393,7 +393,7 @@ Beim BASYS3 Board wird, wenn die Taktfrequenz niedrig ist, ein Frequenzteiler in den HDL Code integriert, - um den Boardtakt entsprechend zu teilen. Wenn die in der Schaltung gewählte Taktfrequenz über 37kHz + um den Boardtakt entsprechend zu teilen. Wenn die in der Schaltung gewählte Taktfrequenz über 4.7MHz liegt, wird die MMCM Einheit des Artix-7 zur Takterzeugung verwendet. Dies stellt sicher, dass die für die Taktverteilung vorgesehenen FPGA-Resourcen auch tatsächlich verwendet werden. @@ -409,8 +409,10 @@ Hardware-Manager kann dieser in ein BASYS3 Board übertragen werden. - Um neben der HDL Datei auch die erforderliche Constraints-Datei erzeugen zu lassen, muss die Schaltung - ein Textfeld mit dem Text "Board: BASYS3", "Board: MimasV1" oder "Board: MimasV2" enthalten. + Um neben der HDL Datei auch die erforderliche Constraints-Datei erzeugen zu lassen, muss in den + Einstellungen das Entsprechende Board konfiguriert werden. Dazu kann im Feld "Toolchain Konfiguration" + die entspechende XML-Datei ausgewählt werden. Die verfügbaren Konfgurationen finden sich im Ordner + examples/hdl und haben die Dateiendung .config. diff --git a/src/test/resources/docu/static_en.xml b/src/test/resources/docu/static_en.xml index bcab6b357..174722743 100644 --- a/src/test/resources/docu/static_en.xml +++ b/src/test/resources/docu/static_en.xml @@ -367,7 +367,7 @@ At a BASYS3 board, if the circuit clock frequency is low, a frequency divider is integrated into the HDL code to divide the board clock accordingly. - If the clock frequency selected in the circuit exceeds 37kHz, the MMCM unit of the + If the clock frequency selected in the circuit exceeds 4.7MHz, the MMCM unit of the Artix-7 is used for clock generation. This ensures that the FPGA resources provided for the clock distribution are used. This allows the included example processor to run at 20MHz, and if you can do without the @@ -383,8 +383,11 @@ to program a BASYS3 board. - To create the required constraints file, the circuit must contain a text field with the text - "Board: BASYS3", "Board: MimasV1" or "Board: MimasV2". + In order to create the required constraints file in addition to the HDL file, the corresponding board + must be configured in the settings. In the field "Toolchain Configuration" the corresponding XML file + can be selected. + The available configurations can be found in the folder examples/hdl and have the file + extension .config. diff --git a/src/test/resources/docu/static_es.xml b/src/test/resources/docu/static_es.xml index 6d8bd829c..11ad73e5a 100644 --- a/src/test/resources/docu/static_es.xml +++ b/src/test/resources/docu/static_es.xml @@ -307,7 +307,7 @@ En la placa BASYS3, si la frecuencia del reloj del circuito es baja, se integrará en el código HDL un divisor de frecuencia para dividir la frecuencia de la placa adecuadamente. - Si la frecuencia de reloj seleccionada supera los 37 kHz, la unidad MMCM de la Artix-7 se empleará para la generación del reloj + Si la frecuencia de reloj seleccionada supera los 4.7MHz, la unidad MMCM de la Artix-7 se empleará para la generación del reloj Esto asegura que los recursos de la FPGA proporcionados por la distribución del reloj se emplean. Esto permite al procesador incluido correr a 20 MHz y si sabe hacerlo sin el multiplicador, es posible hacerlo a 30 MHz. diff --git a/src/test/resources/docu/static_es_ref.xml b/src/test/resources/docu/static_es_ref.xml index bcab6b357..7da7a092c 100644 --- a/src/test/resources/docu/static_es_ref.xml +++ b/src/test/resources/docu/static_es_ref.xml @@ -367,7 +367,7 @@ At a BASYS3 board, if the circuit clock frequency is low, a frequency divider is integrated into the HDL code to divide the board clock accordingly. - If the clock frequency selected in the circuit exceeds 37kHz, the MMCM unit of the + If the clock frequency selected in the circuit exceeds 4.7MHz, the MMCM unit of the Artix-7 is used for clock generation. This ensures that the FPGA resources provided for the clock distribution are used. This allows the included example processor to run at 20MHz, and if you can do without the diff --git a/src/test/resources/docu/static_pt.xml b/src/test/resources/docu/static_pt.xml index 66c900dca..76b223a4f 100644 --- a/src/test/resources/docu/static_pt.xml +++ b/src/test/resources/docu/static_pt.xml @@ -364,7 +364,7 @@ Na placa BASYS3, se a frequência de clock de um circuito for baixa, um divisor de frequências será incorporado ao código HDL a fim de dividir o clock da placa para o valor conveniente. - Se a frequência de clock selecionada exceder 37kHz, a unidade MMCM do Artix-7 será usada para a geração de clock. + Se a frequência de clock selecionada exceder 4.7MHz, a unidade MMCM do Artix-7 será usada para a geração de clock. Isso garantirá que os recursos disponíveis na FPGA para distribuição do clock serão usados. Isso permitirá que o exemplo de processador possa ser executado a 20MHz, e se quiser, sem o multiplicador, 30HMz também será possível. diff --git a/src/test/resources/docu/static_pt_ref.xml b/src/test/resources/docu/static_pt_ref.xml index 37efd9e54..bcf26bd59 100644 --- a/src/test/resources/docu/static_pt_ref.xml +++ b/src/test/resources/docu/static_pt_ref.xml @@ -367,7 +367,7 @@ At a BASYS3 board, if the circuit clock frequency is low, a frequency divider is integrated into the HDL code to divide the board clock accordingly. - If the clock frequency selected in the circuit exceeds 37kHz, the MMCM unit of the + If the clock frequency selected in the circuit exceeds 4.7MHz, the MMCM unit of the Artix-7 is used for clock generation. This ensures that the FPGA resources provided for the clock distribution are used. This allows the included example processor to run at 20MHz, and if you can do without the