This commit is contained in:
hneemann 2017-08-14 18:52:49 +02:00
parent 327d3938ae
commit e9ddde0c73

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@ -3,7 +3,7 @@ Release Notes
HEAD, planned as v0.14
- Added VHDL export (Not yet complete!)
- Pin numbers are strings to allow FPGA pin names like "U16".
- Added Support for BASYS3-Board (*.xdc constrains file is written)
- Added support for BASYS3-Board (*.xdc constrains file is written)
v0.13, released on 25. Jul 2017
- Introduced a library of sub circuits which are available in every circuit.