diff --git a/src/main/java/de/neemann/digital/core/memory/RAMAsync.java b/src/main/java/de/neemann/digital/core/memory/RAMAsync.java index 5d8173463..a483fc2b0 100644 --- a/src/main/java/de/neemann/digital/core/memory/RAMAsync.java +++ b/src/main/java/de/neemann/digital/core/memory/RAMAsync.java @@ -33,7 +33,8 @@ public class RAMAsync extends Node implements Element, RAMInterface { .addAttribute(Keys.ADDR_BITS) .addAttribute(Keys.IS_PROGRAM_MEMORY) .addAttribute(Keys.INVERTER_CONFIG) - .addAttribute(Keys.LABEL); + .addAttribute(Keys.LABEL) + .supportsHDL(); private final DataField memory; private final ObservableValue output; diff --git a/src/main/resources/verilog/DIG_RAMAsync.v b/src/main/resources/verilog/DIG_RAMAsync.v new file mode 100644 index 000000000..a7be0f450 --- /dev/null +++ b/src/main/resources/verilog/DIG_RAMAsync.v @@ -0,0 +1,25 @@ +module +#( + parameter Bits = 8, + parameter AddrBits = 4 +) +( + input [(AddrBits-1):0] A, + input [(Bits-1):0] D, + input we, + output [(Bits-1):0] Q +); + reg [(Bits-1):0] memory[0:((1 << AddrBits) - 1)]; + + assign Q = memory[A]; + + always @ (we, A, D) begin + if (we) + memory[A] <= D; + end +endmodule diff --git a/src/main/resources/vhdl/DIG_RAMAsync.tem b/src/main/resources/vhdl/DIG_RAMAsync.tem new file mode 100644 index 000000000..ea1d4d8fe --- /dev/null +++ b/src/main/resources/vhdl/DIG_RAMAsync.tem @@ -0,0 +1,28 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.numeric_std.all; + +entity DIG_RAMAsync is + generic ( + Bits : integer; + AddrBits : integer ); + port ( + Q: out std_logic_vector ((Bits-1) downto 0); + A: in std_logic_vector ((AddrBits-1) downto 0); + D: in std_logic_vector ((Bits-1) downto 0); + we: in std_logic); +end DIG_RAMAsync; + +architecture Behavioral of DIG_RAMAsync is + -- CAUTION: uses distributed RAM + type memoryType is array(0 to (2**AddrBits)-1) of STD_LOGIC_VECTOR((Bits-1) downto 0); + signal memory : memoryType; +begin + process ( we,A,D ) + begin + if we='1' then + memory(to_integer(unsigned(A))) <= D; + end if; + end process; + Q <= memory(to_integer(unsigned(A))); +end Behavioral; diff --git a/src/test/java/de/neemann/digital/hdl/verilog2/VerilogSimulatorTest.java b/src/test/java/de/neemann/digital/hdl/verilog2/VerilogSimulatorTest.java index 9c96dadaf..fd60c3617 100644 --- a/src/test/java/de/neemann/digital/hdl/verilog2/VerilogSimulatorTest.java +++ b/src/test/java/de/neemann/digital/hdl/verilog2/VerilogSimulatorTest.java @@ -51,8 +51,8 @@ public class VerilogSimulatorTest extends TestCase { File examples = new File(Resources.getRoot(), "/dig/test/vhdl"); try { int tested = new FileScanner(this::checkVerilogExport).noOutput().scan(examples); - assertEquals(67, tested); - assertEquals(57, testBenches); + assertEquals(68, tested); + assertEquals(58, testBenches); } catch (FileScanner.SkipAllException e) { // if iverilog is not installed its also ok } diff --git a/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLSimulatorTest.java b/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLSimulatorTest.java index ea0dafb7f..a4002f1da 100644 --- a/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLSimulatorTest.java +++ b/src/test/java/de/neemann/digital/hdl/vhdl2/VHDLSimulatorTest.java @@ -43,8 +43,8 @@ public class VHDLSimulatorTest extends TestCase { File examples = new File(Resources.getRoot(), "/dig/test/vhdl"); try { int tested = new FileScanner(this::checkVHDLExport).noOutput().scan(examples); - assertEquals(67, tested); - assertEquals(57, testBenches); + assertEquals(68, tested); + assertEquals(58, testBenches); } catch (FileScanner.SkipAllException e) { // if ghdl is not installed its also ok } diff --git a/src/test/java/de/neemann/digital/integration/TestExamples.java b/src/test/java/de/neemann/digital/integration/TestExamples.java index d2f91c110..dadc8f2c4 100644 --- a/src/test/java/de/neemann/digital/integration/TestExamples.java +++ b/src/test/java/de/neemann/digital/integration/TestExamples.java @@ -51,8 +51,8 @@ public class TestExamples extends TestCase { */ public void testTestExamples() throws Exception { File examples = new File(Resources.getRoot(), "/dig/test"); - assertEquals(208, new FileScanner(this::check).scan(examples)); - assertEquals(193, testCasesInFiles); + assertEquals(209, new FileScanner(this::check).scan(examples)); + assertEquals(194, testCasesInFiles); } /** diff --git a/src/test/resources/dig/test/vhdl/ram/RAMAsync.dig b/src/test/resources/dig/test/vhdl/ram/RAMAsync.dig new file mode 100644 index 000000000..12868015a --- /dev/null +++ b/src/test/resources/dig/test/vhdl/ram/RAMAsync.dig @@ -0,0 +1,130 @@ + + + 1 + + + + In + + + Label + A + + + Bits + 8 + + + + + + In + + + Label + we + + + + + + In + + + Label + D + + + Bits + 8 + + + + + + Out + + + Label + Q + + + Bits + 8 + + + + + + RAMAsync + + + AddrBits + 8 + + + Bits + 8 + + + + + + Testcase + + + Testdata + + we A D Q +loop(n,256) +1 (n) (n) (n) +end loop +loop(n,256) +0 (n) 0 (n) +end loop +loop(n,256) +0 (n) 0 (n) +end loop + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file