1823 Commits

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Author	SHA1	Message	Date
hneemann	d0d9a9453e	allow clock component in sub circuits	2017-08-12 15:25:58 +02:00
hneemann	584e82224e	fixed a bug in the clock divider	2017-08-12 12:56:58 +02:00
hneemann	d83c24b129	simplified vhdl output read avoiding	2017-08-12 11:09:47 +02:00
hneemann	cbf270b19a	added a clock divider to vhdl file	2017-08-11 23:42:02 +02:00
helmut.neemann	77d041a824	fixed some vivado issues	2017-08-11 16:29:14 +02:00
hneemann	b9cecb5bf6	added vivado constrains support	2017-08-11 14:03:28 +02:00
hneemann	632cb4bb13	updated release notes	2017-08-11 12:13:22 +02:00
hneemann	56c7608235	moved to non integer string pin numbers	2017-08-11 12:05:00 +02:00
hneemann	2414738949	added vhdl template for JK-flipflop	2017-08-11 08:52:50 +02:00
hneemann	00511cc9d0	avoids reading vhdl outputs	2017-08-10 13:04:09 +02:00
hneemann	ebec915217	added constants to vhdl	2017-08-10 11:42:38 +02:00
hneemann	03e6f9ab95	added comparator to vhdl lib	2017-08-10 10:04:04 +02:00
hneemann	cd4aa49faf	simplified adding of VHDL templates	2017-08-10 09:32:31 +02:00
hneemann	979487230e	added a vhdl template file reader	2017-08-09 22:22:26 +02:00
hneemann	5a48d2f20a	added decoder to vhdl export	2017-08-09 20:20:15 +02:00
hneemann	a08a28c3d7	added multiplexer vhdl export	2017-08-09 19:03:58 +02:00
hneemann	02089e1984	only white spaces	2017-08-09 16:40:58 +02:00
hneemann	9b9b4517e7	fixed some splitters issues	2017-08-09 15:17:10 +02:00
hneemann	aa2cf790e2	added splitters to vhdl generation	2017-08-09 13:59:38 +02:00
hneemann	20d8506997	refactoring of vhdl code generation	2017-08-09 11:52:09 +02:00
hneemann	bdacb81db4	added direct connection from input to output	2017-08-09 00:15:00 +02:00
hneemann	5e6a452d8b	fixed clock error	2017-08-08 23:10:05 +02:00
hneemann	e789f0f9f4	added generic vhdl	2017-08-08 22:59:52 +02:00
hneemann	1ea88ad0f7	minor simplifications	2017-08-08 19:34:13 +02:00
hneemann	488f603849	simplified handling of inverterConfig	2017-08-08 19:17:48 +02:00
hneemann	4d66df9d8c	inverterConfig is running	2017-08-08 19:13:26 +02:00
hneemann	2abe5275d5	first VHDL code with correct syntax	2017-08-08 18:16:03 +02:00
hneemann	2b08f55af0	intermediate representation for hdl generation	2017-08-08 13:53:03 +02:00
hneemann	22cd754052	first vhdl test	2017-08-07 22:16:12 +02:00
hneemann	37ece25fe8	updated release notes v0.13	2017-07-25 07:50:27 +02:00
hneemann	1e527c5033	fixed some findbugs issues	2017-07-24 09:13:13 +02:00
hneemann	08fc96c29f	fixed problems with "C" hotkey in single gate mode	2017-07-23 20:16:20 +02:00
hneemann	fde688d3cb	added memory folder to 74xx lib	2017-07-23 09:08:19 +02:00
hneemann	ef0886e205	added a new test case for error cause indication	2017-07-22 15:46:01 +02:00
hneemann	a0df1dc323	typo	2017-07-22 12:26:17 +02:00
hneemann	cdea8e3fb9	updated release notes	2017-07-22 11:53:25 +02:00
hneemann	98a7459d39	improved error messages	2017-07-22 11:51:52 +02:00
hneemann	1e64844442	simplified the origin book keeping	2017-07-21 16:31:44 +02:00
hneemann	12141c22b7	simplified the origin book keeping	2017-07-21 16:28:30 +02:00
hneemann	e4308826a9	updated README.md	2017-07-21 11:06:51 +02:00
hneemann	e85f9ae6a2	better error messages at certain wiring issues	2017-07-21 10:16:33 +02:00
hneemann	87aacedad7	typo	2017-07-21 09:22:40 +02:00
hneemann	1b39561f42	better error messages in power supply	2017-07-20 20:26:37 +02:00
hneemann	990565071a	added VCC and GND pins to 74xx circuits	2017-07-20 19:56:26 +02:00
hneemann	49154d43b1	more robust check of power supply pin numbers	2017-07-20 18:40:29 +02:00
hneemann	15dc6fe948	fixed a bug in the power supply	2017-07-20 17:43:41 +02:00
hneemann	e4367eb1b0	fixed a bug in the power supply	2017-07-20 17:31:22 +02:00
hneemann	9ca0b2b84b	renamed VDD to VCC in power supply	2017-07-20 13:15:15 +02:00
hneemann	b630f7d6ed	renamed VDD to VCC in power supply	2017-07-20 12:31:07 +02:00
hneemann	da3f2311e5	scan of library only at startup	2017-07-18 20:48:27 +02:00