From 0a12727b3fa67e959730d79111471652fb7215a0 Mon Sep 17 00:00:00 2001
From: John Winans <john@winans.org>
Date: Fri, 18 May 2018 14:35:41 -0500
Subject: [PATCH] Add citations to intro material.

---
 book/intro/chapter.tex | 10 +++++-----
 book/preamble.tex      |  9 ++++++++-
 2 files changed, 13 insertions(+), 6 deletions(-)

diff --git a/book/intro/chapter.tex b/book/intro/chapter.tex
index c1b5084..9154fcf 100644
--- a/book/intro/chapter.tex
+++ b/book/intro/chapter.tex
@@ -147,7 +147,7 @@ The number of bits in each register is defined by the \acrfull{isa}.
 
 Analogous to a {\em core} in other types of CPUs, a {\em \acrshort{hart}} 
 (hardware \gls{thread}) in a RISC-V CPU refers to the collection of 32 registers,
-instruction execution unit and ALU.
+instruction execution unit and ALU.\cite[p.~20]{rvismv1v22:2017}
 
 When more than one hart is present in a CPU, a different stream of instructions can 
 be executed on each hart all at the same time.
@@ -183,10 +183,10 @@ process each one.
 
 The RISC-V ISA is defined as a set of modules.  The purpose of
 dividing the ISA into modules is to allow an implementer to select which 
-features to incorporate into a CPU design.
+features to incorporate into a CPU design.\cite[p.~4]{rvismv1v22:2017}
 
 Any given RISC-V implementation must provide one of the {\em base}
-modules and zero or more of the {\em extension} modules.
+modules and zero or more of the {\em extension} modules.\cite[p.~4]{rvismv1v22:2017}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 \subsection{RV Base Modules}
@@ -194,7 +194,7 @@ modules and zero or more of the {\em extension} modules.
 
 The base modules are RV32I (32-bit general purpose), 
 RV32E (32-bit embedded), RV64I (64-bit general purpose) 
-and RV128I (128-bit general purpose).
+and RV128I (128-bit general purpose).\cite[p.~4]{rvismv1v22:2017}
 
 These base modules provide the minimal functional set of integer operations
 needed to execute a useful application.  The differing bit-widths address
@@ -207,7 +207,7 @@ This text primarily focuses on the RV32I base module and how to program it.
 \subsection{Extension Modules}
 
 RISC-V extension modules may be included by an implementer interested
-in optimizing a design for one or more purposes.
+in optimizing a design for one or more purposes.\cite[p.~4]{rvismv1v22:2017}
 
 \index{RV32M}%
 \index{RV32A}%
diff --git a/book/preamble.tex b/book/preamble.tex
index b388186..d526c6b 100644
--- a/book/preamble.tex
+++ b/book/preamble.tex
@@ -45,11 +45,18 @@
 \usepackage{makeidx,showidx}	% showidx breaks hyperref when loaded before hyperref
 
 
-% put line numbers on every page
+% for one-sided on left margin
 \usepackage{lineno}
 \linenumbers
 
+% for two-sided on inside margin
+%\usepackage[switch*,pagewise]{lineno}
+%\linenumbers
+%\runningpagewiselinenumbers
 
+%\renewcommand\linenumberfont{\normalfont\small\sffamily}
+%\renewcommand\linenumberfont{\normalfont\footnotesize\sffamily}
+\renewcommand\linenumberfont{\normalfont\scriptsize\sffamily}
 
 
 %\usepackage{url}