mirror of
https://github.com/johnwinans/rvalp.git
synced 2025-09-28 21:50:38 -04:00
CLean up instruction format links from refcard.
This commit is contained in:
John Winans
parent
902524b244
commit
0f87512cf9
@ -457,10 +457,10 @@
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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% #1 the binary encoding
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\newcommand\DrawInsnTypeRShiftTikz[1]{
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@ -474,7 +474,7 @@
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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@ -635,7 +635,7 @@
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\newcommand\TDrawInsnTypeRShiftPicture[5]{
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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@ -783,7 +783,7 @@
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\begin{scope}[shift={(0,-7.5)}]\DrawInsnBoxLabelsJtype\end{scope}
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@ -803,6 +803,11 @@
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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% #1 opcode
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% #2 func3
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@ -814,7 +819,8 @@
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\DrawInsnBoxRel{14}{12}{}
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\DrawInsnBoxRel{11}{7}{imm[4:1\textbar11]}
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\DrawInsnBoxRel{6}{0}{}
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\draw(33,.75) node[right]{#3};
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\draw(\InsnBoxTypePosY,.75) node[right]{\hyperref[insnformat:itype]{B-type}};
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@ -829,7 +835,8 @@
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\draw(33,.75) node[right]{#3};
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\begin{scope}[shift={(31-6,0)}]\DrawBitstringX{#1}\end{scope}
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\begin{scope}[shift={(31-14,0)}]\DrawBitstringX{#2}\end{scope}
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@ -846,7 +853,8 @@
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\DrawInsnBoxRel{14}{12}{}
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\DrawInsnBoxRel{11}{7}{rd}
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\DrawInsnBoxRel{6}{0}{}
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\draw(33,.75) node[right]{#3};
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\begin{scope}[shift={(31-6,0)}]\DrawBitstringX{#1}\end{scope}
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\begin{scope}[shift={(31-14,0)}]\DrawBitstringX{#2}\end{scope}
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@ -864,7 +872,8 @@
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\DrawInsnBoxRel{14}{12}{}
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\DrawInsnBoxRel{11}{7}{imm[4:0]}
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\DrawInsnBoxRel{6}{0}{}
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\draw(33,.75) node[right]{#3};
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\draw(\InsnBoxTypePosY,.75) node[right]{\hyperref[insnformat:stype]{S-type}};
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\draw(\InsnBoxMneumonicPosY,.75) node[right]{#3};
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\begin{scope}[shift={(31-6,0)}]\DrawBitstringX{#1}\end{scope}
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\begin{scope}[shift={(31-14,0)}]\DrawBitstringX{#2}\end{scope}
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@ -881,7 +890,8 @@
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\DrawInsnBoxRel{14}{12}{}
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\DrawInsnBoxRel{11}{7}{rd}
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\DrawInsnBoxRel{6}{0}{}
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\draw(33,.75) node[right]{#3};
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\begin{scope}[shift={(31-6,0)}]\DrawBitstringX{#1}\end{scope}
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\begin{scope}[shift={(31-14,0)}]\DrawBitstringX{#2}\end{scope}
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@ -899,7 +909,8 @@
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\DrawInsnBoxRel{14}{12}{}
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\DrawInsnBoxRel{11}{7}{rd}
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\DrawInsnBoxRel{6}{0}{}
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\draw(33,.75) node[right]{#3};
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% \draw(\InsnBoxTypePosY,.75) node[right]{\hyperref[insnformat:rtype]{R-type}};
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\draw(\InsnBoxMneumonicPosY,.75) node[right]{#3};
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\begin{scope}[shift={(31-6,0)}]\DrawBitstringX{#1}\end{scope}
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\begin{scope}[shift={(31-14,0)}]\DrawBitstringX{#2}\end{scope}
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@ -914,7 +925,8 @@
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\DrawInsnBoxRel{14}{12}{}
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\DrawInsnBoxRel{11}{7}{}
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\DrawInsnBoxRel{6}{0}{}
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\draw(33,.75) node[right]{#3};
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% \draw(\InsnBoxTypePosY,.75) node[right]{\hyperref[insnformat:rtype]{R-type}};
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\draw(\InsnBoxMneumonicPosY,.75) node[right]{#3};
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\begin{scope}[shift={(31-6,0)}]\DrawBitstringX{#1}\end{scope}
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\begin{scope}[shift={(31-11,0)}]\DrawBitstringX{00000}\end{scope}
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@ -929,7 +941,8 @@
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\DrawInsnBoxRel{31}{12}{imm[31:12]}
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\DrawInsnBoxRel{11}{7}{rd}
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\DrawInsnBoxRel{6}{0}{}
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\draw(33,.75) node[right]{#2};
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\draw(\InsnBoxTypePosY,.75) node[right]{\hyperref[insnformat:utype]{U-type}};
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\draw(\InsnBoxMneumonicPosY,.75) node[right]{#2};
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\begin{scope}[shift={(31-6,0)}]\DrawBitstringX{#1}\end{scope}
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}
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@ -940,7 +953,8 @@
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\DrawInsnBoxRel{31}{12}{imm[20\textbar10:1\textbar11\textbar19:12]}
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\DrawInsnBoxRel{11}{7}{rd}
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\DrawInsnBoxRel{6}{0}{}
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\draw(33,.75) node[right]{#2};
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\draw(\InsnBoxTypePosY,.75) node[right]{\hyperref[insnformat:jtype]{J-type}};
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\draw(\InsnBoxMneumonicPosY,.75) node[right]{#2};
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\begin{scope}[shift={(31-6,0)}]\DrawBitstringX{#1}\end{scope}
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@ -1134,6 +1148,7 @@
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\DrawInsnBoxCastle{0}{0}
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\end{scope}
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\DrawInsnBoxRel{31}{0}{}
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\draw(33,.5) node[text width = 10, text height = 1, right]{imm\_j};
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\begin{scope}[shift={(0,0)}]\DrawBitstringX{aaaaaaaaaaaapqrstuvwnbcdefghjkm0}\end{scope}
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\begin{scope}[shift={(0,0)}]\DrawHexMarkersRel{32}\end{scope}
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@ -1214,6 +1229,7 @@
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\DrawInsnBoxCastle{0}{0}
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\end{scope}
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\DrawInsnBoxRel{31}{0}{}
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\draw(33,.5) node[text width = 10, text height = 1, right]{imm\_b};
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\begin{scope}[shift={(0,0)}]\DrawBitstringX{aaaaaaaaaaaaaaaaaaaanbcdefghjkm0}\end{scope}
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@ -1286,6 +1302,7 @@
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\DrawInsnBoxCastle{4}{0}
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\end{scope}
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\DrawInsnBoxRel{31}{0}{}
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\draw(33,.5) node[text width = 10, text height = 1, right]{imm\_s};
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\begin{scope}[shift={(0,0)}]\DrawBitstringX{aaaaaaaaaaaaaaaaaaaaabcdefghjkmn}\end{scope}
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@ -1354,6 +1371,7 @@
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\DrawInsnBoxCastle{4}{0}
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\end{scope}
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\DrawInsnBoxRel{31}{0}{}
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\draw(33,.5) node[text width = 10, text height = 1, right]{imm\_i};
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\begin{scope}[shift={(0,0)}]\DrawBitstringX{aaaaaaaaaaaaaaaaaaaaabcdefghjkmn}\end{scope}
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@ -1367,6 +1385,75 @@
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\EndTikzPicture
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}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\newcommand\DrawInsnOpIShiftTypeDecoding{
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\BeginTikzPicture
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\begin{scope}[shift={(0,-1.5)}]
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\DrawInsnTypeI{0000010abcde00011000001110000011}
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\pgfmathsetmacro\ArrowNorth{\BitBoxArrowInset}
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\node at (0,\ZeroNodeY) {0};
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\draw[red,->](.5,\ZeroNodeY)to[out=0,in=110](26,\ArrowSouth);
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\draw[red,->](.5,\ZeroNodeY)to[out=0,in=110](27,\ArrowSouth);
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\draw[blue,->](8,\ArrowNorth)to[out=270,in=90](28,\ArrowSouth); % 4
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\draw[blue,->](9,\ArrowNorth)to[out=270,in=90](29,\ArrowSouth); % 3
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\draw[blue,->](10,\ArrowNorth)to[out=270,in=90](30,\ArrowSouth); % 2
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\draw[blue,->](11,\ArrowNorth)to[out=270,in=90](31,\ArrowSouth); % 1
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\draw[blue,->](12,\ArrowNorth)to[out=270,in=90](32,\ArrowSouth); % 0
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\begin{scope}[shift={(0,0)}]\DrawHexMarkersRel{32}\end{scope}
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\end{scope}
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\begin{scope}[shift={(0,-19.75)}]
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\DrawInsnBoxCastle{4}{0}
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\end{scope}
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\DrawInsnBoxRel{31}{0}{}
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\draw(33,.5) node[text width = 10, text height = 1, right]{shamt\_i};
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\begin{scope}[shift={(0,0)}]\DrawBitstringX{000000000000000000000000000abcde}\end{scope}
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\begin{scope}[shift={(0,0)}]\DrawHexMarkersRel{32}\end{scope}
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\InsnBoxFieldWidthArrow{31}{5}
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\InsnBoxFieldWidthArrow{4}{0}
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\EndTikzPicture
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\newcommand\DrawInsnOpUTypeDecoding{
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\BeginTikzPicture
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@ -1422,6 +1509,7 @@
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\DrawInsnBoxCastle{11}{0}
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\end{scope}
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\DrawInsnBoxRel{31}{0}{}
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\draw(33,.5) node[text width = 10, text height = 1, right]{imm\_u};
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\begin{scope}[shift={(0,0)}]\DrawBitstringX{abcdefghjkmnpqrstuvw000000000000}\end{scope}
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@ -10,77 +10,77 @@
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\hline
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add & rd, rs1, rs2 & \hyperref[insnformat:rtype]{R} & \hyperref[insn:add]{Add} & {\tt rd $\leftarrow$ rs1 + rs2, pc $\leftarrow$ pc+4}\\
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\hline
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addi & rd, rs1, imm & \hyperref[insnformat:itype]{I} & \hyperref[insn:addi]{Add Immediate} & {\tt rd $\leftarrow$ rs1+sx(imm), pc $\leftarrow$ pc+4}\\
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addi & rd, rs1, imm & \hyperref[insnformat:itype]{I} & \hyperref[insn:addi]{Add Immediate} & {\tt rd $\leftarrow$ rs1 + \hyperref[imm.i:decode]{imm\_i}, pc $\leftarrow$ pc+4}\\
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\hline
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and & rd, rs1, rs2 & \hyperref[insnformat:rtype]{R} & \hyperref[insn:and]{And} & {\tt rd $\leftarrow$ rs1 \& rs2, pc $\leftarrow$ pc+4}\\
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\hline
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andi & rd, rs1, imm & \hyperref[insnformat:itype]{I} & \hyperref[insn:andi]{And Immediate} & {\tt rd $\leftarrow$ rs1 \& sx(imm), pc $\leftarrow$ pc+4}\\
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andi & rd, rs1, imm & \hyperref[insnformat:itype]{I} & \hyperref[insn:andi]{And Immediate} & {\tt rd $\leftarrow$ rs1 \& \hyperref[imm.i:decode]{imm\_i}, pc $\leftarrow$ pc+4}\\
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\hline
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auipc & rd, imm & \hyperref[insnformat:utype]{U} & \hyperref[insn:auipc]{Add Upper Immediate to PC} & {\tt rd $\leftarrow$ pc + zr(imm), pc $\leftarrow$ pc+4}\\
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auipc & rd, imm & \hyperref[insnformat:utype]{U} & \hyperref[insn:auipc]{Add Upper Immediate to PC} & {\tt rd $\leftarrow$ pc + \hyperref[imm.u:decode]{imm\_u}, pc $\leftarrow$ pc+4}\\
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\hline
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beq & rs1, rs2, imm & \hyperref[insnformat:btype]{B} & \hyperref[insn:beq]{Branch Equal} & {\tt pc $\leftarrow$ pc + (\verb@(rs1==rs2) ? sx(imm[12:1]<<1) : 4@)}\\
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beq & rs1, rs2, imm & \hyperref[insnformat:btype]{B} & \hyperref[insn:beq]{Branch Equal} & {\tt pc $\leftarrow$ pc + (\verb@(rs1==rs2) ? @\hyperref[imm.b:decode]{imm\_b}\verb@ : 4@)}\\
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\hline
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bge & rs1, rs2, imm & \hyperref[insnformat:btype]{B} & \hyperref[insn:bge]{Branch Greater or Equal} & {\tt pc $\leftarrow$ pc + (\verb@(rs1>=rs2) ? sx(imm[12:1]<<1) : 4@)}\\
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bge & rs1, rs2, imm & \hyperref[insnformat:btype]{B} & \hyperref[insn:bge]{Branch Greater or Equal} & {\tt pc $\leftarrow$ pc + (\verb@(rs1>=rs2) ? @\hyperref[imm.b:decode]{imm\_b}\verb@ : 4@)}\\
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\hline
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bgeu & rs1, rs2, imm & \hyperref[insnformat:btype]{B} & \hyperref[insn:bgeu]{Branch Greater or Equal Unsigned} & {\tt pc $\leftarrow$ pc + (\verb@(rs1>=rs2) ? sx(imm[12:1]<<1) : 4@)}\\
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bgeu & rs1, rs2, imm & \hyperref[insnformat:btype]{B} & \hyperref[insn:bgeu]{Branch Greater or Equal Unsigned} & {\tt pc $\leftarrow$ pc + (\verb@(rs1>=rs2) ? @\hyperref[imm.b:decode]{imm\_b}\verb@ : 4@)}\\
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\hline
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blt & rs1, rs2, imm & \hyperref[insnformat:btype]{B} & \hyperref[insn:blt]{Branch Less Than} & {\tt pc $\leftarrow$ pc + (\verb@(rs1<rs2) ? sx(imm[12:1]<<1) : 4@)}\\
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blt & rs1, rs2, imm & \hyperref[insnformat:btype]{B} & \hyperref[insn:blt]{Branch Less Than} & {\tt pc $\leftarrow$ pc + (\verb@(rs1<rs2) ? @\hyperref[imm.b:decode]{imm\_b}\verb@ : 4@)}\\
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\hline
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bltu & rs1, rs2, imm & \hyperref[insnformat:btype]{B} & \hyperref[insn:bltu]{Branch Less Than Unsigned} & {\tt pc $\leftarrow$ pc + (\verb@(rs1<rs2) ? sx(imm[12:1]<<1) : 4@)}\\
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bltu & rs1, rs2, imm & \hyperref[insnformat:btype]{B} & \hyperref[insn:bltu]{Branch Less Than Unsigned} & {\tt pc $\leftarrow$ pc + (\verb@(rs1<rs2) ? @\hyperref[imm.b:decode]{imm\_b}\verb@ : 4@)}\\
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\hline
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bne & rs1, rs2, imm & \hyperref[insnformat:btype]{B} & \hyperref[insn:bne]{Branch Not Equal} & {\tt pc $\leftarrow$ pc + (\verb@(rs1!=rs2) ? sx(imm[12:1]<<1) : 4@)}\\
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bne & rs1, rs2, imm & \hyperref[insnformat:btype]{B} & \hyperref[insn:bne]{Branch Not Equal} & {\tt pc $\leftarrow$ pc + (\verb@(rs1!=rs2) ? @\hyperref[imm.b:decode]{imm\_b}\verb@ : 4@)}\\
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\hline
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jal & rd, imm & \hyperref[insnformat:jtype]{J} & \hyperref[insn:jal]{Jump And Link} & {\tt rd $\leftarrow$ pc+4, pc $\leftarrow$ pc+sx(imm<<1)}\\
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jal & rd, imm & \hyperref[insnformat:jtype]{J} & \hyperref[insn:jal]{Jump And Link} & {\tt rd $\leftarrow$ pc+4, pc $\leftarrow$ pc+\hyperref[imm.j:decode]{imm\_j}}\\
|
||||
\hline
|
||||
jalr & rd, rs1, imm & \hyperref[insnformat:itype]{I} & \hyperref[insn:jalr]{Jump And Link Register} & {\tt rd $\leftarrow$ pc+4, pc $\leftarrow$ (rs1+sx(imm))\&\textasciitilde{}1}\\
|
||||
jalr & rd, rs1, imm & \hyperref[insnformat:itype]{I} & \hyperref[insn:jalr]{Jump And Link Register} & {\tt rd $\leftarrow$ pc+4, pc $\leftarrow$ (rs1+\hyperref[imm.i:decode]{imm\_i})\&\textasciitilde{}1}\\
|
||||
\hline
|
||||
lb & rd, imm(rs1) & \hyperref[insnformat:itype]{I} & \hyperref[insn:lb]{Load Byte} & {\tt rd $\leftarrow$ sx(m8(rs1+sx(imm))), pc $\leftarrow$ pc+4}\\
|
||||
lb & rd, imm(rs1) & \hyperref[insnformat:itype]{I} & \hyperref[insn:lb]{Load Byte} & {\tt rd $\leftarrow$ sx(m8(rs1+\hyperref[imm.i:decode]{imm\_i})), pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
lbu & rd, imm(rs1) & \hyperref[insnformat:itype]{I} & \hyperref[insn:lbu]{Load Byte Unsigned} & {\tt rd $\leftarrow$ zx(m8(rs1+sx(imm))), pc $\leftarrow$ pc+4}\\
|
||||
lbu & rd, imm(rs1) & \hyperref[insnformat:itype]{I} & \hyperref[insn:lbu]{Load Byte Unsigned} & {\tt rd $\leftarrow$ zx(m8(rs1+\hyperref[imm.i:decode]{imm\_i})), pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
lh & rd, imm(rs1) & \hyperref[insnformat:itype]{I} & \hyperref[insn:lh]{Load Halfword} & {\tt rd $\leftarrow$ sx(m16(rs1+sx(imm))), pc $\leftarrow$ pc+4}\\
|
||||
lh & rd, imm(rs1) & \hyperref[insnformat:itype]{I} & \hyperref[insn:lh]{Load Halfword} & {\tt rd $\leftarrow$ sx(m16(rs1+\hyperref[imm.i:decode]{imm\_i})), pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
lhu & rd, imm(rs1) & \hyperref[insnformat:itype]{I} & \hyperref[insn:lhu]{Load Halfword Unsigned} & {\tt rd $\leftarrow$ zx(m16(rs1+sx(imm))), pc $\leftarrow$ pc+4}\\
|
||||
lhu & rd, imm(rs1) & \hyperref[insnformat:itype]{I} & \hyperref[insn:lhu]{Load Halfword Unsigned} & {\tt rd $\leftarrow$ zx(m16(rs1+\hyperref[imm.i:decode]{imm\_i})), pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
lui & rd, imm & \hyperref[insnformat:utype]{U} & \hyperref[insn:lui]{Load Upper Immediate} & {\tt rd $\leftarrow$ zr(imm), pc $\leftarrow$ pc+4}\\
|
||||
lui & rd, imm & \hyperref[insnformat:utype]{U} & \hyperref[insn:lui]{Load Upper Immediate} & {\tt rd $\leftarrow$ \hyperref[imm.u:decode]{imm\_u}, pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
lw & rd, imm(rs1) & \hyperref[insnformat:itype]{I} & \hyperref[insn:lw]{Load Word} & {\tt rd $\leftarrow$ sx(m32(rs1+sx(imm))), pc $\leftarrow$ pc+4}\\
|
||||
lw & rd, imm(rs1) & \hyperref[insnformat:itype]{I} & \hyperref[insn:lw]{Load Word} & {\tt rd $\leftarrow$ sx(m32(rs1+\hyperref[imm.i:decode]{imm\_i})), pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
or & rd, rs1, rs2 & \hyperref[insnformat:rtype]{R} & \hyperref[insn:or]{Or} & {\tt rd $\leftarrow$ rs1 | rs2, pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
ori & rd, rs1, imm & \hyperref[insnformat:itype]{I} & \hyperref[insn:ori]{Or Immediate} & {\tt rd $\leftarrow$ rs1 | sx(imm), pc $\leftarrow$ pc+4}\\
|
||||
ori & rd, rs1, imm & \hyperref[insnformat:itype]{I} & \hyperref[insn:ori]{Or Immediate} & {\tt rd $\leftarrow$ rs1 | \hyperref[imm.i:decode]{imm\_i}, pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
sb & rs2, imm(rs1) & \hyperref[insnformat:stype]{S} & \hyperref[insn:sb]{Store Byte} & {\tt m8(rs1+sx(imm)) $\leftarrow$ rs2[7:0], pc $\leftarrow$ pc+4}\\
|
||||
sb & rs2, imm(rs1) & \hyperref[insnformat:stype]{S} & \hyperref[insn:sb]{Store Byte} & {\tt m8(rs1+\hyperref[imm.s:decode]{imm\_s}) $\leftarrow$ rs2[7:0], pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
sh & rs2, imm(rs1) & \hyperref[insnformat:stype]{S} & \hyperref[insn:sh]{Store Halfword} & {\tt m16(rs1+sx(imm)) $\leftarrow$ rs2[15:0], pc $\leftarrow$ pc+4}\\
|
||||
sh & rs2, imm(rs1) & \hyperref[insnformat:stype]{S} & \hyperref[insn:sh]{Store Halfword} & {\tt m16(rs1+\hyperref[imm.s:decode]{imm\_s}) $\leftarrow$ rs2[15:0], pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
sll & rd, rs1, rs2 & \hyperref[insnformat:rtype]{R} & \hyperref[insn:sll]{Shift Left Logical} & {\tt rd $\leftarrow$ rs1 << rs2, pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
slli & rd, rs1, shamt & \hyperref[insnformat:itype]{I} & \hyperref[insn:slli]{Shift Left Logical Immediate} & {\tt rd $\leftarrow$ rs1 << shamt, pc $\leftarrow$ pc+4}\\
|
||||
slli & rd, rs1, shamt & \hyperref[insnformat:itype]{I} & \hyperref[insn:slli]{Shift Left Logical Immediate} & {\tt rd $\leftarrow$ rs1 << \hyperref[shamt.i:decode]{shamt\_i}, pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
slt & rd, rs1, rs2 & \hyperref[insnformat:rtype]{R} & \hyperref[insn:slt]{Set Less Than} & {\tt rd $\leftarrow$ (rs1 < rs2) ? 1 : 0, pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
slti & rd, rs1, imm & \hyperref[insnformat:itype]{I} & \hyperref[insn:slti]{Set Less Than Immediate} & {\tt rd $\leftarrow$ (rs1 < sx(imm)) ? 1 : 0, pc $\leftarrow$ pc+4}\\
|
||||
slti & rd, rs1, imm & \hyperref[insnformat:itype]{I} & \hyperref[insn:slti]{Set Less Than Immediate} & {\tt rd $\leftarrow$ (rs1 < \hyperref[imm.i:decode]{imm\_i}) ? 1 : 0, pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
sltiu & rd, rs1, imm & \hyperref[insnformat:itype]{I} & \hyperref[insn:sltiu]{Set Less Than Immediate Unsigned} & {\tt rd $\leftarrow$ (rs1 < sx(imm)) ? 1 : 0, pc $\leftarrow$ pc+4}\\
|
||||
sltiu & rd, rs1, imm & \hyperref[insnformat:itype]{I} & \hyperref[insn:sltiu]{Set Less Than Immediate Unsigned} & {\tt rd $\leftarrow$ (rs1 < \hyperref[imm.i:decode]{imm\_i}) ? 1 : 0, pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
sltu & rd, rs1, rs2 & \hyperref[insnformat:rtype]{R} & \hyperref[insn:sltu]{Set Less Than Unsigned} & {\tt rd $\leftarrow$ (rs1 < rs2) ? 1 : 0, pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
sra & rd, rs1, rs2 & \hyperref[insnformat:rtype]{R} & \hyperref[insn:sra]{Shift Right Arithmetic} & {\tt rd $\leftarrow$ rs1 >> rs2, pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
srai & rd, rs1, shamt & \hyperref[insnformat:itype]{I} & \hyperref[insn:srai]{Shift Right Arithmetic Immediate} & {\tt rd $\leftarrow$ rs1 >> shamt, pc $\leftarrow$ pc+4}\\
|
||||
srai & rd, rs1, shamt & \hyperref[insnformat:itype]{I} & \hyperref[insn:srai]{Shift Right Arithmetic Immediate} & {\tt rd $\leftarrow$ rs1 >> \hyperref[shamt.i:decode]{shamt\_i}, pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
srl & rd, rs1, rs2 & \hyperref[insnformat:rtype]{R} & \hyperref[insn:srl]{Shift Right Logical} & {\tt rd $\leftarrow$ rs1 >> rs2, pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
srli & rd, rs1, shamt & \hyperref[insnformat:itype]{I} & \hyperref[insn:srli]{Shift Right Logical Immediate} & {\tt rd $\leftarrow$ rs1 >> shamt, pc $\leftarrow$ pc+4}\\
|
||||
srli & rd, rs1, shamt & \hyperref[insnformat:itype]{I} & \hyperref[insn:srli]{Shift Right Logical Immediate} & {\tt rd $\leftarrow$ rs1 >> \hyperref[shamt.i:decode]{shamt\_i}, pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
sub & rd, rs1, rs2 & \hyperref[insnformat:rtype]{R} & \hyperref[insn:sub]{Subtract} & {\tt rd $\leftarrow$ rs1 - rs2, pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
sw & rs2, imm(rs1) & \hyperref[insnformat:stype]{S} & \hyperref[insn:sw]{Store Word} & {\tt m32(rs1+sx(imm)) $\leftarrow$ rs2[31:0], pc $\leftarrow$ pc+4}\\
|
||||
sw & rs2, imm(rs1) & \hyperref[insnformat:stype]{S} & \hyperref[insn:sw]{Store Word} & {\tt m32(rs1+\hyperref[imm.s:decode]{imm\_s}) $\leftarrow$ rs2[31:0], pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
xor & rd, rs1, rs2 & \hyperref[insnformat:rtype]{R} & \hyperref[insn:xor]{Exclusive Or} & {\tt rd $\leftarrow$ rs1 \^{} rs2, pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
xori & rd, rs1, imm & \hyperref[insnformat:itype]{I} & \hyperref[insn:xori]{Exclusive Or Immediate} & {\tt rd $\leftarrow$ rs1 \^{} sx(imm), pc $\leftarrow$ pc+4}\\
|
||||
xori & rd, rs1, imm & \hyperref[insnformat:itype]{I} & \hyperref[insn:xori]{Exclusive Or Immediate} & {\tt rd $\leftarrow$ rs1 \^{} \hyperref[imm.i:decode]{imm\_i}, pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
\end{tabular}
|
||||
}
|
||||
@ -88,5 +88,5 @@ xori & rd, rs1, imm & \hyperref[insnformat:itype]{I} & \hyperref[insn:xori]{Ex
|
||||
\newpage
|
||||
{\Large RV32I Base Instruction Set Encoding}~\cite[p.~104]{rvismv1v22:2017}
|
||||
|
||||
\DrawAllInsnTypes\\
|
||||
%\DrawAllInsnTypes\\
|
||||
\DrawAllInsnOps
|
||||
|
||||
@ -273,8 +273,8 @@ This simplification can also allow it operate faster.
|
||||
\DrawInsnTypeUTikz{00000000000000000000000000000000}\\
|
||||
\DrawInsnTypeJTikz{00000000000000000000000000000000}\\
|
||||
\DrawInsnTypeITikz{00000000000000000000000000000000}\\
|
||||
\DrawInsnTypeIShiftTikz{00000000000000000000000000000000}\\
|
||||
\DrawInsnTypeSTikz{00000000000000000000000000000000}\\
|
||||
\DrawInsnTypeRShiftTikz{00000000000000000000000000000000}\\
|
||||
\DrawInsnTypeRTikz{00000000000000000000000000000000}
|
||||
\captionof{figure}{RISC-V instruction formats.}
|
||||
\label{Figure:riscvFormats}
|
||||
@ -301,7 +301,7 @@ the LSBs as discussed in \autoref{extension:zr}.
|
||||
If \Gls{xlen}=32 then the {\em imm} value example will extracted from the instruction
|
||||
and converted as shown below.
|
||||
|
||||
\DrawInsnOpUTypeDecoding
|
||||
\label{imm.u:decode}\DrawInsnOpUTypeDecoding
|
||||
|
||||
%If \Gls{xlen}=32 then the imm value in this example will be
|
||||
%converted as shown below.
|
||||
@ -364,7 +364,7 @@ value to \Gls{xlen} bits as discussed in \autoref{extension:slzr}.
|
||||
If \Gls{xlen}=32 then the {\em imm} value example will extracted from the instruction
|
||||
and converted as shown below.
|
||||
|
||||
\DrawInsnOpJTypeDecoding
|
||||
\label{imm.j:decode}\DrawInsnOpJTypeDecoding
|
||||
|
||||
%\DrawBitBoxSignLeftZeroRightExtendedPicture{32}{01000000110111001001}{1}
|
||||
%
|
||||
@ -383,18 +383,11 @@ counter. Since no instruction can be placed at an odd address the 20-bit
|
||||
imm value is zero-extended to the right to represent a 21-bit signed offset
|
||||
capable of representing numbers twice the magnitude of the 20-bit imm value.
|
||||
|
||||
|
||||
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
||||
\subsection{R Type}
|
||||
\label{insnformat:rtype}
|
||||
\DrawInsnTypeRTikz{01000001111100011000001110110011}
|
||||
|
||||
A special case of the R-type used for shift-immediate instructions where
|
||||
the {\em rs2} field is used as an immediate value named {\em shamt}
|
||||
representing the number of bit positions to shift:
|
||||
|
||||
\DrawInsnTypeRShiftTikz{00000000001000011001001110100011}
|
||||
|
||||
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
||||
\subsection{I Type}
|
||||
\label{insnformat:itype}
|
||||
@ -403,7 +396,14 @@ representing the number of bit positions to shift:
|
||||
If \Gls{xlen}=32 then the {\em imm} value example will extracted from the instruction
|
||||
and converted as shown below.
|
||||
|
||||
\DrawInsnOpITypeDecoding
|
||||
\label{imm.i:decode}\DrawInsnOpITypeDecoding
|
||||
|
||||
A special case of the I-type used for shift-immediate instructions where
|
||||
the {\em imm} field is used as an immediate value named {\em shamt}
|
||||
representing the number of bit positions to shift:
|
||||
|
||||
\label{shamt.i:decode}\DrawInsnOpIShiftTypeDecoding
|
||||
%\DrawInsnTypeIShiftTikz{00000000001000011001001110100011}
|
||||
|
||||
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
||||
\subsection{S Type}
|
||||
@ -413,7 +413,7 @@ and converted as shown below.
|
||||
If \Gls{xlen}=32 then the {\em imm} value example will extracted from the instruction
|
||||
and converted as shown below.
|
||||
|
||||
\DrawInsnOpSTypeDecoding
|
||||
\label{imm.s:decode}\DrawInsnOpSTypeDecoding
|
||||
|
||||
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
||||
\subsection{B Type}
|
||||
@ -423,7 +423,7 @@ and converted as shown below.
|
||||
If \Gls{xlen}=32 then the {\em imm} value example will extracted from the instruction
|
||||
and converted as shown below.
|
||||
|
||||
\DrawInsnOpBTypeDecoding
|
||||
\label{imm.b:decode}\DrawInsnOpBTypeDecoding
|
||||
|
||||
|
||||
%insnTypeF
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user