From 1bc441a4a2271e9c15af3ebe467a69696ed1d736 Mon Sep 17 00:00:00 2001 From: John Winans Date: Sun, 8 Mar 2020 21:00:37 -0500 Subject: [PATCH] Add minimal insn descriptions to the Instruction Encoding Formats section. --- book/rv32/chapter.tex | 542 +++++++++++++++++++++++++++++++++++++----- 1 file changed, 488 insertions(+), 54 deletions(-) diff --git a/book/rv32/chapter.tex b/book/rv32/chapter.tex index 0e1e2d2..263a522 100644 --- a/book/rv32/chapter.tex +++ b/book/rv32/chapter.tex @@ -1,3 +1,6 @@ + +\newcommand\instructionHeader[1]{{\large\tt \string#1}} + \chapter{RV32 Machine Instructions} \label{chapter:RV32} \index{RV32} @@ -247,26 +250,30 @@ immediate, register, base-displacement, pc-relative %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{Instruction Encoding Formats} \label{section:EncodingFormats} -This -\enote{Should discuss types and sizes beyond the fundamentals. Will add -if/when instruction details are added in the future.} -document concerns itself with the following RISC-V instruction formats. -XXX Show and discuss a stack of formats explaining how the unnatural ordering -of the {\em imm} fields reduces the number of possible locations that -the hardware has to be prepared to {\em look} for various bits. For example, -the opcode, rd, rs1, rs1, func3 and the sign bit (when used) are all always -in the same position. Also note that imm[19:12] and imm[10:5] can only be -found in one place. imm[4:0] can only be found in one of two places\ldots +%XXX Show and discuss a stack of formats explaining how the unnatural ordering +%of the {\em imm} fields reduces the number of possible locations that +%the hardware has to be prepared to {\em look} for various bits. For example, +%the opcode, rd, rs1, rs1, func3 and the sign bit (when used) are all always +%in the same position. Also note that imm[19:12] and imm[10:5] can only be +%found in one place. imm[4:0] can only be found in one of two places\ldots -The point to all this is that it is easier to build a machine if it -does not have to accommodate many different ways to perform the same task. -This simplification can also allow it operate faster. +The method/format of an instruction is designed with an eye on the ease +of future manufacture of the machine that will execute them. It is +easier to build a machine if it does not have to accommodate many different +ways to perform the same task. The result is that a machine can be +built with fewer gates, consumes less power, and can run faster than +if it were built when a priority is on how a user might prefer to decode +the same instructions from a hex dump. -\autoref{Figure:riscvFormats} Shows the RISC-V instruction formats. +This document concerns itself with the RISC-V instruction formats shown +in \autoref{Figure:riscvFormats}. + +%\autoref{Figure:riscvFormats} Shows the RISC-V instruction formats. \begin{figure}[ht] \DrawInsnTypeBTikz{00000000000000000000000000000000}\\ @@ -280,6 +287,9 @@ This simplification can also allow it operate faster. \label{Figure:riscvFormats} \end{figure} +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{U Type} \label{insnformat:utype} @@ -319,13 +329,39 @@ value suggests a rationale for the name of this format. %from $01010110000000000011_2$ (\verb@d6003@$_{16}$) to %$11010110000000000011000000000000_2$ (\verb@d6003000@$_{16}$). -If \Gls{xlen}=64 then the imm value in this example will be converted to the -same two's complement integer value by extending the sign to the left. -%\DrawBitBoxSignLeftZeroRightExtendedPicture{64}{11010110000000000011}{12} -%$1111111111111111111111111111111111010110000000000011000000000000_2$ -%(\verb@ffffffffd6003000@$_{16}$). +\begin{itemize} +\item\instructionHeader{lui\ \ \ rd,imm} +\label{insn:lui} +Set register \verb@rd@ to the \verb@imm_u@ value as shown in \autoref{Figure:u_type_decode}. + +For example: \verb@lui x23,0x12345@ will result in setting register \verb@x23@ to +the value \verb@0x12335000@. + +\item\instructionHeader{auipc rd,imm} +\label{insn:auipc} + +Add the address of the instruction to the \verb@imm_u@ value as +shown \autoref{Figure:u_type_decode} and store the result in register \verb@rd@. + +For example, if the instruction \verb@auipc x22,0x10001@ is executed from +memory address \verb@0x800012f4@ then register \verb@x22@ will be set to +\verb@0x900022f4@. +\end{itemize} + + + +If \Gls{xlen}=64 then the \verb@imm_u@ value in this example will be converted to the +same two's complement integer value by extending the sign-bit (indicated by \verb@a@ +in \autoref{Figure:u_type_decode}) to the left. + + + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{J Type} \label{insnformat:jtype} @@ -393,14 +429,121 @@ counter. Since no instruction can be placed at an odd address the 20-bit imm value is zero-extended to the right to represent a 21-bit signed offset capable of representing numbers twice the magnitude of the 20-bit imm value. +\begin{itemize} +\item\instructionHeader{jal\ \ \ rd,imm} +\label{insn:jal} + +Set register \verb@rd@ to the address of the next instruction that would +otherwise be executed (the address of the \verb@jal@ instruction + 4) and then +jump to an address given by the sum of the \verb@pc@ register and the +\verb@imm_j@ value as decoded from the instruction shown in \autoref{imm.j:decode}. + + + +\end{itemize} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{R Type} \label{insnformat:rtype} \DrawInsnTypeRTikz{01000001111100011000001110110011} +The R-type instructions are used for operations that set a destination +register \verb@rd@ to the result of an arithmetic, logical or shift operation +applied to source registers \verb@rs1@ and \verb@rs2@. + Note that bit 30 is used to select between the \verb@add@ and \verb@sub@ instructions as well as to select between arithmetic and logical shifting. +\begin{itemize} +\item\instructionHeader{add\ \ \ rd,rs1,rs2} +\label{insn:add} + +Set register \verb@rd@ to \verb@rs1 + rs2@. + +\item\instructionHeader{and\ \ \ rd,rs1,rs2} +\label{insn:and} + +Set register \verb@rd@ to the bitwise \verb@and@ of \verb@rs1@ and \verb@rs2@. + +For example, if \verb@x17@ = \verb@0x55551111@ and \verb@x18@ = \verb@0xff00ff00@ +then the instruction \verb@xor x12,x17,x18@ will set \verb@x12@ to the +value \verb@0x55001100@. + +\item\instructionHeader{or\ \ \ \ rd,rs1,rs2} +\label{insn:or} + +Set register \verb@rd@ to the bitwise \verb@or@ of \verb@rs1@ and \verb@rs2@. + +For example, if \verb@x17@ = \verb@0x55551111@ and \verb@x18@ = \verb@0xff00ff00@ +then the instruction \verb@xor x12,x17,x18@ will set \verb@x12@ to the +value \verb@0xff55ff11@. + +\item\instructionHeader{sll\ \ \ rd,rs1,rs2} +\label{insn:sll} + +Shift \verb@rs1@ left by the number of bits given in \verb@rs2@ and +store the result in \verb@rd@. + +For example, if \verb@x17@ = \verb@0x12345678@ and \verb@x18@ = \verb@0x08@ +then the instruction \verb@sll x12,x17,x18@ will set \verb@x12@ to the +value \verb@0x34567800@. + +\item\instructionHeader{slt\ \ \ rd,rs1,rs2} +\label{insn:slt} + +If the signed integer value in \verb@rs1@ is less than the +signed integer value in \verb@rs2@ then set \verb@rd@ to \verb@1@. +Otherwise, set \verb@rd@ to \verb@0@. + +\item\instructionHeader{sltu\ \ rd,rs1,rs2} +\label{insn:sltu} + +If the unsigned integer value in \verb@rs1@ is less than the +unsigned integer value in \verb@rs2@ then set \verb@rd@ to \verb@1@. +Otherwise, set \verb@rd@ to \verb@0@. + +\item\instructionHeader{sra\ \ \ rd,rs1,rs2} +\label{insn:sra} + +Logic-shift \verb@rs1@ right by the number of bits given in \verb@rs2@ and +store the result in \verb@rd@. + +For example, if \verb@x17@ = \verb@0x87654321@ and \verb@x18@ = \verb@0x08@ +then the instruction \verb@sll x12,x17,x18@ will set \verb@x12@ to the +value \verb@0xff876543@. + +\item\instructionHeader{srl\ \ \ rd,rs1,rs2} +\label{insn:srl} + +Logic-shift \verb@rs1@ right by the number of bits given in \verb@rs2@ and +store the result in \verb@rd@. + +For example, if \verb@x17@ = \verb@0x87654321@ and \verb@x18@ = \verb@0x08@ +then the instruction \verb@sll x12,x17,x18@ will set \verb@x12@ to the +value \verb@0x00876543@. + +\item\instructionHeader{sub\ \ \ rd,rs1,rs2} +\label{insn:sub} + +Set register \verb@rd@ to \verb@rs1 - rs2@. + +\item\instructionHeader{xor\ \ \ rd,rs1,rs2} +\label{insn:xor} + +Set register \verb@rd@ to the bitwise \verb@xor@ of \verb@rs1@ and \verb@rs2@. + +For example, if \verb@x17@ = \verb@0x55551111@ and \verb@x18@ = \verb@0xff00ff00@ +then the instruction \verb@xor x12,x17,x18@ will set \verb@x12@ to the +value \verb@0xaa55ee11@. + +\end{itemize} + + + %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{I Type} \label{insnformat:itype} @@ -419,7 +562,7 @@ and converted as shown in \autoref{Figure:i_type_decode}. \end{figure} A special case of the I-type used for shift-immediate instructions where -the {\em imm} field is used as an immediate value named {\em shamt} +the {\em imm} field is used as an immediate value named {\em shamt\_i} representing the number of bit positions to shift as shown in \autoref{Figure:shamt_i_type_decode}. @@ -434,7 +577,184 @@ representing the number of bit positions to shift as shown in Note that bit 30 is used to select between arithmetic and logical shifting. -%\DrawInsnTypeIShiftTikz{00000000001000011001001110100011} +\begin{figure}[ht] +\centering +\begin{verbatim} + 00002640: 6f 00 00 00 6f 00 00 00 b7 87 00 00 03 a5 07 43 *o...o..........C* + 00002650: 67 80 00 00 00 00 00 00 76 61 6c 3d 00 00 00 00 *g.......val=....* + 00002660: 00 00 00 00 80 84 2e 41 1f 85 45 41 80 40 9a 44 *.......A..EA.@.D* + 00002670: 4f 11 f3 c3 6e 8a 67 41 20 1b 00 00 20 1b 00 00 *O...n.gA ... ...* + 00002680: 44 1b 00 00 14 1b 00 00 14 1b 00 00 04 1c 00 00 *D...............* +\end{verbatim} +\captionof{figure}{An Example Memory Dump.} +\label{Figure:imm:memory:dump} +\end{figure} + + +\begin{itemize} +\item\instructionHeader{addi\ \ rd,rs1,imm} +\label{insn:addi} + +Set register \verb@rd@ to \verb@rs1 + imm_i@. + +\item\instructionHeader{andi\ \ rd,rs1,imm} +\label{insn:andi} + +Set register \verb@rd@ to the bitwise \verb@and@ of \verb@rs1@ and \verb@imm_i@. + +For example, if \verb@x17@ = \verb@0x55551111@ then the instruction +\verb@andi x12,x17,0x0ff@ will set \verb@x12@ to the value \verb@0x00000011@. + +Recall that \verb@imm@ is sign-extended. +Therefore if \verb@x17@ = \verb@0x55551111@ then the instruction +\verb@andi x12,x17,0x800@ will set \verb@x12@ to the value \verb@0x55551000@. + +\item\instructionHeader{jalr\ \ rd,rs1,imm} +\label{insn:jalr} + +Set register \verb@rd@ to the address of the next instruction that would +otherwise be executed (the address of the \verb@jalr@ instruction + 4) and then +jump to an address given by the sum of the \verb@pc@ register and the +\verb@imm_i@ value as decoded from the instruction shown in \autoref{imm.i:decode}. + +Note that the \verb@pc@ register can never refer to an odd address. +This instruction will explicitly set the \acrshort{lsb} to zero regardless +of the value of \verb@rs1@. + +\item\instructionHeader{lb\ \ \ \ rd,imm(rs1)} +\label{insn:lb} + +Set register \verb@rd@ to the value of the sign-extended byte fetched from +the memory address given by the sum of \verb@rs1@ and \verb@imm_i@. + +For example, given the memory contents shown in \autoref{Figure:imm:memory:dump}, +if register \verb@x13@ = \verb@0x00002650@ then the instruction +\verb@lb x12,1(x13)@ will set \verb@x12@ to the value \verb@0xffffff80@. + +\item\instructionHeader{lbu\ \ \ rd,imm(rs1)} +\label{insn:lbu} + +Set register \verb@rd@ to the value of the zero-extended byte fetched from +the memory address given by the sum of \verb@rs1@ and \verb@imm_i@. + +For example, given the memory contents shown in \autoref{Figure:imm:memory:dump}, +if register \verb@x13@ = \verb@0x00002650@ then the instruction +\verb@lb x12,1(x13)@ will set \verb@x12@ to the value \verb@0x00000080@. + +\item\instructionHeader{lh\ \ \ \ rd,imm(rs1)} +\label{insn:lh} + +Set register \verb@rd@ to the value of the sign-extended 16-bit little-endian +half-word value fetched from the memory address given by the sum +of \verb@rs1@ and \verb@imm_i@. + +For example, given the memory contents shown in \autoref{Figure:imm:memory:dump}, +if register \verb@x13@ = \verb@0x00002650@ then the instruction +\verb@lh x12,-2(x13)@ will set \verb@x12@ to the value \verb@0x00004307@. + +If register \verb@x13@ = \verb@0x00002650@ then the instruction +\verb@lh x12,-8(x13)@ will set \verb@x12@ to the value \verb@0xffff87b7@. + +\item\instructionHeader{lhu\ \ \ rd,imm(rs1)} +\label{insn:lhu} + +Set register \verb@rd@ to the value of the zero-extended 16-bit little-endian +half-word value fetched from the memory address given by the sum +of \verb@rs1@ and \verb@imm_i@. + +For example, given the memory contents shown in \autoref{Figure:imm:memory:dump}, +if register \verb@x13@ = \verb@0x00002650@ then the instruction +\verb@lhu x12,-2(x13)@ will set \verb@x12@ to the value \verb@0x00004307@. + +If register \verb@x13@ = \verb@0x00002650@ then the instruction +\verb@lhu x12,-8(x13)@ will set \verb@x12@ to the value \verb@0x000087b7@. + +\item\instructionHeader{lw\ \ \ \ rd,imm(rs1)} +\label{insn:lw} + +Set register \verb@rd@ to the value of the sign-extended 32-bit little-endian +word value fetched from the memory address given by the sum +of \verb@rs1@ and \verb@imm_i@. + +For example, given the memory contents shown in \autoref{Figure:imm:memory:dump}, +if register \verb@x13@ = \verb@0x00002650@ then the instruction +\verb@lh x12,-4(x13)@ will set \verb@x12@ to the value \verb@4307a503@. + + +\item\instructionHeader{ori\ \ \ rd,rs1,imm} +\label{insn:ori} + +Set register \verb@rd@ to the bitwise \verb@or@ of \verb@rs1@ and \verb@imm_i@. + +For example, if \verb@x17@ = \verb@0x55551111@ then the instruction +\verb@ori x12,x17,0x0ff@ will set \verb@x12@ to the value \verb@0x555511ff@. + +Recall that \verb@imm@ is sign-extended. +Therefore if \verb@x17@ = \verb@0x55551111@ then the instruction +\verb@ori x12,x17,0x800@ will set \verb@x12@ to the value \verb@0xfffff911@. + +\item\instructionHeader{slli\ \ rd,rs1,imm} +\label{insn:slli} + +Shift \verb@rs1@ left by the number of bits given in \verb@shamt_i@ +(as shown in \autoref{shamt.i:decode}) and store the result in \verb@rd@. + +For example, if \verb@x17@ = \verb@0x12345678@ then the instruction +\verb@slli x12,x17,4@ will set \verb@x12@ to the value \verb@0x23456780@. + +\item\instructionHeader{slti\ \ rd,rs1,imm} +\label{insn:slti} + +If the signed integer value in \verb@rs1@ is less than the +signed integer value in \verb@imm_i@ then set \verb@rd@ to \verb@1@. +Otherwise, set \verb@rd@ to \verb@0@. + +\item\instructionHeader{sltiu\ rd,rs1,imm} +\label{insn:sltiu} + +If the unsigned integer value in \verb@rs1@ is less than the +unsigned integer value in \verb@imm_i@ then set \verb@rd@ to \verb@1@. +Otherwise, set \verb@rd@ to \verb@0@. + +Note that \verb@imm_i@ is always created by sign-extending the \verb@imm@ value +as shown in \autoref{imm.i:decode} even though it is then later used as an unsigned +integer for the purposes of comparing its magnitude to the unsigned value in rs1. +Therefore, this instruction provides a method to compare \verb@rs1@ to a value +in the ranges of +$[\text{\tt 0}..\text{\tt 0x7ff}]$ and $[\text{\tt 0xfffff800}..\text{\tt 0xffffffff}]$. + +\item\instructionHeader{srai\ \ rd,rs1,imm} +\label{insn:srai} + +Arithmetic-shift \verb@rs1@ right by the number of bits given in \verb@shamt_i@ +(as shown in \autoref{shamt.i:decode}) and store the result in \verb@rd@. + +For example, if \verb@x17@ = \verb@0x87654321@ then the instruction +\verb@srai x12,x17,4@ will set \verb@x12@ to the value \verb@0xf8765432@. + +\item\instructionHeader{srli\ \ rd,rs1,imm} +\label{insn:srli} + +Logic-shift \verb@rs1@ right by the number of bits given in \verb@shamt_i@ +(as shown in \autoref{shamt.i:decode}) and store the result in \verb@rd@. + +For example, if \verb@x17@ = \verb@0x87654321@ then the instruction +\verb@srli x12,x17,4@ will set \verb@x12@ to the value \verb@0x08765432@. + +\item\instructionHeader{xori\ \ rd,rs1,imm} +\label{insn:xori} + +Set register \verb@rd@ to the bitwise \verb@xor@ of \verb@rs1@ and \verb@imm_i@. + +For example, if \verb@x17@ = \verb@0x55551111@ then the instruction +\verb@xori x12,x17,0x0ff@ will set \verb@x12@ to the value \verb@0x555511ee@. + +Recall that \verb@imm@ is sign-extended. +Therefore if \verb@x17@ = \verb@0x55551111@ then the instruction +\verb@xori x12,x17,0x800@ will set \verb@x12@ to the value \verb@0xaaaae911@. + +\end{itemize} + %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{S Type} @@ -453,6 +773,65 @@ and converted as shown \autoref{Figure:imm_s_type_decode}. \index{imm\protect\_s} \end{figure} +\begin{itemize} +\item\instructionHeader{sb\ \ \ \ rs2,imm(rs1)} +\label{insn:sb} + +Set the byte of memory at the address given by the sum of \verb@rs1@ and +\verb@imm_s@ to the 8 \acrshort{lsb}s of \verb@rs2@. + +For example, given the memory contents shown in \autoref{Figure:imm:memory:dump}, +if registers \verb@x13@ = \verb@0x00002650@ and \verb@x12@ = \verb@0x12345678@ +then the instruction \verb@sb x12,1(x13)@ will change the memory byte at address +\verb@0x00002651@ from \verb@0x80@ to \verb@0x78@ resulting in: + +\begin{verbatim} + 00002640: 6f 00 00 00 6f 00 00 00 b7 87 00 00 03 a5 07 43 *o...o..........C* + 00002650: 67 78 00 00 00 00 00 00 76 61 6c 3d 00 00 00 00 *gx......val=....* + 00002660: 00 00 00 00 80 84 2e 41 1f 85 45 41 80 40 9a 44 *.......A..EA.@.D* + 00002670: 4f 11 f3 c3 6e 8a 67 41 20 1b 00 00 20 1b 00 00 *O...n.gA ... ...* + 00002680: 44 1b 00 00 14 1b 00 00 14 1b 00 00 04 1c 00 00 *D...............* +\end{verbatim} + +\item\instructionHeader{sh\ \ \ \ rs2,imm(rs1)} +\label{insn:sh} + +Set the 16-bit half-word of memory at the address given by the sum of \verb@rs1@ and +\verb@imm_s@ to the 16 \acrshort{lsb}s of \verb@rs2@. + +For example, given the memory contents shown in \autoref{Figure:imm:memory:dump}, +if registers \verb@x13@ = \verb@0x00002650@ and \verb@x12@ = \verb@0x12345678@ +then the instruction \verb@sh x12,2(x13)@ will change the memory half-word at +address \verb@0x00002652@ from \verb@0x0000@ to \verb@0x5678@ resulting in: + +\begin{verbatim} + 00002640: 6f 00 00 00 6f 00 00 00 b7 87 00 00 03 a5 07 43 *o...o..........C* + 00002650: 67 80 78 56 00 00 00 00 76 61 6c 3d 00 00 00 00 *g.xV....val=....* + 00002660: 00 00 00 00 80 84 2e 41 1f 85 45 41 80 40 9a 44 *.......A..EA.@.D* + 00002670: 4f 11 f3 c3 6e 8a 67 41 20 1b 00 00 20 1b 00 00 *O...n.gA ... ...* + 00002680: 44 1b 00 00 14 1b 00 00 14 1b 00 00 04 1c 00 00 *D...............* +\end{verbatim} + +\item\instructionHeader{sw\ \ \ \ rs2,imm(rs1)} +\label{insn:sw} + +Set the 32-bit word of memory at the address given by the sum of \verb@rs1@ and +\verb@imm_s@ to the 16 \acrshort{lsb}s of \verb@rs2@. + +For example, given the memory contents shown in \autoref{Figure:imm:memory:dump}, +if registers \verb@x13@ = \verb@0x00002650@ and \verb@x12@ = \verb@0x12345678@ +then the instruction \verb@sw x12,0(x13)@ will change the memory word at address +\verb@0x00002650@ from \verb@0x00008067@ to \verb@0x12345678@ resulting in: + +\begin{verbatim} + 00002640: 6f 00 00 00 6f 00 00 00 b7 87 00 00 03 a5 07 43 *o...o..........C* + 00002650: 78 56 34 12 00 00 00 00 76 61 6c 3d 00 00 00 00 *xV4.....val=....* + 00002660: 00 00 00 00 80 84 2e 41 1f 85 45 41 80 40 9a 44 *.......A..EA.@.D* + 00002670: 4f 11 f3 c3 6e 8a 67 41 20 1b 00 00 20 1b 00 00 *O...n.gA ... ...* + 00002680: 44 1b 00 00 14 1b 00 00 14 1b 00 00 04 1c 00 00 *D...............* +\end{verbatim} + +\end{itemize} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{B Type} @@ -471,6 +850,60 @@ and converted as shown in \autoref{Figure:imm_b_type_decode}. \index{imm\protect\_b} \end{figure} +\begin{itemize} +\item\instructionHeader{beq\ \ \ rs1,rs2,imm} +\label{insn:beq} + +If \verb@rs1@ is equal to \verb@rs2@ then add \verb@imm_b@ to the +\verb@pc@ register. + +\item\instructionHeader{bge\ \ \ rs1,rs2,imm} +\label{insn:bge} + +If the signed value in \verb@rs1@ is greater than or euqal to the +signed value in \verb@rs2@ then add \verb@imm_b@ to the +\verb@pc@ register. + +\item\instructionHeader{bgeu\ \ \ rs1,rs2,imm} +\label{insn:bgeu} + +If the unsigned value in \verb@rs1@ is greater than or euqal to the +unsigned value in \verb@rs2@ then add \verb@imm_b@ to the +\verb@pc@ register. + +\item\instructionHeader{blt\ \ \ rs1,rs2,imm} +\label{insn:blt} + +If the signed value in \verb@rs1@ is less than the +signed value in \verb@rs2@ then add \verb@imm_b@ to the +\verb@pc@ register. + +\item\instructionHeader{bltu\ \ \ rs1,rs2,imm} +\label{insn:bltu} + +If the unsigned value in \verb@rs1@ is less than the +unsigned value in \verb@rs2@ then add \verb@imm_b@ to the +\verb@pc@ register. + +\item\instructionHeader{bne\ \ \ rs1,rs2,imm} +\label{insn:bne} + +If \verb@rs1@ is not equal to \verb@rs2@ then add \verb@imm_b@ to the +\verb@pc@ register. + +\end{itemize} + +%\label{insn:bgt} +%\label{insn:ble} +%\label{insn:bgtu} +%\label{insn:beqz} +%\label{insn:bnez} +%\label{insn:blez} +%\label{insn:bgez} +%\label{insn:bltz} +%\label{insn:bgtz} + + %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{CPU Registers} \label{cpuregs} @@ -497,41 +930,41 @@ in the compressed format. \begin{center} \begin{tabular}{|l|l|l|l|} \hline -Reg & Alias & Description & Saved \\ +Reg & Alias & Description & Saved \\ \hline \hline -x0 & zero & Hard-wired zero & \\ -x1 & ra & Return address & \\ -x2 & sp & Stack pointer & yes \\ -x3 & gp & Global pointer & \\ -x4 & tp & Thread pointer & \\ -x5 & t0 & Temporary/alternate link register & \\ -x6 & t1 & Temporary & \\ -x7 & t2 & Temporary & \\ -x8 & s0/fp & Saved register/frame pointer & yes \\ -x9 & s1 & Saved register & yes \\ -x10 & a0 & Function argument/return value & \\ -x11 & a1 & Function argument/return value & \\ -x12 & a2 & Function argument & \\ -x13 & a3 & Function argument & \\ -x14 & a4 & Function argument & \\ -x15 & a5 & Function argument & \\ -x16 & a6 & Function argument & \\ -x17 & a7 & Function argument & \\ -x18 & s2 & Saved register & yes \\ -x19 & s3 & Saved register & yes \\ -x20 & s4 & Saved register & yes \\ -x21 & s5 & Saved register & yes \\ -x22 & s6 & Saved register & yes \\ -x23 & s7 & Saved register & yes \\ -x24 & s8 & Saved register & yes \\ -x25 & s9 & Saved register & yes \\ -x26 & s10 & Saved register & yes \\ -x27 & s11 & Saved register & yes \\ -x28 & t3 & Temporary & \\ -x29 & t4 & Temporary & \\ -x30 & t5 & Temporary & \\ -x31 & t6 & Temporary & \\ +x0 & zero & Hard-wired zero & \\ +x1 & ra & Return address & \\ +x2 & sp & Stack pointer & yes \\ +x3 & gp & Global pointer & \\ +x4 & tp & Thread pointer & \\ +x5 & t0 & Temporary/alternate link register & \\ +x6 & t1 & Temporary & \\ +x7 & t2 & Temporary & \\ +x8 & s0/fp & Saved register/frame pointer & yes \\ +x9 & s1 & Saved register & yes \\ +x10 & a0 & Function argument/return value & \\ +x11 & a1 & Function argument/return value & \\ +x12 & a2 & Function argument & \\ +x13 & a3 & Function argument & \\ +x14 & a4 & Function argument & \\ +x15 & a5 & Function argument & \\ +x16 & a6 & Function argument & \\ +x17 & a7 & Function argument & \\ +x18 & s2 & Saved register & yes \\ +x19 & s3 & Saved register & yes \\ +x20 & s4 & Saved register & yes \\ +x21 & s5 & Saved register & yes \\ +x22 & s6 & Saved register & yes \\ +x23 & s7 & Saved register & yes \\ +x24 & s8 & Saved register & yes \\ +x25 & s9 & Saved register & yes \\ +x26 & s10 & Saved register & yes \\ +x27 & s11 & Saved register & yes \\ +x28 & t3 & Temporary & \\ +x29 & t4 & Temporary & \\ +x30 & t5 & Temporary & \\ +x31 & t6 & Temporary & \\ \hline \end{tabular} \end{center} @@ -585,6 +1018,7 @@ When XLEN is 64 or 128, the immediate value is sign-extended to the left. \input{insn/lui.tex} + %Instruction Format and Example: % %\DrawInsnTypeUPicture{LUI t0, 3}{00000000000000000011001010110111}